From 23e6a7ca464ed2b9d949520e07f7e0735bc025f4 Mon Sep 17 00:00:00 2001 From: Randy Dunlap Date: Fri, 23 Jul 2021 11:25:58 -0700 Subject: mailbox: sti: quieten kernel-doc warnings Use kernel-doc struct notation for the mailbox structs to prevent these kernel-doc warnings: drivers/mailbox/mailbox-sti.c:39: warning: This comment starts with '/**', but isn't a kernel-doc comment. Refer Documentation/doc-guide/kernel-doc.rst * STi Mailbox device data drivers/mailbox/mailbox-sti.c:63: warning: This comment starts with '/**', but isn't a kernel-doc comment. Refer Documentation/doc-guide/kernel-doc.rst * STi Mailbox platform specific configuration drivers/mailbox/mailbox-sti.c:74: warning: This comment starts with '/**', but isn't a kernel-doc comment. Refer Documentation/doc-guide/kernel-doc.rst * STi Mailbox allocated channel information Also move the field descriptions ahead of the function description as is expected in kernel-doc. This prevents another kernel-doc warning. Fixes: 9ef4546cbd7e ("mailbox: Add support for ST's Mailbox IP") Signed-off-by: Randy Dunlap Reported-by: kernel test robot Cc: Aditya Srivastava Cc: Lee Jones Signed-off-by: Jassi Brar --- drivers/mailbox/mailbox-sti.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) (limited to 'drivers/mailbox') diff --git a/drivers/mailbox/mailbox-sti.c b/drivers/mailbox/mailbox-sti.c index 2baf69a0b81c..ab3a6ab762d3 100644 --- a/drivers/mailbox/mailbox-sti.c +++ b/drivers/mailbox/mailbox-sti.c @@ -36,12 +36,7 @@ #define MBOX_BASE(mdev, inst) ((mdev)->base + ((inst) * 4)) /** - * STi Mailbox device data - * - * An IP Mailbox is currently composed of 4 instances - * Each instance is currently composed of 32 channels - * This means that we have 128 channels per Mailbox - * A channel an be used for TX or RX + * struct sti_mbox_device - STi Mailbox device data * * @dev: Device to which it is attached * @mbox: Representation of a communication channel controller @@ -49,6 +44,11 @@ * @name: Name of the mailbox * @enabled: Local copy of enabled channels * @lock: Mutex protecting enabled status + * + * An IP Mailbox is currently composed of 4 instances + * Each instance is currently composed of 32 channels + * This means that we have 128 channels per Mailbox + * A channel an be used for TX or RX */ struct sti_mbox_device { struct device *dev; @@ -60,7 +60,7 @@ struct sti_mbox_device { }; /** - * STi Mailbox platform specific configuration + * struct sti_mbox_pdata - STi Mailbox platform specific configuration * * @num_inst: Maximum number of instances in one HW Mailbox * @num_chan: Maximum number of channel per instance @@ -71,7 +71,7 @@ struct sti_mbox_pdata { }; /** - * STi Mailbox allocated channel information + * struct sti_channel - STi Mailbox allocated channel information * * @mdev: Pointer to parent Mailbox device * @instance: Instance number channel resides in -- cgit 1.4.1 From 8d7e5908c0bcf8a0abc437385e58e49abab11a93 Mon Sep 17 00:00:00 2001 From: Amit Pundir Date: Fri, 16 Jul 2021 13:19:46 +0530 Subject: mailbox: qcom-ipcc: Enable loading QCOM_IPCC as a module This patch enables the qcom_ipcc driver to be loaded as a module. IPCC is fairly core to system, so as such it should never be unloaded. It registers as a mailbox + irq controller and the irq controller drivers in kernel are not supposed to be unloaded as they don't have the visibility over the clients consuming the irqs. Hence adding supress_bind_attrs to disable bind/unbind via sysfs. Signed-off-by: Amit Pundir Reviewed-by: Manivannan Sadhasivam Signed-off-by: Jassi Brar --- drivers/mailbox/Kconfig | 2 +- drivers/mailbox/qcom-ipcc.c | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) (limited to 'drivers/mailbox') diff --git a/drivers/mailbox/Kconfig b/drivers/mailbox/Kconfig index b4b780ea2ac8..c9fc06c7e685 100644 --- a/drivers/mailbox/Kconfig +++ b/drivers/mailbox/Kconfig @@ -264,7 +264,7 @@ config SPRD_MBOX you want to build the Spreatrum mailbox controller driver. config QCOM_IPCC - bool "Qualcomm Technologies, Inc. IPCC driver" + tristate "Qualcomm Technologies, Inc. IPCC driver" depends on ARCH_QCOM || COMPILE_TEST help Qualcomm Technologies, Inc. Inter-Processor Communication Controller diff --git a/drivers/mailbox/qcom-ipcc.c b/drivers/mailbox/qcom-ipcc.c index 584700cd1585..f1d4f4679b17 100644 --- a/drivers/mailbox/qcom-ipcc.c +++ b/drivers/mailbox/qcom-ipcc.c @@ -277,6 +277,7 @@ static struct platform_driver qcom_ipcc_driver = { .driver = { .name = "qcom-ipcc", .of_match_table = qcom_ipcc_of_match, + .suppress_bind_attrs = true, }, }; -- cgit 1.4.1 From 84fd4201b78b96f8d31f6a2624be27ad6306a9bc Mon Sep 17 00:00:00 2001 From: Yongqiang Niu Date: Mon, 2 Aug 2021 15:46:05 +0800 Subject: mailbox: cmdq: add mt8192 support add mt8192 support Signed-off-by: Yongqiang Niu Signed-off-by: Hsin-Yi Wang Signed-off-by: Jassi Brar --- drivers/mailbox/mtk-cmdq-mailbox.c | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'drivers/mailbox') diff --git a/drivers/mailbox/mtk-cmdq-mailbox.c b/drivers/mailbox/mtk-cmdq-mailbox.c index 67a42b514429..8d39b988df9e 100644 --- a/drivers/mailbox/mtk-cmdq-mailbox.c +++ b/drivers/mailbox/mtk-cmdq-mailbox.c @@ -36,6 +36,8 @@ #define CMDQ_THR_WAIT_TOKEN 0x30 #define CMDQ_THR_PRIORITY 0x40 +#define GCE_GCTL_VALUE 0x48 + #define CMDQ_THR_ACTIVE_SLOT_CYCLES 0x3200 #define CMDQ_THR_ENABLED 0x1 #define CMDQ_THR_DISABLED 0x0 @@ -76,11 +78,13 @@ struct cmdq { struct clk *clock; bool suspended; u8 shift_pa; + bool control_by_sw; }; struct gce_plat { u32 thread_nr; u8 shift; + bool control_by_sw; }; u8 cmdq_get_shift_pa(struct mbox_chan *chan) @@ -121,6 +125,8 @@ static void cmdq_init(struct cmdq *cmdq) int i; WARN_ON(clk_enable(cmdq->clock) < 0); + if (cmdq->control_by_sw) + writel(0x7, cmdq->base + GCE_GCTL_VALUE); writel(CMDQ_THR_ACTIVE_SLOT_CYCLES, cmdq->base + CMDQ_THR_SLOT_CYCLES); for (i = 0; i <= CMDQ_MAX_EVENT; i++) writel(i, cmdq->base + CMDQ_SYNC_TOKEN_UPDATE); @@ -540,6 +546,7 @@ static int cmdq_probe(struct platform_device *pdev) cmdq->thread_nr = plat_data->thread_nr; cmdq->shift_pa = plat_data->shift; + cmdq->control_by_sw = plat_data->control_by_sw; cmdq->irq_mask = GENMASK(cmdq->thread_nr - 1, 0); err = devm_request_irq(dev, cmdq->irq, cmdq_irq_handler, IRQF_SHARED, "mtk_cmdq", cmdq); @@ -605,11 +612,14 @@ static const struct dev_pm_ops cmdq_pm_ops = { static const struct gce_plat gce_plat_v2 = {.thread_nr = 16}; static const struct gce_plat gce_plat_v3 = {.thread_nr = 24}; static const struct gce_plat gce_plat_v4 = {.thread_nr = 24, .shift = 3}; +static const struct gce_plat gce_plat_v5 = {.thread_nr = 24, .shift = 3, + .control_by_sw = true}; static const struct of_device_id cmdq_of_ids[] = { {.compatible = "mediatek,mt8173-gce", .data = (void *)&gce_plat_v2}, {.compatible = "mediatek,mt8183-gce", .data = (void *)&gce_plat_v3}, {.compatible = "mediatek,mt6779-gce", .data = (void *)&gce_plat_v4}, + {.compatible = "mediatek,mt8192-gce", .data = (void *)&gce_plat_v5}, {} }; -- cgit 1.4.1 From 8b60ed2b1674b78ebc433a11efa7d48821229037 Mon Sep 17 00:00:00 2001 From: Yongqiang Niu Date: Mon, 2 Aug 2021 15:52:26 +0800 Subject: soc: mediatek: cmdq: add address shift in jump Add address shift when compose jump instruction to compatible with 35bit format. Fixes: 0858fde496f8 ("mailbox: cmdq: variablize address shift in platform") Signed-off-by: Yongqiang Niu Reviewed-by: Nicolas Boichat Signed-off-by: Jassi Brar --- drivers/mailbox/mtk-cmdq-mailbox.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'drivers/mailbox') diff --git a/drivers/mailbox/mtk-cmdq-mailbox.c b/drivers/mailbox/mtk-cmdq-mailbox.c index 8d39b988df9e..d03bfafe05b4 100644 --- a/drivers/mailbox/mtk-cmdq-mailbox.c +++ b/drivers/mailbox/mtk-cmdq-mailbox.c @@ -174,7 +174,8 @@ static void cmdq_task_insert_into_thread(struct cmdq_task *task) dma_sync_single_for_cpu(dev, prev_task->pa_base, prev_task->pkt->cmd_buf_size, DMA_TO_DEVICE); prev_task_base[CMDQ_NUM_CMD(prev_task->pkt) - 1] = - (u64)CMDQ_JUMP_BY_PA << 32 | task->pa_base; + (u64)CMDQ_JUMP_BY_PA << 32 | + (task->pa_base >> task->cmdq->shift_pa); dma_sync_single_for_device(dev, prev_task->pa_base, prev_task->pkt->cmd_buf_size, DMA_TO_DEVICE); -- cgit 1.4.1 From dc2b8edfa3b3e691fa43694c4bd1e16b682393e1 Mon Sep 17 00:00:00 2001 From: Iskren Chernev Date: Sun, 27 Jun 2021 21:58:28 +0300 Subject: mailbox: qcom: Add support for SM6115 APCS IPC Qcom SM4250/6115, have APCS mailbox setup similar to msm8998 and msm8916. Signed-off-by: Iskren Chernev Signed-off-by: Jassi Brar --- drivers/mailbox/qcom-apcs-ipc-mailbox.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/mailbox') diff --git a/drivers/mailbox/qcom-apcs-ipc-mailbox.c b/drivers/mailbox/qcom-apcs-ipc-mailbox.c index 03bdc96dc457..f51594208adb 100644 --- a/drivers/mailbox/qcom-apcs-ipc-mailbox.c +++ b/drivers/mailbox/qcom-apcs-ipc-mailbox.c @@ -173,6 +173,7 @@ static const struct of_device_id qcom_apcs_ipc_of_match[] = { { .compatible = "qcom,sdm845-apss-shared", .data = &apps_shared_apcs_data }, { .compatible = "qcom,sm6125-apcs-hmss-global", .data = &sm6125_apcs_data }, { .compatible = "qcom,sm8150-apss-shared", .data = &apps_shared_apcs_data }, + { .compatible = "qcom,sm6115-apcs-hmss-global", .data = &sdm660_apcs_data }, { .compatible = "qcom,sdx55-apcs-gcc", .data = &sdx55_apcs_data }, {} }; -- cgit 1.4.1 From e5c11ee3106072ef4b949eca93db160f55e6b55b Mon Sep 17 00:00:00 2001 From: Vladimir Lypak Date: Tue, 10 Aug 2021 16:44:33 +0000 Subject: mailbox: qcom-apcs-ipc: Add compatible for MSM8953 SoC MSM8953 has an APCS block similar to MSM8916 but with different clocks which are spread over 2MB IO region next to it. Signed-off-by: Vladimir Lypak Signed-off-by: Sireesh Kodali Signed-off-by: Jassi Brar --- drivers/mailbox/qcom-apcs-ipc-mailbox.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/mailbox') diff --git a/drivers/mailbox/qcom-apcs-ipc-mailbox.c b/drivers/mailbox/qcom-apcs-ipc-mailbox.c index f51594208adb..82ccfaf14b24 100644 --- a/drivers/mailbox/qcom-apcs-ipc-mailbox.c +++ b/drivers/mailbox/qcom-apcs-ipc-mailbox.c @@ -163,6 +163,7 @@ static const struct of_device_id qcom_apcs_ipc_of_match[] = { { .compatible = "qcom,ipq8074-apcs-apps-global", .data = &ipq8074_apcs_data }, { .compatible = "qcom,msm8916-apcs-kpss-global", .data = &msm8916_apcs_data }, { .compatible = "qcom,msm8939-apcs-kpss-global", .data = &msm8916_apcs_data }, + { .compatible = "qcom,msm8953-apcs-kpss-global", .data = &msm8994_apcs_data }, { .compatible = "qcom,msm8994-apcs-kpss-global", .data = &msm8994_apcs_data }, { .compatible = "qcom,msm8996-apcs-hmss-global", .data = &msm8996_apcs_data }, { .compatible = "qcom,msm8998-apcs-hmss-global", .data = &msm8998_apcs_data }, -- cgit 1.4.1 From 8d4f5a9e012abb7919f7b63656ea571f22789918 Mon Sep 17 00:00:00 2001 From: "jason-jh.lin" Date: Tue, 31 Aug 2021 15:09:02 +0800 Subject: mailbox: cmdq: add mediatek mailbox support for mt8195 Add mt8195 compatible name in the driver data of cmdq mailbox driver. Signed-off-by: jason-jh.lin Signed-off-by: Jassi Brar --- drivers/mailbox/mtk-cmdq-mailbox.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/mailbox') diff --git a/drivers/mailbox/mtk-cmdq-mailbox.c b/drivers/mailbox/mtk-cmdq-mailbox.c index d03bfafe05b4..8ca3fa00dcfb 100644 --- a/drivers/mailbox/mtk-cmdq-mailbox.c +++ b/drivers/mailbox/mtk-cmdq-mailbox.c @@ -621,6 +621,7 @@ static const struct of_device_id cmdq_of_ids[] = { {.compatible = "mediatek,mt8183-gce", .data = (void *)&gce_plat_v3}, {.compatible = "mediatek,mt6779-gce", .data = (void *)&gce_plat_v4}, {.compatible = "mediatek,mt8192-gce", .data = (void *)&gce_plat_v5}, + {.compatible = "mediatek,mt8195-gce", .data = (void *)&gce_plat_v4}, {} }; -- cgit 1.4.1 From 85dfdbfc13ea9614a2168ce4a7d2cd089d84cb64 Mon Sep 17 00:00:00 2001 From: "jason-jh.lin" Date: Tue, 31 Aug 2021 15:09:03 +0800 Subject: mailbox: cmdq: add multi-gce clocks support for mt8195 For the design of GCE hardware event signal transportation, evnet rx will send the event signal to all GCE event merges after receiving the event signal from the other hardware. Because GCE event merges need to response to event rx, their clocks must be enabled at that time. To make sure all the gce clock is enabled while receiving the hardware event, each cmdq mailbox should enable or disable the others gce clk at the same time. Signed-off-by: jason-jh.lin Signed-off-by: Jassi Brar --- drivers/mailbox/mtk-cmdq-mailbox.c | 101 +++++++++++++++++++++++++++++-------- 1 file changed, 79 insertions(+), 22 deletions(-) (limited to 'drivers/mailbox') diff --git a/drivers/mailbox/mtk-cmdq-mailbox.c b/drivers/mailbox/mtk-cmdq-mailbox.c index 8ca3fa00dcfb..64175a893312 100644 --- a/drivers/mailbox/mtk-cmdq-mailbox.c +++ b/drivers/mailbox/mtk-cmdq-mailbox.c @@ -19,6 +19,7 @@ #define CMDQ_OP_CODE_MASK (0xff << CMDQ_OP_CODE_SHIFT) #define CMDQ_NUM_CMD(t) (t->cmd_buf_size / CMDQ_INST_SIZE) +#define CMDQ_GCE_NUM_MAX (2) #define CMDQ_CURR_IRQ_STATUS 0x10 #define CMDQ_SYNC_TOKEN_UPDATE 0x68 @@ -75,16 +76,18 @@ struct cmdq { u32 thread_nr; u32 irq_mask; struct cmdq_thread *thread; - struct clk *clock; + struct clk_bulk_data clocks[CMDQ_GCE_NUM_MAX]; bool suspended; u8 shift_pa; bool control_by_sw; + u32 gce_num; }; struct gce_plat { u32 thread_nr; u8 shift; bool control_by_sw; + u32 gce_num; }; u8 cmdq_get_shift_pa(struct mbox_chan *chan) @@ -124,13 +127,13 @@ static void cmdq_init(struct cmdq *cmdq) { int i; - WARN_ON(clk_enable(cmdq->clock) < 0); + WARN_ON(clk_bulk_enable(cmdq->gce_num, cmdq->clocks)); if (cmdq->control_by_sw) writel(0x7, cmdq->base + GCE_GCTL_VALUE); writel(CMDQ_THR_ACTIVE_SLOT_CYCLES, cmdq->base + CMDQ_THR_SLOT_CYCLES); for (i = 0; i <= CMDQ_MAX_EVENT; i++) writel(i, cmdq->base + CMDQ_SYNC_TOKEN_UPDATE); - clk_disable(cmdq->clock); + clk_bulk_disable(cmdq->gce_num, cmdq->clocks); } static int cmdq_thread_reset(struct cmdq *cmdq, struct cmdq_thread *thread) @@ -269,7 +272,7 @@ static void cmdq_thread_irq_handler(struct cmdq *cmdq, if (list_empty(&thread->task_busy_list)) { cmdq_thread_disable(cmdq, thread); - clk_disable(cmdq->clock); + clk_bulk_disable(cmdq->gce_num, cmdq->clocks); } } @@ -314,7 +317,7 @@ static int cmdq_suspend(struct device *dev) if (task_running) dev_warn(dev, "exist running task(s) in suspend\n"); - clk_unprepare(cmdq->clock); + clk_bulk_unprepare(cmdq->gce_num, cmdq->clocks); return 0; } @@ -323,7 +326,7 @@ static int cmdq_resume(struct device *dev) { struct cmdq *cmdq = dev_get_drvdata(dev); - WARN_ON(clk_prepare(cmdq->clock) < 0); + WARN_ON(clk_bulk_prepare(cmdq->gce_num, cmdq->clocks)); cmdq->suspended = false; return 0; } @@ -332,8 +335,7 @@ static int cmdq_remove(struct platform_device *pdev) { struct cmdq *cmdq = platform_get_drvdata(pdev); - clk_unprepare(cmdq->clock); - + clk_bulk_unprepare(cmdq->gce_num, cmdq->clocks); return 0; } @@ -359,7 +361,8 @@ static int cmdq_mbox_send_data(struct mbox_chan *chan, void *data) task->pkt = pkt; if (list_empty(&thread->task_busy_list)) { - WARN_ON(clk_enable(cmdq->clock) < 0); + WARN_ON(clk_bulk_enable(cmdq->gce_num, cmdq->clocks)); + /* * The thread reset will clear thread related register to 0, * including pc, end, priority, irq, suspend and enable. Thus @@ -431,7 +434,8 @@ static void cmdq_mbox_shutdown(struct mbox_chan *chan) } cmdq_thread_disable(cmdq, thread); - clk_disable(cmdq->clock); + clk_bulk_disable(cmdq->gce_num, cmdq->clocks); + done: /* * The thread->task_busy_list empty means thread already disable. The @@ -476,7 +480,7 @@ static int cmdq_mbox_flush(struct mbox_chan *chan, unsigned long timeout) cmdq_thread_resume(thread); cmdq_thread_disable(cmdq, thread); - clk_disable(cmdq->clock); + clk_bulk_disable(cmdq->gce_num, cmdq->clocks); out: spin_unlock_irqrestore(&thread->chan->lock, flags); @@ -525,6 +529,10 @@ static int cmdq_probe(struct platform_device *pdev) struct cmdq *cmdq; int err, i; struct gce_plat *plat_data; + struct device_node *phandle = dev->of_node; + struct device_node *node; + int alias_id = 0; + char clk_name[4] = "gce"; cmdq = devm_kzalloc(dev, sizeof(*cmdq), GFP_KERNEL); if (!cmdq) @@ -548,6 +556,7 @@ static int cmdq_probe(struct platform_device *pdev) cmdq->thread_nr = plat_data->thread_nr; cmdq->shift_pa = plat_data->shift; cmdq->control_by_sw = plat_data->control_by_sw; + cmdq->gce_num = plat_data->gce_num; cmdq->irq_mask = GENMASK(cmdq->thread_nr - 1, 0); err = devm_request_irq(dev, cmdq->irq, cmdq_irq_handler, IRQF_SHARED, "mtk_cmdq", cmdq); @@ -559,10 +568,28 @@ static int cmdq_probe(struct platform_device *pdev) dev_dbg(dev, "cmdq device: addr:0x%p, va:0x%p, irq:%d\n", dev, cmdq->base, cmdq->irq); - cmdq->clock = devm_clk_get(dev, "gce"); - if (IS_ERR(cmdq->clock)) { - dev_err(dev, "failed to get gce clk\n"); - return PTR_ERR(cmdq->clock); + if (cmdq->gce_num > 1) { + for_each_child_of_node(phandle->parent, node) { + char clk_id[8]; + + alias_id = of_alias_get_id(node, clk_name); + if (alias_id < cmdq->gce_num) { + snprintf(clk_id, sizeof(clk_id), "%s%d", clk_name, alias_id); + cmdq->clocks[alias_id].id = clk_id; + cmdq->clocks[alias_id].clk = of_clk_get(node, 0); + if (IS_ERR(cmdq->clocks[alias_id].clk)) { + dev_err(dev, "failed to get gce clk: %d\n", alias_id); + return PTR_ERR(cmdq->clocks[alias_id].clk); + } + } + } + } else { + cmdq->clocks[alias_id].id = clk_name; + cmdq->clocks[alias_id].clk = devm_clk_get(&pdev->dev, clk_name); + if (IS_ERR(cmdq->clocks[alias_id].clk)) { + dev_err(dev, "failed to get gce clk\n"); + return PTR_ERR(cmdq->clocks[alias_id].clk); + } } cmdq->mbox.dev = dev; @@ -598,7 +625,8 @@ static int cmdq_probe(struct platform_device *pdev) } platform_set_drvdata(pdev, cmdq); - WARN_ON(clk_prepare(cmdq->clock) < 0); + + WARN_ON(clk_bulk_prepare(cmdq->gce_num, cmdq->clocks)); cmdq_init(cmdq); @@ -610,18 +638,47 @@ static const struct dev_pm_ops cmdq_pm_ops = { .resume = cmdq_resume, }; -static const struct gce_plat gce_plat_v2 = {.thread_nr = 16}; -static const struct gce_plat gce_plat_v3 = {.thread_nr = 24}; -static const struct gce_plat gce_plat_v4 = {.thread_nr = 24, .shift = 3}; -static const struct gce_plat gce_plat_v5 = {.thread_nr = 24, .shift = 3, - .control_by_sw = true}; +static const struct gce_plat gce_plat_v2 = { + .thread_nr = 16, + .shift = 0, + .control_by_sw = false, + .gce_num = 1 +}; + +static const struct gce_plat gce_plat_v3 = { + .thread_nr = 24, + .shift = 0, + .control_by_sw = false, + .gce_num = 1 +}; + +static const struct gce_plat gce_plat_v4 = { + .thread_nr = 24, + .shift = 3, + .control_by_sw = false, + .gce_num = 1 +}; + +static const struct gce_plat gce_plat_v5 = { + .thread_nr = 24, + .shift = 3, + .control_by_sw = true, + .gce_num = 2 +}; + +static const struct gce_plat gce_plat_v6 = { + .thread_nr = 24, + .shift = 3, + .control_by_sw = false, + .gce_num = 2 +}; static const struct of_device_id cmdq_of_ids[] = { {.compatible = "mediatek,mt8173-gce", .data = (void *)&gce_plat_v2}, {.compatible = "mediatek,mt8183-gce", .data = (void *)&gce_plat_v3}, {.compatible = "mediatek,mt6779-gce", .data = (void *)&gce_plat_v4}, {.compatible = "mediatek,mt8192-gce", .data = (void *)&gce_plat_v5}, - {.compatible = "mediatek,mt8195-gce", .data = (void *)&gce_plat_v4}, + {.compatible = "mediatek,mt8195-gce", .data = (void *)&gce_plat_v6}, {} }; -- cgit 1.4.1