From 87366d8cf7b3f6dc34633938aa8766e5a390ce33 Mon Sep 17 00:00:00 2001 From: Radha Mohan Chintakuntla Date: Fri, 7 Mar 2014 08:49:25 +0000 Subject: arm64: Add boot time configuration of Intermediate Physical Address size ARMv8 supports a range of physical address bit sizes. The PARange bits from ID_AA64MMFR0_EL1 register are read during boot-time and the intermediate physical address size bits are written in the translation control registers (TCR_EL1 and VTCR_EL2). There is no change in the VA bits and levels of translation. Signed-off-by: Radha Mohan Chintakuntla Reviewed-by: Will Deacon Acked-by: Marc Zyngier Signed-off-by: Catalin Marinas --- arch/arm64/kvm/hyp-init.S | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch/arm64/kvm') diff --git a/arch/arm64/kvm/hyp-init.S b/arch/arm64/kvm/hyp-init.S index 2b0244d65c16..d968796f4b2d 100644 --- a/arch/arm64/kvm/hyp-init.S +++ b/arch/arm64/kvm/hyp-init.S @@ -68,6 +68,12 @@ __do_hyp_init: msr tcr_el2, x4 ldr x4, =VTCR_EL2_FLAGS + /* + * Read the PARange bits from ID_AA64MMFR0_EL1 and set the PS bits in + * VTCR_EL2. + */ + mrs x5, ID_AA64MMFR0_EL1 + bfi x4, x5, #16, #3 msr vtcr_el2, x4 mrs x4, mair_el1 -- cgit 1.4.1