From d091fcb97ff48a5cb6de19ad0881fb2c8e76dbc0 Mon Sep 17 00:00:00 2001 From: Vineet Gupta Date: Mon, 17 Jun 2013 19:44:06 +0530 Subject: ARC: MMUv4 preps/2 - Reshuffle PTE bits With previous commit freeing up PTE bits, reassign them so as to: - Match the bit to H/w counterpart where possible (e.g. MMUv2 GLOBAL/PRESENT, this avoids a shift in create_tlb()) - Avoid holes in _PAGE_xxx definitions Signed-off-by: Vineet Gupta --- arch/arc/mm/tlbex.S | 3 --- 1 file changed, 3 deletions(-) (limited to 'arch/arc/mm/tlbex.S') diff --git a/arch/arc/mm/tlbex.S b/arch/arc/mm/tlbex.S index ec382e59d681..50e83ca96b96 100644 --- a/arch/arc/mm/tlbex.S +++ b/arch/arc/mm/tlbex.S @@ -229,9 +229,6 @@ ex_saved_reg1: sr r3, [ARC_REG_TLBPD1] ; these go in PD1 and r2, r0, PTE_BITS_IN_PD0 ; Extract other PTE flags: (V)alid, (G)lb -#if (CONFIG_ARC_MMU_VER <= 2) /* Neednot be done with v3 onwards */ - lsr r2, r2 ; shift PTE flags to match layout in PD0 -#endif lr r3,[ARC_REG_TLBPD0] ; MMU prepares PD0 with vaddr and asid -- cgit 1.4.1