From 560655247b627ac74f5ec0c023b31c5a1f621a62 Mon Sep 17 00:00:00 2001 From: Ulrich Hecht Date: Wed, 29 Jun 2016 18:06:04 +0200 Subject: pinctrl: sh-pfc: r8a7795: Add bias pinconf support Implements pull-up and pull-down. On this SoC there is no simple mapping of GP pins to bias register bits, so we need a table. Signed-off-by: Ulrich Hecht Signed-off-by: Geert Uytterhoeven --- drivers/pinctrl/sh-pfc/pfc-r8a7795.c | 254 +++++++++++++++++++++++++++++++++-- 1 file changed, 242 insertions(+), 12 deletions(-) diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c index b74cdd310d83..0f1a111447c3 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c @@ -13,19 +13,23 @@ #include "core.h" #include "sh_pfc.h" +#define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | \ + SH_PFC_PIN_CFG_PULL_UP | \ + SH_PFC_PIN_CFG_PULL_DOWN) + #define CPU_ALL_PORT(fn, sfx) \ - PORT_GP_CFG_16(0, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \ - PORT_GP_CFG_28(1, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \ - PORT_GP_CFG_15(2, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \ - PORT_GP_CFG_12(3, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH | SH_PFC_PIN_CFG_IO_VOLTAGE), \ - PORT_GP_CFG_1(3, 12, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \ - PORT_GP_CFG_1(3, 13, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \ - PORT_GP_CFG_1(3, 14, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \ - PORT_GP_CFG_1(3, 15, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \ - PORT_GP_CFG_18(4, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH | SH_PFC_PIN_CFG_IO_VOLTAGE), \ - PORT_GP_CFG_26(5, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \ - PORT_GP_CFG_32(6, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \ - PORT_GP_CFG_4(7, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH) + PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS), \ + PORT_GP_CFG_28(1, fn, sfx, CFG_FLAGS), \ + PORT_GP_CFG_15(2, fn, sfx, CFG_FLAGS), \ + PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \ + PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS), \ + PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS), \ + PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS), \ + PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS), \ + PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \ + PORT_GP_CFG_26(5, fn, sfx, CFG_FLAGS), \ + PORT_GP_CFG_32(6, fn, sfx, CFG_FLAGS), \ + PORT_GP_CFG_4(7, fn, sfx, CFG_FLAGS) /* * F_() : just information * FM() : macro for FN_xxx / xxx_MARK @@ -5073,8 +5077,234 @@ static int r8a7795_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *poc return bit; } +#define PUEN 0xe6060400 +#define PUD 0xe6060440 + +#define PU0 0x00 +#define PU1 0x04 +#define PU2 0x08 +#define PU3 0x0c +#define PU4 0x10 +#define PU5 0x14 +#define PU6 0x18 + +static const struct { + u16 reg : 11; + u16 bit : 5; +} pullups[] = { + [RCAR_GP_PIN(2, 11)] = { PU0, 31 }, /* AVB_PHY_INT */ + [RCAR_GP_PIN(2, 10)] = { PU0, 30 }, /* AVB_MAGIC */ + [RCAR_GP_PIN(2, 9)] = { PU0, 29 }, /* AVB_MDC */ + + [RCAR_GP_PIN(1, 19)] = { PU1, 31 }, /* A19 */ + [RCAR_GP_PIN(1, 18)] = { PU1, 30 }, /* A18 */ + [RCAR_GP_PIN(1, 17)] = { PU1, 29 }, /* A17 */ + [RCAR_GP_PIN(1, 16)] = { PU1, 28 }, /* A16 */ + [RCAR_GP_PIN(1, 15)] = { PU1, 27 }, /* A15 */ + [RCAR_GP_PIN(1, 14)] = { PU1, 26 }, /* A14 */ + [RCAR_GP_PIN(1, 13)] = { PU1, 25 }, /* A13 */ + [RCAR_GP_PIN(1, 12)] = { PU1, 24 }, /* A12 */ + [RCAR_GP_PIN(1, 11)] = { PU1, 23 }, /* A11 */ + [RCAR_GP_PIN(1, 10)] = { PU1, 22 }, /* A10 */ + [RCAR_GP_PIN(1, 9)] = { PU1, 21 }, /* A9 */ + [RCAR_GP_PIN(1, 8)] = { PU1, 20 }, /* A8 */ + [RCAR_GP_PIN(1, 7)] = { PU1, 19 }, /* A7 */ + [RCAR_GP_PIN(1, 6)] = { PU1, 18 }, /* A6 */ + [RCAR_GP_PIN(1, 5)] = { PU1, 17 }, /* A5 */ + [RCAR_GP_PIN(1, 4)] = { PU1, 16 }, /* A4 */ + [RCAR_GP_PIN(1, 3)] = { PU1, 15 }, /* A3 */ + [RCAR_GP_PIN(1, 2)] = { PU1, 14 }, /* A2 */ + [RCAR_GP_PIN(1, 1)] = { PU1, 13 }, /* A1 */ + [RCAR_GP_PIN(1, 0)] = { PU1, 12 }, /* A0 */ + [RCAR_GP_PIN(2, 8)] = { PU1, 11 }, /* PWM2_A */ + [RCAR_GP_PIN(2, 7)] = { PU1, 10 }, /* PWM1_A */ + [RCAR_GP_PIN(2, 6)] = { PU1, 9 }, /* PWM0 */ + [RCAR_GP_PIN(2, 5)] = { PU1, 8 }, /* IRQ5 */ + [RCAR_GP_PIN(2, 4)] = { PU1, 7 }, /* IRQ4 */ + [RCAR_GP_PIN(2, 3)] = { PU1, 6 }, /* IRQ3 */ + [RCAR_GP_PIN(2, 2)] = { PU1, 5 }, /* IRQ2 */ + [RCAR_GP_PIN(2, 1)] = { PU1, 4 }, /* IRQ1 */ + [RCAR_GP_PIN(2, 0)] = { PU1, 3 }, /* IRQ0 */ + [RCAR_GP_PIN(2, 14)] = { PU1, 2 }, /* AVB_AVTP_CAPTURE_A */ + [RCAR_GP_PIN(2, 13)] = { PU1, 1 }, /* AVB_AVTP_MATCH_A */ + [RCAR_GP_PIN(2, 12)] = { PU1, 0 }, /* AVB_LINK */ + + [RCAR_GP_PIN(7, 3)] = { PU2, 29 }, /* HDMI1_CEC */ + [RCAR_GP_PIN(7, 2)] = { PU2, 28 }, /* HDMI0_CEC */ + [RCAR_GP_PIN(7, 1)] = { PU2, 27 }, /* AVS2 */ + [RCAR_GP_PIN(7, 0)] = { PU2, 26 }, /* AVS1 */ + [RCAR_GP_PIN(0, 15)] = { PU2, 25 }, /* D15 */ + [RCAR_GP_PIN(0, 14)] = { PU2, 24 }, /* D14 */ + [RCAR_GP_PIN(0, 13)] = { PU2, 23 }, /* D13 */ + [RCAR_GP_PIN(0, 12)] = { PU2, 22 }, /* D12 */ + [RCAR_GP_PIN(0, 11)] = { PU2, 21 }, /* D11 */ + [RCAR_GP_PIN(0, 10)] = { PU2, 20 }, /* D10 */ + [RCAR_GP_PIN(0, 9)] = { PU2, 19 }, /* D9 */ + [RCAR_GP_PIN(0, 8)] = { PU2, 18 }, /* D8 */ + [RCAR_GP_PIN(0, 7)] = { PU2, 17 }, /* D7 */ + [RCAR_GP_PIN(0, 6)] = { PU2, 16 }, /* D6 */ + [RCAR_GP_PIN(0, 5)] = { PU2, 15 }, /* D5 */ + [RCAR_GP_PIN(0, 4)] = { PU2, 14 }, /* D4 */ + [RCAR_GP_PIN(0, 3)] = { PU2, 13 }, /* D3 */ + [RCAR_GP_PIN(0, 2)] = { PU2, 12 }, /* D2 */ + [RCAR_GP_PIN(0, 1)] = { PU2, 11 }, /* D1 */ + [RCAR_GP_PIN(0, 0)] = { PU2, 10 }, /* D0 */ + [RCAR_GP_PIN(1, 27)] = { PU2, 8 }, /* EX_WAIT0_A */ + [RCAR_GP_PIN(1, 26)] = { PU2, 7 }, /* WE1_N */ + [RCAR_GP_PIN(1, 25)] = { PU2, 6 }, /* WE0_N */ + [RCAR_GP_PIN(1, 24)] = { PU2, 5 }, /* RD_WR_N */ + [RCAR_GP_PIN(1, 23)] = { PU2, 4 }, /* RD_N */ + [RCAR_GP_PIN(1, 22)] = { PU2, 3 }, /* BS_N */ + [RCAR_GP_PIN(1, 21)] = { PU2, 2 }, /* CS1_N_A26 */ + [RCAR_GP_PIN(1, 20)] = { PU2, 1 }, /* CS0_N */ + + [RCAR_GP_PIN(4, 9)] = { PU3, 31 }, /* SD3_DAT0 */ + [RCAR_GP_PIN(4, 8)] = { PU3, 30 }, /* SD3_CMD */ + [RCAR_GP_PIN(4, 7)] = { PU3, 29 }, /* SD3_CLK */ + [RCAR_GP_PIN(4, 6)] = { PU3, 28 }, /* SD2_DS */ + [RCAR_GP_PIN(4, 5)] = { PU3, 27 }, /* SD2_DAT3 */ + [RCAR_GP_PIN(4, 4)] = { PU3, 26 }, /* SD2_DAT2 */ + [RCAR_GP_PIN(4, 3)] = { PU3, 25 }, /* SD2_DAT1 */ + [RCAR_GP_PIN(4, 2)] = { PU3, 24 }, /* SD2_DAT0 */ + [RCAR_GP_PIN(4, 1)] = { PU3, 23 }, /* SD2_CMD */ + [RCAR_GP_PIN(4, 0)] = { PU3, 22 }, /* SD2_CLK */ + [RCAR_GP_PIN(3, 11)] = { PU3, 21 }, /* SD1_DAT3 */ + [RCAR_GP_PIN(3, 10)] = { PU3, 20 }, /* SD1_DAT2 */ + [RCAR_GP_PIN(3, 9)] = { PU3, 19 }, /* SD1_DAT1 */ + [RCAR_GP_PIN(3, 8)] = { PU3, 18 }, /* SD1_DAT0 */ + [RCAR_GP_PIN(3, 7)] = { PU3, 17 }, /* SD1_CMD */ + [RCAR_GP_PIN(3, 6)] = { PU3, 16 }, /* SD1_CLK */ + [RCAR_GP_PIN(3, 5)] = { PU3, 15 }, /* SD0_DAT3 */ + [RCAR_GP_PIN(3, 4)] = { PU3, 14 }, /* SD0_DAT2 */ + [RCAR_GP_PIN(3, 3)] = { PU3, 13 }, /* SD0_DAT1 */ + [RCAR_GP_PIN(3, 2)] = { PU3, 12 }, /* SD0_DAT0 */ + [RCAR_GP_PIN(3, 1)] = { PU3, 11 }, /* SD0_CMD */ + [RCAR_GP_PIN(3, 0)] = { PU3, 10 }, /* SD0_CLK */ + + [RCAR_GP_PIN(5, 19)] = { PU4, 31 }, /* MSIOF0_SS1 */ + [RCAR_GP_PIN(5, 18)] = { PU4, 30 }, /* MSIOF0_SYNC */ + [RCAR_GP_PIN(5, 17)] = { PU4, 29 }, /* MSIOF0_SCK */ + [RCAR_GP_PIN(5, 16)] = { PU4, 28 }, /* HRTS0_N */ + [RCAR_GP_PIN(5, 15)] = { PU4, 27 }, /* HCTS0_N */ + [RCAR_GP_PIN(5, 14)] = { PU4, 26 }, /* HTX0 */ + [RCAR_GP_PIN(5, 13)] = { PU4, 25 }, /* HRX0 */ + [RCAR_GP_PIN(5, 12)] = { PU4, 24 }, /* HSCK0 */ + [RCAR_GP_PIN(5, 11)] = { PU4, 23 }, /* RX2_A */ + [RCAR_GP_PIN(5, 10)] = { PU4, 22 }, /* TX2_A */ + [RCAR_GP_PIN(5, 9)] = { PU4, 21 }, /* SCK2 */ + [RCAR_GP_PIN(5, 8)] = { PU4, 20 }, /* RTS1_N_TANS */ + [RCAR_GP_PIN(5, 7)] = { PU4, 19 }, /* CTS1_N */ + [RCAR_GP_PIN(5, 6)] = { PU4, 18 }, /* TX1_A */ + [RCAR_GP_PIN(5, 5)] = { PU4, 17 }, /* RX1_A */ + [RCAR_GP_PIN(5, 4)] = { PU4, 16 }, /* RTS0_N_TANS */ + [RCAR_GP_PIN(5, 3)] = { PU4, 15 }, /* CTS0_N */ + [RCAR_GP_PIN(5, 2)] = { PU4, 14 }, /* TX0 */ + [RCAR_GP_PIN(5, 1)] = { PU4, 13 }, /* RX0 */ + [RCAR_GP_PIN(5, 0)] = { PU4, 12 }, /* SCK0 */ + [RCAR_GP_PIN(3, 15)] = { PU4, 11 }, /* SD1_WP */ + [RCAR_GP_PIN(3, 14)] = { PU4, 10 }, /* SD1_CD */ + [RCAR_GP_PIN(3, 13)] = { PU4, 9 }, /* SD0_WP */ + [RCAR_GP_PIN(3, 12)] = { PU4, 8 }, /* SD0_CD */ + [RCAR_GP_PIN(4, 17)] = { PU4, 7 }, /* SD3_DS */ + [RCAR_GP_PIN(4, 16)] = { PU4, 6 }, /* SD3_DAT7 */ + [RCAR_GP_PIN(4, 15)] = { PU4, 5 }, /* SD3_DAT6 */ + [RCAR_GP_PIN(4, 14)] = { PU4, 4 }, /* SD3_DAT5 */ + [RCAR_GP_PIN(4, 13)] = { PU4, 3 }, /* SD3_DAT4 */ + [RCAR_GP_PIN(4, 12)] = { PU4, 2 }, /* SD3_DAT3 */ + [RCAR_GP_PIN(4, 11)] = { PU4, 1 }, /* SD3_DAT2 */ + [RCAR_GP_PIN(4, 10)] = { PU4, 0 }, /* SD3_DAT1 */ + + [RCAR_GP_PIN(6, 24)] = { PU5, 31 }, /* USB0_PWEN */ + [RCAR_GP_PIN(6, 23)] = { PU5, 30 }, /* AUDIO_CLKB_B */ + [RCAR_GP_PIN(6, 22)] = { PU5, 29 }, /* AUDIO_CLKA_A */ + [RCAR_GP_PIN(6, 21)] = { PU5, 28 }, /* SSI_SDATA9_A */ + [RCAR_GP_PIN(6, 20)] = { PU5, 27 }, /* SSI_SDATA8 */ + [RCAR_GP_PIN(6, 19)] = { PU5, 26 }, /* SSI_SDATA7 */ + [RCAR_GP_PIN(6, 18)] = { PU5, 25 }, /* SSI_WS78 */ + [RCAR_GP_PIN(6, 17)] = { PU5, 24 }, /* SSI_SCK78 */ + [RCAR_GP_PIN(6, 16)] = { PU5, 23 }, /* SSI_SDATA6 */ + [RCAR_GP_PIN(6, 15)] = { PU5, 22 }, /* SSI_WS6 */ + [RCAR_GP_PIN(6, 14)] = { PU5, 21 }, /* SSI_SCK6 */ + [RCAR_GP_PIN(6, 13)] = { PU5, 20 }, /* SSI_SDATA5 */ + [RCAR_GP_PIN(6, 12)] = { PU5, 19 }, /* SSI_WS5 */ + [RCAR_GP_PIN(6, 11)] = { PU5, 18 }, /* SSI_SCK5 */ + [RCAR_GP_PIN(6, 10)] = { PU5, 17 }, /* SSI_SDATA4 */ + [RCAR_GP_PIN(6, 9)] = { PU5, 16 }, /* SSI_WS4 */ + [RCAR_GP_PIN(6, 8)] = { PU5, 15 }, /* SSI_SCK4 */ + [RCAR_GP_PIN(6, 7)] = { PU5, 14 }, /* SSI_SDATA3 */ + [RCAR_GP_PIN(6, 6)] = { PU5, 13 }, /* SSI_WS34 */ + [RCAR_GP_PIN(6, 5)] = { PU5, 12 }, /* SSI_SCK34 */ + [RCAR_GP_PIN(6, 4)] = { PU5, 11 }, /* SSI_SDATA2_A */ + [RCAR_GP_PIN(6, 3)] = { PU5, 10 }, /* SSI_SDATA1_A */ + [RCAR_GP_PIN(6, 2)] = { PU5, 9 }, /* SSI_SDATA0 */ + [RCAR_GP_PIN(6, 1)] = { PU5, 8 }, /* SSI_WS01239 */ + [RCAR_GP_PIN(6, 0)] = { PU5, 7 }, /* SSI_SCK01239 */ + [RCAR_GP_PIN(5, 25)] = { PU5, 5 }, /* MLB_DAT */ + [RCAR_GP_PIN(5, 24)] = { PU5, 4 }, /* MLB_SIG */ + [RCAR_GP_PIN(5, 23)] = { PU5, 3 }, /* MLB_CLK */ + [RCAR_GP_PIN(5, 22)] = { PU5, 2 }, /* MSIOF0_RXD */ + [RCAR_GP_PIN(5, 21)] = { PU5, 1 }, /* MSIOF0_SS2 */ + [RCAR_GP_PIN(5, 20)] = { PU5, 0 }, /* MSIOF0_TXD */ + + [RCAR_GP_PIN(6, 31)] = { PU6, 6 }, /* USB31_OVC */ + [RCAR_GP_PIN(6, 30)] = { PU6, 5 }, /* USB31_PWEN */ + [RCAR_GP_PIN(6, 29)] = { PU6, 4 }, /* USB30_OVC */ + [RCAR_GP_PIN(6, 28)] = { PU6, 3 }, /* USB30_PWEN */ + [RCAR_GP_PIN(6, 27)] = { PU6, 2 }, /* USB1_OVC */ + [RCAR_GP_PIN(6, 26)] = { PU6, 1 }, /* USB1_PWEN */ + [RCAR_GP_PIN(6, 25)] = { PU6, 0 }, /* USB0_OVC */ +}; + +static unsigned int r8a7795_pinmux_get_bias(struct sh_pfc *pfc, + unsigned int pin) +{ + u32 reg; + u32 bit; + + if (WARN_ON_ONCE(!pullups[pin].reg)) + return PIN_CONFIG_BIAS_DISABLE; + + reg = pullups[pin].reg; + bit = BIT(pullups[pin].bit); + + if (sh_pfc_read_reg(pfc, PUEN + reg, 32) & bit) { + if (sh_pfc_read_reg(pfc, PUD + reg, 32) & bit) + return PIN_CONFIG_BIAS_PULL_UP; + else + return PIN_CONFIG_BIAS_PULL_DOWN; + } else + return PIN_CONFIG_BIAS_DISABLE; +} + +static void r8a7795_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin, + unsigned int bias) +{ + u32 enable, updown; + u32 reg; + u32 bit; + + if (WARN_ON_ONCE(!pullups[pin].reg)) + return; + + reg = pullups[pin].reg; + bit = BIT(pullups[pin].bit); + + enable = sh_pfc_read_reg(pfc, PUEN + reg, 32) & ~bit; + if (bias != PIN_CONFIG_BIAS_DISABLE) + enable |= bit; + + updown = sh_pfc_read_reg(pfc, PUD + reg, 32) & ~bit; + if (bias == PIN_CONFIG_BIAS_PULL_UP) + updown |= bit; + + sh_pfc_write_reg(pfc, PUD + reg, 32, updown); + sh_pfc_write_reg(pfc, PUEN + reg, 32, enable); +} + static const struct sh_pfc_soc_operations r8a7795_pinmux_ops = { .pin_to_pocctrl = r8a7795_pin_to_pocctrl, + .get_bias = r8a7795_pinmux_get_bias, + .set_bias = r8a7795_pinmux_set_bias, }; const struct sh_pfc_soc_info r8a7795_pinmux_info = { -- cgit 1.4.1 From e729bbc19e18e559973d4ac0c0b1cf739acaa7f4 Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Thu, 30 Jun 2016 00:20:18 +0300 Subject: pinctrl: sh-pfc: Fix overly long lines The PORT_GP_CFG_() macros take up more than 80 columns -- and not for a good reason. Make the header file checkpatch.pl-proof at least in this respect... Signed-off-by: Sergei Shtylyov Signed-off-by: Geert Uytterhoeven --- drivers/pinctrl/sh-pfc/sh_pfc.h | 95 ++++++++++++++++++++++++----------------- 1 file changed, 55 insertions(+), 40 deletions(-) diff --git a/drivers/pinctrl/sh-pfc/sh_pfc.h b/drivers/pinctrl/sh-pfc/sh_pfc.h index 5e966c09434d..11f18be532b8 100644 --- a/drivers/pinctrl/sh-pfc/sh_pfc.h +++ b/drivers/pinctrl/sh-pfc/sh_pfc.h @@ -354,72 +354,87 @@ extern const struct sh_pfc_soc_info shx3_pinmux_info; * GP port style (32 ports banks) */ -#define PORT_GP_CFG_1(bank, pin, fn, sfx, cfg) fn(bank, pin, GP_##bank##_##pin, sfx, cfg) +#define PORT_GP_CFG_1(bank, pin, fn, sfx, cfg) \ + fn(bank, pin, GP_##bank##_##pin, sfx, cfg) #define PORT_GP_1(bank, pin, fn, sfx) PORT_GP_CFG_1(bank, pin, fn, sfx, 0) -#define PORT_GP_CFG_4(bank, fn, sfx, cfg) \ - PORT_GP_CFG_1(bank, 0, fn, sfx, cfg), PORT_GP_CFG_1(bank, 1, fn, sfx, cfg), \ - PORT_GP_CFG_1(bank, 2, fn, sfx, cfg), PORT_GP_CFG_1(bank, 3, fn, sfx, cfg) +#define PORT_GP_CFG_4(bank, fn, sfx, cfg) \ + PORT_GP_CFG_1(bank, 0, fn, sfx, cfg), \ + PORT_GP_CFG_1(bank, 1, fn, sfx, cfg), \ + PORT_GP_CFG_1(bank, 2, fn, sfx, cfg), \ + PORT_GP_CFG_1(bank, 3, fn, sfx, cfg) #define PORT_GP_4(bank, fn, sfx) PORT_GP_CFG_4(bank, fn, sfx, 0) -#define PORT_GP_CFG_8(bank, fn, sfx, cfg) \ - PORT_GP_CFG_4(bank, fn, sfx, cfg), \ - PORT_GP_CFG_1(bank, 4, fn, sfx, cfg), PORT_GP_CFG_1(bank, 5, fn, sfx, cfg), \ - PORT_GP_CFG_1(bank, 6, fn, sfx, cfg), PORT_GP_CFG_1(bank, 7, fn, sfx, cfg) +#define PORT_GP_CFG_8(bank, fn, sfx, cfg) \ + PORT_GP_CFG_4(bank, fn, sfx, cfg), \ + PORT_GP_CFG_1(bank, 4, fn, sfx, cfg), \ + PORT_GP_CFG_1(bank, 5, fn, sfx, cfg), \ + PORT_GP_CFG_1(bank, 6, fn, sfx, cfg), \ + PORT_GP_CFG_1(bank, 7, fn, sfx, cfg) #define PORT_GP_8(bank, fn, sfx) PORT_GP_CFG_8(bank, fn, sfx, 0) -#define PORT_GP_CFG_9(bank, fn, sfx, cfg) \ - PORT_GP_CFG_8(bank, fn, sfx, cfg), \ +#define PORT_GP_CFG_9(bank, fn, sfx, cfg) \ + PORT_GP_CFG_8(bank, fn, sfx, cfg), \ PORT_GP_CFG_1(bank, 8, fn, sfx, cfg) #define PORT_GP_9(bank, fn, sfx) PORT_GP_CFG_9(bank, fn, sfx, 0) -#define PORT_GP_CFG_12(bank, fn, sfx, cfg) \ - PORT_GP_CFG_8(bank, fn, sfx, cfg), \ - PORT_GP_CFG_1(bank, 8, fn, sfx, cfg), PORT_GP_CFG_1(bank, 9, fn, sfx, cfg), \ - PORT_GP_CFG_1(bank, 10, fn, sfx, cfg), PORT_GP_CFG_1(bank, 11, fn, sfx, cfg) +#define PORT_GP_CFG_12(bank, fn, sfx, cfg) \ + PORT_GP_CFG_9(bank, fn, sfx, cfg), \ + PORT_GP_CFG_1(bank, 9, fn, sfx, cfg), \ + PORT_GP_CFG_1(bank, 10, fn, sfx, cfg), \ + PORT_GP_CFG_1(bank, 11, fn, sfx, cfg) #define PORT_GP_12(bank, fn, sfx) PORT_GP_CFG_12(bank, fn, sfx, 0) -#define PORT_GP_CFG_14(bank, fn, sfx, cfg) \ - PORT_GP_CFG_12(bank, fn, sfx, cfg), \ - PORT_GP_CFG_1(bank, 12, fn, sfx, cfg), PORT_GP_CFG_1(bank, 13, fn, sfx, cfg) +#define PORT_GP_CFG_14(bank, fn, sfx, cfg) \ + PORT_GP_CFG_12(bank, fn, sfx, cfg), \ + PORT_GP_CFG_1(bank, 12, fn, sfx, cfg), \ + PORT_GP_CFG_1(bank, 13, fn, sfx, cfg) #define PORT_GP_14(bank, fn, sfx) PORT_GP_CFG_14(bank, fn, sfx, 0) -#define PORT_GP_CFG_15(bank, fn, sfx, cfg) \ - PORT_GP_CFG_14(bank, fn, sfx, cfg), \ +#define PORT_GP_CFG_15(bank, fn, sfx, cfg) \ + PORT_GP_CFG_14(bank, fn, sfx, cfg), \ PORT_GP_CFG_1(bank, 14, fn, sfx, cfg) #define PORT_GP_15(bank, fn, sfx) PORT_GP_CFG_15(bank, fn, sfx, 0) -#define PORT_GP_CFG_16(bank, fn, sfx, cfg) \ - PORT_GP_CFG_14(bank, fn, sfx, cfg), \ - PORT_GP_CFG_1(bank, 14, fn, sfx, cfg), PORT_GP_CFG_1(bank, 15, fn, sfx, cfg) +#define PORT_GP_CFG_16(bank, fn, sfx, cfg) \ + PORT_GP_CFG_15(bank, fn, sfx, cfg), \ + PORT_GP_CFG_1(bank, 15, fn, sfx, cfg) #define PORT_GP_16(bank, fn, sfx) PORT_GP_CFG_16(bank, fn, sfx, 0) -#define PORT_GP_CFG_18(bank, fn, sfx, cfg) \ - PORT_GP_CFG_16(bank, fn, sfx, cfg), \ - PORT_GP_CFG_1(bank, 16, fn, sfx, cfg), PORT_GP_CFG_1(bank, 17, fn, sfx, cfg) +#define PORT_GP_CFG_18(bank, fn, sfx, cfg) \ + PORT_GP_CFG_16(bank, fn, sfx, cfg), \ + PORT_GP_CFG_1(bank, 16, fn, sfx, cfg), \ + PORT_GP_CFG_1(bank, 17, fn, sfx, cfg) #define PORT_GP_18(bank, fn, sfx) PORT_GP_CFG_18(bank, fn, sfx, 0) -#define PORT_GP_CFG_26(bank, fn, sfx, cfg) \ - PORT_GP_CFG_18(bank, fn, sfx, cfg), \ - PORT_GP_CFG_1(bank, 18, fn, sfx, cfg), PORT_GP_CFG_1(bank, 19, fn, sfx, cfg), \ - PORT_GP_CFG_1(bank, 20, fn, sfx, cfg), PORT_GP_CFG_1(bank, 21, fn, sfx, cfg), \ - PORT_GP_CFG_1(bank, 22, fn, sfx, cfg), PORT_GP_CFG_1(bank, 23, fn, sfx, cfg), \ - PORT_GP_CFG_1(bank, 24, fn, sfx, cfg), PORT_GP_CFG_1(bank, 25, fn, sfx, cfg) +#define PORT_GP_CFG_26(bank, fn, sfx, cfg) \ + PORT_GP_CFG_18(bank, fn, sfx, cfg), \ + PORT_GP_CFG_1(bank, 18, fn, sfx, cfg), \ + PORT_GP_CFG_1(bank, 19, fn, sfx, cfg), \ + PORT_GP_CFG_1(bank, 20, fn, sfx, cfg), \ + PORT_GP_CFG_1(bank, 21, fn, sfx, cfg), \ + PORT_GP_CFG_1(bank, 22, fn, sfx, cfg), \ + PORT_GP_CFG_1(bank, 23, fn, sfx, cfg), \ + PORT_GP_CFG_1(bank, 24, fn, sfx, cfg), \ + PORT_GP_CFG_1(bank, 25, fn, sfx, cfg) #define PORT_GP_26(bank, fn, sfx) PORT_GP_CFG_26(bank, fn, sfx, 0) -#define PORT_GP_CFG_28(bank, fn, sfx, cfg) \ - PORT_GP_CFG_26(bank, fn, sfx, cfg), \ - PORT_GP_CFG_1(bank, 26, fn, sfx, cfg), PORT_GP_CFG_1(bank, 27, fn, sfx, cfg) +#define PORT_GP_CFG_28(bank, fn, sfx, cfg) \ + PORT_GP_CFG_26(bank, fn, sfx, cfg), \ + PORT_GP_CFG_1(bank, 26, fn, sfx, cfg), \ + PORT_GP_CFG_1(bank, 27, fn, sfx, cfg) #define PORT_GP_28(bank, fn, sfx) PORT_GP_CFG_28(bank, fn, sfx, 0) -#define PORT_GP_CFG_30(bank, fn, sfx, cfg) \ - PORT_GP_CFG_28(bank, fn, sfx, cfg), \ - PORT_GP_CFG_1(bank, 28, fn, sfx, cfg), PORT_GP_CFG_1(bank, 29, fn, sfx, cfg) +#define PORT_GP_CFG_30(bank, fn, sfx, cfg) \ + PORT_GP_CFG_28(bank, fn, sfx, cfg), \ + PORT_GP_CFG_1(bank, 28, fn, sfx, cfg), \ + PORT_GP_CFG_1(bank, 29, fn, sfx, cfg) #define PORT_GP_30(bank, fn, sfx) PORT_GP_CFG_30(bank, fn, sfx, 0) -#define PORT_GP_CFG_32(bank, fn, sfx, cfg) \ - PORT_GP_CFG_30(bank, fn, sfx, cfg), \ - PORT_GP_CFG_1(bank, 30, fn, sfx, cfg), PORT_GP_CFG_1(bank, 31, fn, sfx, cfg) +#define PORT_GP_CFG_32(bank, fn, sfx, cfg) \ + PORT_GP_CFG_30(bank, fn, sfx, cfg), \ + PORT_GP_CFG_1(bank, 30, fn, sfx, cfg), \ + PORT_GP_CFG_1(bank, 31, fn, sfx, cfg) #define PORT_GP_32(bank, fn, sfx) PORT_GP_CFG_32(bank, fn, sfx, 0) #define PORT_GP_32_REV(bank, fn, sfx) \ -- cgit 1.4.1 From 2cf59e0c200de79cd2a8f87ba06c87fa24060e2d Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Thu, 30 Jun 2016 00:21:08 +0300 Subject: pinctrl: sh-pfc: Add R8A7792 PFC support Add the PFC support for the R8A7792 SoC including pin groups for some on-chip devices such as SCIF, INTC, and LBSC... Signed-off-by: Sergei Shtylyov [geert: s/LSBC/LBSC/] Signed-off-by: Geert Uytterhoeven --- .../bindings/pinctrl/renesas,pfc-pinctrl.txt | 1 + drivers/pinctrl/sh-pfc/Kconfig | 5 + drivers/pinctrl/sh-pfc/Makefile | 1 + drivers/pinctrl/sh-pfc/core.c | 6 + drivers/pinctrl/sh-pfc/pfc-r8a7792.c | 1716 ++++++++++++++++++++ drivers/pinctrl/sh-pfc/sh_pfc.h | 25 +- 6 files changed, 1748 insertions(+), 6 deletions(-) create mode 100644 drivers/pinctrl/sh-pfc/pfc-r8a7792.c diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt index e4cf022c992e..48db27cadba0 100644 --- a/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt @@ -17,6 +17,7 @@ Required Properties: - "renesas,pfc-r8a7779": for R8A7779 (R-Car H1) compatible pin-controller. - "renesas,pfc-r8a7790": for R8A7790 (R-Car H2) compatible pin-controller. - "renesas,pfc-r8a7791": for R8A7791 (R-Car M2-W) compatible pin-controller. + - "renesas,pfc-r8a7792": for R8A7792 (R-Car V2H) compatible pin-controller. - "renesas,pfc-r8a7793": for R8A7793 (R-Car M2-N) compatible pin-controller. - "renesas,pfc-r8a7794": for R8A7794 (R-Car E2) compatible pin-controller. - "renesas,pfc-r8a7795": for R8A7795 (R-Car H3) compatible pin-controller. diff --git a/drivers/pinctrl/sh-pfc/Kconfig b/drivers/pinctrl/sh-pfc/Kconfig index 415dd8023063..8858c3ee2c61 100644 --- a/drivers/pinctrl/sh-pfc/Kconfig +++ b/drivers/pinctrl/sh-pfc/Kconfig @@ -54,6 +54,11 @@ config PINCTRL_PFC_R8A7791 depends on ARCH_R8A7791 select PINCTRL_SH_PFC +config PINCTRL_PFC_R8A7792 + def_bool y + depends on ARCH_R8A7792 + select PINCTRL_SH_PFC + config PINCTRL_PFC_R8A7793 def_bool y depends on ARCH_R8A7793 diff --git a/drivers/pinctrl/sh-pfc/Makefile b/drivers/pinctrl/sh-pfc/Makefile index 8a2c8710fc93..ffe7eb7da395 100644 --- a/drivers/pinctrl/sh-pfc/Makefile +++ b/drivers/pinctrl/sh-pfc/Makefile @@ -7,6 +7,7 @@ obj-$(CONFIG_PINCTRL_PFC_R8A7778) += pfc-r8a7778.o obj-$(CONFIG_PINCTRL_PFC_R8A7779) += pfc-r8a7779.o obj-$(CONFIG_PINCTRL_PFC_R8A7790) += pfc-r8a7790.o obj-$(CONFIG_PINCTRL_PFC_R8A7791) += pfc-r8a7791.o +obj-$(CONFIG_PINCTRL_PFC_R8A7792) += pfc-r8a7792.o obj-$(CONFIG_PINCTRL_PFC_R8A7793) += pfc-r8a7791.o obj-$(CONFIG_PINCTRL_PFC_R8A7794) += pfc-r8a7794.o obj-$(CONFIG_PINCTRL_PFC_R8A7795) += pfc-r8a7795.o diff --git a/drivers/pinctrl/sh-pfc/core.c b/drivers/pinctrl/sh-pfc/core.c index a3b82041b6a2..d74169edf35d 100644 --- a/drivers/pinctrl/sh-pfc/core.c +++ b/drivers/pinctrl/sh-pfc/core.c @@ -494,6 +494,12 @@ static const struct of_device_id sh_pfc_of_table[] = { .data = &r8a7791_pinmux_info, }, #endif +#ifdef CONFIG_PINCTRL_PFC_R8A7792 + { + .compatible = "renesas,pfc-r8a7792", + .data = &r8a7792_pinmux_info, + }, +#endif #ifdef CONFIG_PINCTRL_PFC_R8A7793 { .compatible = "renesas,pfc-r8a7793", diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7792.c b/drivers/pinctrl/sh-pfc/pfc-r8a7792.c new file mode 100644 index 000000000000..b902e3ec221e --- /dev/null +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7792.c @@ -0,0 +1,1716 @@ +/* + * r8a7792 processor support - PFC hardware block. + * + * Copyright (C) 2013-2014 Renesas Electronics Corporation + * Copyright (C) 2016 Cogent Embedded, Inc., + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 + * as published by the Free Software Foundation. + */ + +#include + +#include "core.h" +#include "sh_pfc.h" + +#define CPU_ALL_PORT(fn, sfx) \ + PORT_GP_29(0, fn, sfx), \ + PORT_GP_23(1, fn, sfx), \ + PORT_GP_32(2, fn, sfx), \ + PORT_GP_28(3, fn, sfx), \ + PORT_GP_17(4, fn, sfx), \ + PORT_GP_17(5, fn, sfx), \ + PORT_GP_17(6, fn, sfx), \ + PORT_GP_17(7, fn, sfx), \ + PORT_GP_17(8, fn, sfx), \ + PORT_GP_17(9, fn, sfx), \ + PORT_GP_32(10, fn, sfx), \ + PORT_GP_30(11, fn, sfx) + +enum { + PINMUX_RESERVED = 0, + + PINMUX_DATA_BEGIN, + GP_ALL(DATA), + PINMUX_DATA_END, + + PINMUX_FUNCTION_BEGIN, + GP_ALL(FN), + + /* GPSR0 */ + FN_IP0_0, FN_IP0_1, FN_IP0_2, FN_IP0_3, FN_IP0_4, FN_IP0_5, + FN_IP0_6, FN_IP0_7, FN_IP0_8, FN_IP0_9, FN_IP0_10, FN_IP0_11, + FN_IP0_12, FN_IP0_13, FN_IP0_14, FN_IP0_15, FN_IP0_16, + FN_IP0_17, FN_IP0_18, FN_IP0_19, FN_IP0_20, FN_IP0_21, + FN_IP0_22, FN_IP0_23, FN_IP1_0, FN_IP1_1, FN_IP1_2, + FN_IP1_3, FN_IP1_4, + + /* GPSR1 */ + FN_IP1_5, FN_IP1_6, FN_IP1_7, FN_IP1_8, FN_IP1_9, FN_IP1_10, + FN_IP1_11, FN_IP1_12, FN_IP1_13, FN_IP1_14, FN_IP1_15, FN_IP1_16, + FN_DU1_DB2_C0_DATA12, FN_DU1_DB3_C1_DATA13, FN_DU1_DB4_C2_DATA14, + FN_DU1_DB5_C3_DATA15, FN_DU1_DB6_C4, FN_DU1_DB7_C5, + FN_DU1_EXHSYNC_DU1_HSYNC, FN_DU1_EXVSYNC_DU1_VSYNC, + FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_DU1_DISP, FN_DU1_CDE, + + /* GPSR2 */ + FN_D0, FN_D1, FN_D2, FN_D3, FN_D4, FN_D5, FN_D6, FN_D7, + FN_D8, FN_D9, FN_D10, FN_D11, FN_D12, FN_D13, FN_D14, FN_D15, + FN_A0, FN_A1, FN_A2, FN_A3, FN_A4, FN_A5, FN_A6, FN_A7, + FN_A8, FN_A9, FN_A10, FN_A11, FN_A12, FN_A13, FN_A14, FN_A15, + + /* GPSR3 */ + FN_A16, FN_A17, FN_A18, FN_A19, FN_IP1_17, FN_IP1_18, + FN_CS1_N_A26, FN_EX_CS0_N, FN_EX_CS1_N, FN_EX_CS2_N, FN_EX_CS3_N, + FN_EX_CS4_N, FN_EX_CS5_N, FN_BS_N, FN_RD_N, FN_RD_WR_N, + FN_WE0_N, FN_WE1_N, FN_EX_WAIT0, FN_IRQ0, FN_IRQ1, FN_IRQ2, FN_IRQ3, + FN_IP1_19, FN_IP1_20, FN_IP1_21, FN_IP1_22, FN_CS0_N, + + /* GPSR4 */ + FN_VI0_CLK, FN_VI0_CLKENB, FN_VI0_HSYNC_N, FN_VI0_VSYNC_N, + FN_VI0_D0_B0_C0, FN_VI0_D1_B1_C1, FN_VI0_D2_B2_C2, FN_VI0_D3_B3_C3, + FN_VI0_D4_B4_C4, FN_VI0_D5_B5_C5, FN_VI0_D6_B6_C6, FN_VI0_D7_B7_C7, + FN_VI0_D8_G0_Y0, FN_VI0_D9_G1_Y1, FN_VI0_D10_G2_Y2, FN_VI0_D11_G3_Y3, + FN_VI0_FIELD, + + /* GPSR5 */ + FN_VI1_CLK, FN_VI1_CLKENB, FN_VI1_HSYNC_N, FN_VI1_VSYNC_N, + FN_VI1_D0_B0_C0, FN_VI1_D1_B1_C1, FN_VI1_D2_B2_C2, FN_VI1_D3_B3_C3, + FN_VI1_D4_B4_C4, FN_VI1_D5_B5_C5, FN_VI1_D6_B6_C6, FN_VI1_D7_B7_C7, + FN_VI1_D8_G0_Y0, FN_VI1_D9_G1_Y1, FN_VI1_D10_G2_Y2, FN_VI1_D11_G3_Y3, + FN_VI1_FIELD, + + /* GPSR6 */ + FN_IP2_0, FN_IP2_1, FN_IP2_2, FN_IP2_3, FN_IP2_4, FN_IP2_5, FN_IP2_6, + FN_IP2_7, FN_IP2_8, FN_IP2_9, FN_IP2_10, FN_IP2_11, FN_IP2_12, + FN_IP2_13, FN_IP2_14, FN_IP2_15, FN_IP2_16, + + /* GPSR7 */ + FN_IP3_0, FN_IP3_1, FN_IP3_2, FN_IP3_3, FN_IP3_4, FN_IP3_5, FN_IP3_6, + FN_IP3_7, FN_IP3_8, FN_IP3_9, FN_IP3_10, FN_IP3_11, FN_IP3_12, + FN_IP3_13, FN_VI3_D10_Y2, FN_IP3_14, FN_VI3_FIELD, + + /* GPSR8 */ + FN_VI4_CLK, FN_IP4_0, FN_IP4_1, FN_IP4_3_2, FN_IP4_4, FN_IP4_6_5, + FN_IP4_8_7, FN_IP4_10_9, FN_IP4_12_11, FN_IP4_14_13, FN_IP4_16_15, + FN_IP4_18_17, FN_IP4_20_19, FN_IP4_21, FN_IP4_22, FN_IP4_23, FN_IP4_24, + + /* GPSR9 */ + FN_VI5_CLK, FN_IP5_0, FN_IP5_1, FN_IP5_2, FN_IP5_3, FN_IP5_4, FN_IP5_5, + FN_IP5_6, FN_IP5_7, FN_IP5_8, FN_IP5_9, FN_IP5_10, FN_IP5_11, + FN_VI5_D9_Y1, FN_VI5_D10_Y2, FN_VI5_D11_Y3, FN_VI5_FIELD, + + /* GPSR10 */ + FN_IP6_0, FN_IP6_1, FN_HRTS0_N, FN_IP6_2, FN_IP6_3, FN_IP6_4, FN_IP6_5, + FN_HCTS1_N, FN_IP6_6, FN_IP6_7, FN_SCK0, FN_CTS0_N, FN_RTS0_N, + FN_TX0, FN_RX0, FN_SCK1, FN_CTS1_N, FN_RTS1_N, FN_TX1, FN_RX1, + FN_IP6_9_8, FN_IP6_11_10, FN_IP6_13_12, FN_IP6_15_14, FN_IP6_16, + FN_IP6_18_17, FN_SCIF_CLK, FN_CAN0_TX, FN_CAN0_RX, FN_CAN_CLK, + FN_CAN1_TX, FN_CAN1_RX, + + /* GPSR11 */ + FN_IP7_1_0, FN_IP7_3_2, FN_IP7_5_4, FN_IP7_6, FN_IP7_7, FN_SD0_CLK, + FN_SD0_CMD, FN_SD0_DAT0, FN_SD0_DAT1, FN_SD0_DAT2, FN_SD0_DAT3, + FN_SD0_CD, FN_SD0_WP, FN_IP7_9_8, FN_IP7_11_10, FN_IP7_13_12, + FN_IP7_15_14, FN_IP7_16, FN_IP7_17, FN_IP7_18, FN_IP7_19, FN_IP7_20, + FN_ADICLK, FN_ADICS_SAMP, FN_ADIDATA, FN_ADICHS0, FN_ADICHS1, + FN_ADICHS2, FN_AVS1, FN_AVS2, + + /* IPSR0 */ + FN_DU0_DR0_DATA0, FN_DU0_DR1_DATA1, FN_DU0_DR2_Y4_DATA2, + FN_DU0_DR3_Y5_DATA3, FN_DU0_DR4_Y6_DATA4, FN_DU0_DR5_Y7_DATA5, + FN_DU0_DR6_Y8_DATA6, FN_DU0_DR7_Y9_DATA7, FN_DU0_DG0_DATA8, + FN_DU0_DG1_DATA9, FN_DU0_DG2_C6_DATA10, FN_DU0_DG3_C7_DATA11, + FN_DU0_DG4_Y0_DATA12, FN_DU0_DG5_Y1_DATA13, FN_DU0_DG6_Y2_DATA14, + FN_DU0_DG7_Y3_DATA15, FN_DU0_DB0, FN_DU0_DB1, FN_DU0_DB2_C0, + FN_DU0_DB3_C1, FN_DU0_DB4_C2, FN_DU0_DB5_C3, FN_DU0_DB6_C4, + FN_DU0_DB7_C5, + + /* IPSR1 */ + FN_DU0_EXHSYNC_DU0_HSYNC, FN_DU0_EXVSYNC_DU0_VSYNC, + FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, FN_DU0_DISP, FN_DU0_CDE, + FN_DU1_DR2_Y4_DATA0, FN_DU1_DR3_Y5_DATA1, FN_DU1_DR4_Y6_DATA2, + FN_DU1_DR5_Y7_DATA3, FN_DU1_DR6_DATA4, FN_DU1_DR7_DATA5, + FN_DU1_DG2_C6_DATA6, FN_DU1_DG3_C7_DATA7, FN_DU1_DG4_Y0_DATA8, + FN_DU1_DG5_Y1_DATA9, FN_DU1_DG6_Y2_DATA10, FN_DU1_DG7_Y3_DATA11, + FN_A20, FN_MOSI_IO0, FN_A21, FN_MISO_IO1, FN_A22, FN_IO2, + FN_A23, FN_IO3, FN_A24, FN_SPCLK, FN_A25, FN_SSL, + + /* IPSR2 */ + FN_VI2_CLK, FN_AVB_RX_CLK, FN_VI2_CLKENB, FN_AVB_RX_DV, + FN_VI2_HSYNC_N, FN_AVB_RXD0, FN_VI2_VSYNC_N, FN_AVB_RXD1, + FN_VI2_D0_C0, FN_AVB_RXD2, FN_VI2_D1_C1, FN_AVB_RXD3, + FN_VI2_D2_C2, FN_AVB_RXD4, FN_VI2_D3_C3, FN_AVB_RXD5, + FN_VI2_D4_C4, FN_AVB_RXD6, FN_VI2_D5_C5, FN_AVB_RXD7, + FN_VI2_D6_C6, FN_AVB_RX_ER, FN_VI2_D7_C7, FN_AVB_COL, + FN_VI2_D8_Y0, FN_AVB_TXD3, FN_VI2_D9_Y1, FN_AVB_TX_EN, + FN_VI2_D10_Y2, FN_AVB_TXD0, FN_VI2_D11_Y3, FN_AVB_TXD1, + FN_VI2_FIELD, FN_AVB_TXD2, + + /* IPSR3 */ + FN_VI3_CLK, FN_AVB_TX_CLK, FN_VI3_CLKENB, FN_AVB_TXD4, + FN_VI3_HSYNC_N, FN_AVB_TXD5, FN_VI3_VSYNC_N, FN_AVB_TXD6, + FN_VI3_D0_C0, FN_AVB_TXD7, FN_VI3_D1_C1, FN_AVB_TX_ER, + FN_VI3_D2_C2, FN_AVB_GTX_CLK, FN_VI3_D3_C3, FN_AVB_MDC, + FN_VI3_D4_C4, FN_AVB_MDIO, FN_VI3_D5_C5, FN_AVB_LINK, + FN_VI3_D6_C6, FN_AVB_MAGIC, FN_VI3_D7_C7, FN_AVB_PHY_INT, + FN_VI3_D8_Y0, FN_AVB_CRS, FN_VI3_D9_Y1, FN_AVB_GTXREFCLK, + FN_VI3_D11_Y3, FN_AVB_AVTP_MATCH, + + /* IPSR4 */ + FN_VI4_CLKENB, FN_VI0_D12_G4_Y4, FN_VI4_HSYNC_N, FN_VI0_D13_G5_Y5, + FN_VI4_VSYNC_N, FN_VI0_D14_G6_Y6, FN_RDR_CLKOUT, + FN_VI4_D0_C0, FN_VI0_D15_G7_Y7, + FN_VI4_D1_C1, FN_VI0_D16_R0, FN_VI1_D12_G4_Y4, + FN_VI4_D2_C2, FN_VI0_D17_R1, FN_VI1_D13_G5_Y5, + FN_VI4_D3_C3, FN_VI0_D18_R2, FN_VI1_D14_G6_Y6, + FN_VI4_D4_C4, FN_VI0_D19_R3, FN_VI1_D15_G7_Y7, + FN_VI4_D5_C5, FN_VI0_D20_R4, FN_VI2_D12_Y4, + FN_VI4_D6_C6, FN_VI0_D21_R5, FN_VI2_D13_Y5, + FN_VI4_D7_C7, FN_VI0_D22_R6, FN_VI2_D14_Y6, + FN_VI4_D8_Y0, FN_VI0_D23_R7, FN_VI2_D15_Y7, + FN_VI4_D9_Y1, FN_VI3_D12_Y4, FN_VI4_D10_Y2, FN_VI3_D13_Y5, + FN_VI4_D11_Y3, FN_VI3_D14_Y6, FN_VI4_FIELD, FN_VI3_D15_Y7, + + /* IPSR5 */ + FN_VI5_CLKENB, FN_VI1_D12_G4_Y4_B, FN_VI5_HSYNC_N, FN_VI1_D13_G5_Y5_B, + FN_VI5_VSYNC_N, FN_VI1_D14_G6_Y6_B, FN_VI5_D0_C0, FN_VI1_D15_G7_Y7_B, + FN_VI5_D1_C1, FN_VI1_D16_R0, FN_VI5_D2_C2, FN_VI1_D17_R1, + FN_VI5_D3_C3, FN_VI1_D18_R2, FN_VI5_D4_C4, FN_VI1_D19_R3, + FN_VI5_D5_C5, FN_VI1_D20_R4, FN_VI5_D6_C6, FN_VI1_D21_R5, + FN_VI5_D7_C7, FN_VI1_D22_R6, FN_VI5_D8_Y0, FN_VI1_D23_R7, + + /* IPSR6 */ + FN_MSIOF0_SCK, FN_HSCK0, FN_MSIOF0_SYNC, FN_HCTS0_N, + FN_MSIOF0_TXD, FN_HTX0, FN_MSIOF0_RXD, FN_HRX0, + FN_MSIOF1_SCK, FN_HSCK1, FN_MSIOF1_SYNC, FN_HRTS1_N, + FN_MSIOF1_TXD, FN_HTX1, FN_MSIOF1_RXD, FN_HRX1, + FN_DRACK0, FN_SCK2, FN_DACK0, FN_TX2, FN_DREQ0_N, FN_RX2, + FN_DACK1, FN_SCK3, FN_TX3, FN_DREQ1_N, FN_RX3, + + /* IPSR7 */ + FN_PWM0, FN_TCLK1, FN_FSO_CFE_0, FN_PWM1, FN_TCLK2, FN_FSO_CFE_1, + FN_PWM2, FN_TCLK3, FN_FSO_TOE, FN_PWM3, FN_PWM4, + FN_SSI_SCK34, FN_TPU0TO0, FN_SSI_WS34, FN_TPU0TO1, + FN_SSI_SDATA3, FN_TPU0TO2, FN_SSI_SCK4, FN_TPU0TO3, + FN_SSI_WS4, FN_SSI_SDATA4, FN_AUDIO_CLKOUT, + FN_AUDIO_CLKA, FN_AUDIO_CLKB, + + /* MOD_SEL */ + FN_SEL_VI1_0, FN_SEL_VI1_1, + PINMUX_FUNCTION_END, + + PINMUX_MARK_BEGIN, + DU1_DB2_C0_DATA12_MARK, DU1_DB3_C1_DATA13_MARK, + DU1_DB4_C2_DATA14_MARK, DU1_DB5_C3_DATA15_MARK, + DU1_DB6_C4_MARK, DU1_DB7_C5_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK, + DU1_EXVSYNC_DU1_VSYNC_MARK, DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK, + DU1_DISP_MARK, DU1_CDE_MARK, + + D0_MARK, D1_MARK, D2_MARK, D3_MARK, D4_MARK, D5_MARK, D6_MARK, + D7_MARK, D8_MARK, D9_MARK, D10_MARK, D11_MARK, D12_MARK, D13_MARK, + D14_MARK, D15_MARK, A0_MARK, A1_MARK, A2_MARK, A3_MARK, A4_MARK, + A5_MARK, A6_MARK, A7_MARK, A8_MARK, A9_MARK, A10_MARK, A11_MARK, + A12_MARK, A13_MARK, A14_MARK, A15_MARK, + + A16_MARK, A17_MARK, A18_MARK, A19_MARK, CS1_N_A26_MARK, + EX_CS0_N_MARK, EX_CS1_N_MARK, EX_CS2_N_MARK, EX_CS3_N_MARK, + EX_CS4_N_MARK, EX_CS5_N_MARK, BS_N_MARK, RD_N_MARK, RD_WR_N_MARK, + WE0_N_MARK, WE1_N_MARK, EX_WAIT0_MARK, + IRQ0_MARK, IRQ1_MARK, IRQ2_MARK, IRQ3_MARK, CS0_N_MARK, + + VI0_CLK_MARK, VI0_CLKENB_MARK, VI0_HSYNC_N_MARK, VI0_VSYNC_N_MARK, + VI0_D0_B0_C0_MARK, VI0_D1_B1_C1_MARK, VI0_D2_B2_C2_MARK, + VI0_D3_B3_C3_MARK, VI0_D4_B4_C4_MARK, VI0_D5_B5_C5_MARK, + VI0_D6_B6_C6_MARK, VI0_D7_B7_C7_MARK, VI0_D8_G0_Y0_MARK, + VI0_D9_G1_Y1_MARK, VI0_D10_G2_Y2_MARK, VI0_D11_G3_Y3_MARK, + VI0_FIELD_MARK, + + VI1_CLK_MARK, VI1_CLKENB_MARK, VI1_HSYNC_N_MARK, VI1_VSYNC_N_MARK, + VI1_D0_B0_C0_MARK, VI1_D1_B1_C1_MARK, VI1_D2_B2_C2_MARK, + VI1_D3_B3_C3_MARK, VI1_D4_B4_C4_MARK, VI1_D5_B5_C5_MARK, + VI1_D6_B6_C6_MARK, VI1_D7_B7_C7_MARK, VI1_D8_G0_Y0_MARK, + VI1_D9_G1_Y1_MARK, VI1_D10_G2_Y2_MARK, VI1_D11_G3_Y3_MARK, + VI1_FIELD_MARK, + + VI3_D10_Y2_MARK, VI3_FIELD_MARK, + + VI4_CLK_MARK, + + VI5_CLK_MARK, VI5_D9_Y1_MARK, VI5_D10_Y2_MARK, VI5_D11_Y3_MARK, + VI5_FIELD_MARK, + + HRTS0_N_MARK, HCTS1_N_MARK, SCK0_MARK, CTS0_N_MARK, RTS0_N_MARK, + TX0_MARK, RX0_MARK, SCK1_MARK, CTS1_N_MARK, RTS1_N_MARK, + TX1_MARK, RX1_MARK, SCIF_CLK_MARK, CAN0_TX_MARK, CAN0_RX_MARK, + CAN_CLK_MARK, CAN1_TX_MARK, CAN1_RX_MARK, + + SD0_CLK_MARK, SD0_CMD_MARK, SD0_DAT0_MARK, SD0_DAT1_MARK, + SD0_DAT2_MARK, SD0_DAT3_MARK, SD0_CD_MARK, SD0_WP_MARK, + ADICLK_MARK, ADICS_SAMP_MARK, ADIDATA_MARK, ADICHS0_MARK, + ADICHS1_MARK, ADICHS2_MARK, AVS1_MARK, AVS2_MARK, + + /* IPSR0 */ + DU0_DR0_DATA0_MARK, DU0_DR1_DATA1_MARK, DU0_DR2_Y4_DATA2_MARK, + DU0_DR3_Y5_DATA3_MARK, DU0_DR4_Y6_DATA4_MARK, DU0_DR5_Y7_DATA5_MARK, + DU0_DR6_Y8_DATA6_MARK, DU0_DR7_Y9_DATA7_MARK, DU0_DG0_DATA8_MARK, + DU0_DG1_DATA9_MARK, DU0_DG2_C6_DATA10_MARK, DU0_DG3_C7_DATA11_MARK, + DU0_DG4_Y0_DATA12_MARK, DU0_DG5_Y1_DATA13_MARK, DU0_DG6_Y2_DATA14_MARK, + DU0_DG7_Y3_DATA15_MARK, DU0_DB0_MARK, DU0_DB1_MARK, + DU0_DB2_C0_MARK, DU0_DB3_C1_MARK, DU0_DB4_C2_MARK, DU0_DB5_C3_MARK, + DU0_DB6_C4_MARK, DU0_DB7_C5_MARK, + + /* IPSR1 */ + DU0_EXHSYNC_DU0_HSYNC_MARK, DU0_EXVSYNC_DU0_VSYNC_MARK, + DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK, DU0_DISP_MARK, DU0_CDE_MARK, + DU1_DR2_Y4_DATA0_MARK, DU1_DR3_Y5_DATA1_MARK, DU1_DR4_Y6_DATA2_MARK, + DU1_DR5_Y7_DATA3_MARK, DU1_DR6_DATA4_MARK, DU1_DR7_DATA5_MARK, + DU1_DG2_C6_DATA6_MARK, DU1_DG3_C7_DATA7_MARK, DU1_DG4_Y0_DATA8_MARK, + DU1_DG5_Y1_DATA9_MARK, DU1_DG6_Y2_DATA10_MARK, DU1_DG7_Y3_DATA11_MARK, + A20_MARK, MOSI_IO0_MARK, A21_MARK, MISO_IO1_MARK, A22_MARK, IO2_MARK, + A23_MARK, IO3_MARK, A24_MARK, SPCLK_MARK, A25_MARK, SSL_MARK, + + /* IPSR2 */ + VI2_CLK_MARK, AVB_RX_CLK_MARK, VI2_CLKENB_MARK, AVB_RX_DV_MARK, + VI2_HSYNC_N_MARK, AVB_RXD0_MARK, VI2_VSYNC_N_MARK, AVB_RXD1_MARK, + VI2_D0_C0_MARK, AVB_RXD2_MARK, VI2_D1_C1_MARK, AVB_TX_CLK_MARK, + VI2_D2_C2_MARK, AVB_RXD4_MARK, VI2_D3_C3_MARK, AVB_RXD5_MARK, + VI2_D4_C4_MARK, AVB_RXD6_MARK, VI2_D5_C5_MARK, AVB_RXD7_MARK, + VI2_D6_C6_MARK, AVB_RX_ER_MARK, VI2_D7_C7_MARK, AVB_COL_MARK, + VI2_D8_Y0_MARK, AVB_RXD3_MARK, VI2_D9_Y1_MARK, AVB_TX_EN_MARK, + VI2_D10_Y2_MARK, AVB_TXD0_MARK, + VI2_D11_Y3_MARK, AVB_TXD1_MARK, VI2_FIELD_MARK, AVB_TXD2_MARK, + + /* IPSR3 */ + VI3_CLK_MARK, AVB_TXD3_MARK, VI3_CLKENB_MARK, AVB_TXD4_MARK, + VI3_HSYNC_N_MARK, AVB_TXD5_MARK, VI3_VSYNC_N_MARK, AVB_TXD6_MARK, + VI3_D0_C0_MARK, AVB_TXD7_MARK, VI3_D1_C1_MARK, AVB_TX_ER_MARK, + VI3_D2_C2_MARK, AVB_GTX_CLK_MARK, VI3_D3_C3_MARK, AVB_MDC_MARK, + VI3_D4_C4_MARK, AVB_MDIO_MARK, VI3_D5_C5_MARK, AVB_LINK_MARK, + VI3_D6_C6_MARK, AVB_MAGIC_MARK, VI3_D7_C7_MARK, AVB_PHY_INT_MARK, + VI3_D8_Y0_MARK, AVB_CRS_MARK, VI3_D9_Y1_MARK, AVB_GTXREFCLK_MARK, + VI3_D11_Y3_MARK, AVB_AVTP_MATCH_MARK, + + /* IPSR4 */ + VI4_CLKENB_MARK, VI0_D12_G4_Y4_MARK, VI4_HSYNC_N_MARK, + VI0_D13_G5_Y5_MARK, VI4_VSYNC_N_MARK, VI0_D14_G6_Y6_MARK, + RDR_CLKOUT_MARK, VI4_D0_C0_MARK, VI0_D15_G7_Y7_MARK, VI4_D1_C1_MARK, + VI0_D16_R0_MARK, VI1_D12_G4_Y4_MARK, VI4_D2_C2_MARK, VI0_D17_R1_MARK, + VI1_D13_G5_Y5_MARK, VI4_D3_C3_MARK, VI0_D18_R2_MARK, VI1_D14_G6_Y6_MARK, + VI4_D4_C4_MARK, VI0_D19_R3_MARK, VI1_D15_G7_Y7_MARK, VI4_D5_C5_MARK, + VI0_D20_R4_MARK, VI2_D12_Y4_MARK, VI4_D6_C6_MARK, VI0_D21_R5_MARK, + VI2_D13_Y5_MARK, VI4_D7_C7_MARK, VI0_D22_R6_MARK, VI2_D14_Y6_MARK, + VI4_D8_Y0_MARK, VI0_D23_R7_MARK, VI2_D15_Y7_MARK, VI4_D9_Y1_MARK, + VI3_D12_Y4_MARK, VI4_D10_Y2_MARK, VI3_D13_Y5_MARK, VI4_D11_Y3_MARK, + VI3_D14_Y6_MARK, VI4_FIELD_MARK, VI3_D15_Y7_MARK, + + /* IPSR5 */ + VI5_CLKENB_MARK, VI1_D12_G4_Y4_B_MARK, VI5_HSYNC_N_MARK, + VI1_D13_G5_Y5_B_MARK, VI5_VSYNC_N_MARK, VI1_D14_G6_Y6_B_MARK, + VI5_D0_C0_MARK, VI1_D15_G7_Y7_B_MARK, VI5_D1_C1_MARK, VI1_D16_R0_MARK, + VI5_D2_C2_MARK, VI1_D17_R1_MARK, VI5_D3_C3_MARK, VI1_D18_R2_MARK, + VI5_D4_C4_MARK, VI1_D19_R3_MARK, VI5_D5_C5_MARK, VI1_D20_R4_MARK, + VI5_D6_C6_MARK, VI1_D21_R5_MARK, VI5_D7_C7_MARK, VI1_D22_R6_MARK, + VI5_D8_Y0_MARK, VI1_D23_R7_MARK, + + /* IPSR6 */ + MSIOF0_SCK_MARK, HSCK0_MARK, MSIOF0_SYNC_MARK, HCTS0_N_MARK, + MSIOF0_TXD_MARK, HTX0_MARK, MSIOF0_RXD_MARK, HRX0_MARK, + MSIOF1_SCK_MARK, HSCK1_MARK, MSIOF1_SYNC_MARK, HRTS1_N_MARK, + MSIOF1_TXD_MARK, HTX1_MARK, MSIOF1_RXD_MARK, HRX1_MARK, + DRACK0_MARK, SCK2_MARK, DACK0_MARK, TX2_MARK, DREQ0_N_MARK, + RX2_MARK, DACK1_MARK, SCK3_MARK, TX3_MARK, DREQ1_N_MARK, + RX3_MARK, + + /* IPSR7 */ + PWM0_MARK, TCLK1_MARK, FSO_CFE_0_MARK, PWM1_MARK, TCLK2_MARK, + FSO_CFE_1_MARK, PWM2_MARK, TCLK3_MARK, FSO_TOE_MARK, PWM3_MARK, + PWM4_MARK, SSI_SCK34_MARK, TPU0TO0_MARK, SSI_WS34_MARK, TPU0TO1_MARK, + SSI_SDATA3_MARK, TPU0TO2_MARK, SSI_SCK4_MARK, TPU0TO3_MARK, + SSI_WS4_MARK, SSI_SDATA4_MARK, AUDIO_CLKOUT_MARK, AUDIO_CLKA_MARK, + AUDIO_CLKB_MARK, + PINMUX_MARK_END, +}; + +static const u16 pinmux_data[] = { + PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */ + + PINMUX_SINGLE(DU1_DB2_C0_DATA12), + PINMUX_SINGLE(DU1_DB3_C1_DATA13), + PINMUX_SINGLE(DU1_DB4_C2_DATA14), + PINMUX_SINGLE(DU1_DB5_C3_DATA15), + PINMUX_SINGLE(DU1_DB6_C4), + PINMUX_SINGLE(DU1_DB7_C5), + PINMUX_SINGLE(DU1_EXHSYNC_DU1_HSYNC), + PINMUX_SINGLE(DU1_EXVSYNC_DU1_VSYNC), + PINMUX_SINGLE(DU1_EXODDF_DU1_ODDF_DISP_CDE), + PINMUX_SINGLE(DU1_DISP), + PINMUX_SINGLE(DU1_CDE), + PINMUX_SINGLE(D0), + PINMUX_SINGLE(D1), + PINMUX_SINGLE(D2), + PINMUX_SINGLE(D3), + PINMUX_SINGLE(D4), + PINMUX_SINGLE(D5), + PINMUX_SINGLE(D6), + PINMUX_SINGLE(D7), + PINMUX_SINGLE(D8), + PINMUX_SINGLE(D9), + PINMUX_SINGLE(D10), + PINMUX_SINGLE(D11), + PINMUX_SINGLE(D12), + PINMUX_SINGLE(D13), + PINMUX_SINGLE(D14), + PINMUX_SINGLE(D15), + PINMUX_SINGLE(A0), + PINMUX_SINGLE(A1), + PINMUX_SINGLE(A2), + PINMUX_SINGLE(A3), + PINMUX_SINGLE(A4), + PINMUX_SINGLE(A5), + PINMUX_SINGLE(A6), + PINMUX_SINGLE(A7), + PINMUX_SINGLE(A8), + PINMUX_SINGLE(A9), + PINMUX_SINGLE(A10), + PINMUX_SINGLE(A11), + PINMUX_SINGLE(A12), + PINMUX_SINGLE(A13), + PINMUX_SINGLE(A14), + PINMUX_SINGLE(A15), + PINMUX_SINGLE(A16), + PINMUX_SINGLE(A17), + PINMUX_SINGLE(A18), + PINMUX_SINGLE(A19), + PINMUX_SINGLE(CS1_N_A26), + PINMUX_SINGLE(EX_CS0_N), + PINMUX_SINGLE(EX_CS1_N), + PINMUX_SINGLE(EX_CS2_N), + PINMUX_SINGLE(EX_CS3_N), + PINMUX_SINGLE(EX_CS4_N), + PINMUX_SINGLE(EX_CS5_N), + PINMUX_SINGLE(BS_N), + PINMUX_SINGLE(RD_N), + PINMUX_SINGLE(RD_WR_N), + PINMUX_SINGLE(WE0_N), + PINMUX_SINGLE(WE1_N), + PINMUX_SINGLE(EX_WAIT0), + PINMUX_SINGLE(IRQ0), + PINMUX_SINGLE(IRQ1), + PINMUX_SINGLE(IRQ2), + PINMUX_SINGLE(IRQ3), + PINMUX_SINGLE(CS0_N), + PINMUX_SINGLE(VI0_CLK), + PINMUX_SINGLE(VI0_CLKENB), + PINMUX_SINGLE(VI0_HSYNC_N), + PINMUX_SINGLE(VI0_VSYNC_N), + PINMUX_SINGLE(VI0_D0_B0_C0), + PINMUX_SINGLE(VI0_D1_B1_C1), + PINMUX_SINGLE(VI0_D2_B2_C2), + PINMUX_SINGLE(VI0_D3_B3_C3), + PINMUX_SINGLE(VI0_D4_B4_C4), + PINMUX_SINGLE(VI0_D5_B5_C5), + PINMUX_SINGLE(VI0_D6_B6_C6), + PINMUX_SINGLE(VI0_D7_B7_C7), + PINMUX_SINGLE(VI0_D8_G0_Y0), + PINMUX_SINGLE(VI0_D9_G1_Y1), + PINMUX_SINGLE(VI0_D10_G2_Y2), + PINMUX_SINGLE(VI0_D11_G3_Y3), + PINMUX_SINGLE(VI0_FIELD), + PINMUX_SINGLE(VI1_CLK), + PINMUX_SINGLE(VI1_CLKENB), + PINMUX_SINGLE(VI1_HSYNC_N), + PINMUX_SINGLE(VI1_VSYNC_N), + PINMUX_SINGLE(VI1_D0_B0_C0), + PINMUX_SINGLE(VI1_D1_B1_C1), + PINMUX_SINGLE(VI1_D2_B2_C2), + PINMUX_SINGLE(VI1_D3_B3_C3), + PINMUX_SINGLE(VI1_D4_B4_C4), + PINMUX_SINGLE(VI1_D5_B5_C5), + PINMUX_SINGLE(VI1_D6_B6_C6), + PINMUX_SINGLE(VI1_D7_B7_C7), + PINMUX_SINGLE(VI1_D8_G0_Y0), + PINMUX_SINGLE(VI1_D9_G1_Y1), + PINMUX_SINGLE(VI1_D10_G2_Y2), + PINMUX_SINGLE(VI1_D11_G3_Y3), + PINMUX_SINGLE(VI1_FIELD), + PINMUX_SINGLE(VI3_D10_Y2), + PINMUX_SINGLE(VI3_FIELD), + PINMUX_SINGLE(VI4_CLK), + PINMUX_SINGLE(VI5_CLK), + PINMUX_SINGLE(VI5_D9_Y1), + PINMUX_SINGLE(VI5_D10_Y2), + PINMUX_SINGLE(VI5_D11_Y3), + PINMUX_SINGLE(VI5_FIELD), + PINMUX_SINGLE(HRTS0_N), + PINMUX_SINGLE(HCTS1_N), + PINMUX_SINGLE(SCK0), + PINMUX_SINGLE(CTS0_N), + PINMUX_SINGLE(RTS0_N), + PINMUX_SINGLE(TX0), + PINMUX_SINGLE(RX0), + PINMUX_SINGLE(SCK1), + PINMUX_SINGLE(CTS1_N), + PINMUX_SINGLE(RTS1_N), + PINMUX_SINGLE(TX1), + PINMUX_SINGLE(RX1), + PINMUX_SINGLE(SCIF_CLK), + PINMUX_SINGLE(CAN0_TX), + PINMUX_SINGLE(CAN0_RX), + PINMUX_SINGLE(CAN_CLK), + PINMUX_SINGLE(CAN1_TX), + PINMUX_SINGLE(CAN1_RX), + PINMUX_SINGLE(SD0_CLK), + PINMUX_SINGLE(SD0_CMD), + PINMUX_SINGLE(SD0_DAT0), + PINMUX_SINGLE(SD0_DAT1), + PINMUX_SINGLE(SD0_DAT2), + PINMUX_SINGLE(SD0_DAT3), + PINMUX_SINGLE(SD0_CD), + PINMUX_SINGLE(SD0_WP), + PINMUX_SINGLE(ADICLK), + PINMUX_SINGLE(ADICS_SAMP), + PINMUX_SINGLE(ADIDATA), + PINMUX_SINGLE(ADICHS0), + PINMUX_SINGLE(ADICHS1), + PINMUX_SINGLE(ADICHS2), + PINMUX_SINGLE(AVS1), + PINMUX_SINGLE(AVS2), + + /* IPSR0 */ + PINMUX_IPSR_GPSR(IP0_0, DU0_DR0_DATA0), + PINMUX_IPSR_GPSR(IP0_1, DU0_DR1_DATA1), + PINMUX_IPSR_GPSR(IP0_2, DU0_DR2_Y4_DATA2), + PINMUX_IPSR_GPSR(IP0_3, DU0_DR3_Y5_DATA3), + PINMUX_IPSR_GPSR(IP0_4, DU0_DR4_Y6_DATA4), + PINMUX_IPSR_GPSR(IP0_5, DU0_DR5_Y7_DATA5), + PINMUX_IPSR_GPSR(IP0_6, DU0_DR6_Y8_DATA6), + PINMUX_IPSR_GPSR(IP0_7, DU0_DR7_Y9_DATA7), + PINMUX_IPSR_GPSR(IP0_8, DU0_DG0_DATA8), + PINMUX_IPSR_GPSR(IP0_9, DU0_DG1_DATA9), + PINMUX_IPSR_GPSR(IP0_10, DU0_DG2_C6_DATA10), + PINMUX_IPSR_GPSR(IP0_11, DU0_DG3_C7_DATA11), + PINMUX_IPSR_GPSR(IP0_12, DU0_DG4_Y0_DATA12), + PINMUX_IPSR_GPSR(IP0_13, DU0_DG5_Y1_DATA13), + PINMUX_IPSR_GPSR(IP0_14, DU0_DG6_Y2_DATA14), + PINMUX_IPSR_GPSR(IP0_15, DU0_DG7_Y3_DATA15), + PINMUX_IPSR_GPSR(IP0_16, DU0_DB0), + PINMUX_IPSR_GPSR(IP0_17, DU0_DB1), + PINMUX_IPSR_GPSR(IP0_18, DU0_DB2_C0), + PINMUX_IPSR_GPSR(IP0_19, DU0_DB3_C1), + PINMUX_IPSR_GPSR(IP0_20, DU0_DB4_C2), + PINMUX_IPSR_GPSR(IP0_21, DU0_DB5_C3), + PINMUX_IPSR_GPSR(IP0_22, DU0_DB6_C4), + PINMUX_IPSR_GPSR(IP0_23, DU0_DB7_C5), + + /* IPSR1 */ + PINMUX_IPSR_GPSR(IP1_0, DU0_EXHSYNC_DU0_HSYNC), + PINMUX_IPSR_GPSR(IP1_1, DU0_EXVSYNC_DU0_VSYNC), + PINMUX_IPSR_GPSR(IP1_2, DU0_EXODDF_DU0_ODDF_DISP_CDE), + PINMUX_IPSR_GPSR(IP1_3, DU0_DISP), + PINMUX_IPSR_GPSR(IP1_4, DU0_CDE), + PINMUX_IPSR_GPSR(IP1_5, DU1_DR2_Y4_DATA0), + PINMUX_IPSR_GPSR(IP1_6, DU1_DR3_Y5_DATA1), + PINMUX_IPSR_GPSR(IP1_7, DU1_DR4_Y6_DATA2), + PINMUX_IPSR_GPSR(IP1_8, DU1_DR5_Y7_DATA3), + PINMUX_IPSR_GPSR(IP1_9, DU1_DR6_DATA4), + PINMUX_IPSR_GPSR(IP1_10, DU1_DR7_DATA5), + PINMUX_IPSR_GPSR(IP1_11, DU1_DG2_C6_DATA6), + PINMUX_IPSR_GPSR(IP1_12, DU1_DG3_C7_DATA7), + PINMUX_IPSR_GPSR(IP1_13, DU1_DG4_Y0_DATA8), + PINMUX_IPSR_GPSR(IP1_14, DU1_DG5_Y1_DATA9), + PINMUX_IPSR_GPSR(IP1_15, DU1_DG6_Y2_DATA10), + PINMUX_IPSR_GPSR(IP1_16, DU1_DG7_Y3_DATA11), + PINMUX_IPSR_GPSR(IP1_17, A20), + PINMUX_IPSR_GPSR(IP1_17, MOSI_IO0), + PINMUX_IPSR_GPSR(IP1_18, A21), + PINMUX_IPSR_GPSR(IP1_18, MISO_IO1), + PINMUX_IPSR_GPSR(IP1_19, A22), + PINMUX_IPSR_GPSR(IP1_19, IO2), + PINMUX_IPSR_GPSR(IP1_20, A23), + PINMUX_IPSR_GPSR(IP1_20, IO3), + PINMUX_IPSR_GPSR(IP1_21, A24), + PINMUX_IPSR_GPSR(IP1_21, SPCLK), + PINMUX_IPSR_GPSR(IP1_22, A25), + PINMUX_IPSR_GPSR(IP1_22, SSL), + + /* IPSR2 */ + PINMUX_IPSR_GPSR(IP2_0, VI2_CLK), + PINMUX_IPSR_GPSR(IP2_0, AVB_RX_CLK), + PINMUX_IPSR_GPSR(IP2_1, VI2_CLKENB), + PINMUX_IPSR_GPSR(IP2_1, AVB_RX_DV), + PINMUX_IPSR_GPSR(IP2_2, VI2_HSYNC_N), + PINMUX_IPSR_GPSR(IP2_2, AVB_RXD0), + PINMUX_IPSR_GPSR(IP2_3, VI2_VSYNC_N), + PINMUX_IPSR_GPSR(IP2_3, AVB_RXD1), + PINMUX_IPSR_GPSR(IP2_4, VI2_D0_C0), + PINMUX_IPSR_GPSR(IP2_4, AVB_RXD2), + PINMUX_IPSR_GPSR(IP2_5, VI2_D1_C1), + PINMUX_IPSR_GPSR(IP2_5, AVB_RXD3), + PINMUX_IPSR_GPSR(IP2_6, VI2_D2_C2), + PINMUX_IPSR_GPSR(IP2_6, AVB_RXD4), + PINMUX_IPSR_GPSR(IP2_7, VI2_D3_C3), + PINMUX_IPSR_GPSR(IP2_7, AVB_RXD5), + PINMUX_IPSR_GPSR(IP2_8, VI2_D4_C4), + PINMUX_IPSR_GPSR(IP2_8, AVB_RXD6), + PINMUX_IPSR_GPSR(IP2_9, VI2_D5_C5), + PINMUX_IPSR_GPSR(IP2_9, AVB_RXD7), + PINMUX_IPSR_GPSR(IP2_10, VI2_D6_C6), + PINMUX_IPSR_GPSR(IP2_10, AVB_RX_ER), + PINMUX_IPSR_GPSR(IP2_11, VI2_D7_C7), + PINMUX_IPSR_GPSR(IP2_11, AVB_COL), + PINMUX_IPSR_GPSR(IP2_12, VI2_D8_Y0), + PINMUX_IPSR_GPSR(IP2_12, AVB_TXD3), + PINMUX_IPSR_GPSR(IP2_13, VI2_D9_Y1), + PINMUX_IPSR_GPSR(IP2_13, AVB_TX_EN), + PINMUX_IPSR_GPSR(IP2_14, VI2_D10_Y2), + PINMUX_IPSR_GPSR(IP2_14, AVB_TXD0), + PINMUX_IPSR_GPSR(IP2_15, VI2_D11_Y3), + PINMUX_IPSR_GPSR(IP2_15, AVB_TXD1), + PINMUX_IPSR_GPSR(IP2_16, VI2_FIELD), + PINMUX_IPSR_GPSR(IP2_16, AVB_TXD2), + + /* IPSR3 */ + PINMUX_IPSR_GPSR(IP3_0, VI3_CLK), + PINMUX_IPSR_GPSR(IP3_0, AVB_TX_CLK), + PINMUX_IPSR_GPSR(IP3_1, VI3_CLKENB), + PINMUX_IPSR_GPSR(IP3_1, AVB_TXD4), + PINMUX_IPSR_GPSR(IP3_2, VI3_HSYNC_N), + PINMUX_IPSR_GPSR(IP3_2, AVB_TXD5), + PINMUX_IPSR_GPSR(IP3_3, VI3_VSYNC_N), + PINMUX_IPSR_GPSR(IP3_3, AVB_TXD6), + PINMUX_IPSR_GPSR(IP3_4, VI3_D0_C0), + PINMUX_IPSR_GPSR(IP3_4, AVB_TXD7), + PINMUX_IPSR_GPSR(IP3_5, VI3_D1_C1), + PINMUX_IPSR_GPSR(IP3_5, AVB_TX_ER), + PINMUX_IPSR_GPSR(IP3_6, VI3_D2_C2), + PINMUX_IPSR_GPSR(IP3_6, AVB_GTX_CLK), + PINMUX_IPSR_GPSR(IP3_7, VI3_D3_C3), + PINMUX_IPSR_GPSR(IP3_7, AVB_MDC), + PINMUX_IPSR_GPSR(IP3_8, VI3_D4_C4), + PINMUX_IPSR_GPSR(IP3_8, AVB_MDIO), + PINMUX_IPSR_GPSR(IP3_9, VI3_D5_C5), + PINMUX_IPSR_GPSR(IP3_9, AVB_LINK), + PINMUX_IPSR_GPSR(IP3_10, VI3_D6_C6), + PINMUX_IPSR_GPSR(IP3_10, AVB_MAGIC), + PINMUX_IPSR_GPSR(IP3_11, VI3_D7_C7), + PINMUX_IPSR_GPSR(IP3_11, AVB_PHY_INT), + PINMUX_IPSR_GPSR(IP3_12, VI3_D8_Y0), + PINMUX_IPSR_GPSR(IP3_12, AVB_CRS), + PINMUX_IPSR_GPSR(IP3_13, VI3_D9_Y1), + PINMUX_IPSR_GPSR(IP3_13, AVB_GTXREFCLK), + PINMUX_IPSR_GPSR(IP3_14, VI3_D11_Y3), + PINMUX_IPSR_GPSR(IP3_14, AVB_AVTP_MATCH), + + /* IPSR4 */ + PINMUX_IPSR_GPSR(IP4_0, VI4_CLKENB), + PINMUX_IPSR_GPSR(IP4_0, VI0_D12_G4_Y4), + PINMUX_IPSR_GPSR(IP4_1, VI4_HSYNC_N), + PINMUX_IPSR_GPSR(IP4_1, VI0_D13_G5_Y5), + PINMUX_IPSR_GPSR(IP4_3_2, VI4_VSYNC_N), + PINMUX_IPSR_GPSR(IP4_3_2, VI0_D14_G6_Y6), + PINMUX_IPSR_GPSR(IP4_4, VI4_D0_C0), + PINMUX_IPSR_GPSR(IP4_4, VI0_D15_G7_Y7), + PINMUX_IPSR_GPSR(IP4_6_5, VI4_D1_C1), + PINMUX_IPSR_GPSR(IP4_6_5, VI0_D16_R0), + PINMUX_IPSR_MSEL(IP4_6_5, VI1_D12_G4_Y4, SEL_VI1_0), + PINMUX_IPSR_GPSR(IP4_8_7, VI4_D2_C2), + PINMUX_IPSR_GPSR(IP4_8_7, VI0_D17_R1), + PINMUX_IPSR_MSEL(IP4_8_7, VI1_D13_G5_Y5, SEL_VI1_0), + PINMUX_IPSR_GPSR(IP4_10_9, VI4_D3_C3), + PINMUX_IPSR_GPSR(IP4_10_9, VI0_D18_R2), + PINMUX_IPSR_MSEL(IP4_10_9, VI1_D14_G6_Y6, SEL_VI1_0), + PINMUX_IPSR_GPSR(IP4_12_11, VI4_D4_C4), + PINMUX_IPSR_GPSR(IP4_12_11, VI0_D19_R3), + PINMUX_IPSR_MSEL(IP4_12_11, VI1_D15_G7_Y7, SEL_VI1_0), + PINMUX_IPSR_GPSR(IP4_14_13, VI4_D5_C5), + PINMUX_IPSR_GPSR(IP4_14_13, VI0_D20_R4), + PINMUX_IPSR_GPSR(IP4_14_13, VI2_D12_Y4), + PINMUX_IPSR_GPSR(IP4_16_15, VI4_D6_C6), + PINMUX_IPSR_GPSR(IP4_16_15, VI0_D21_R5), + PINMUX_IPSR_GPSR(IP4_16_15, VI2_D13_Y5), + PINMUX_IPSR_GPSR(IP4_18_17, VI4_D7_C7), + PINMUX_IPSR_GPSR(IP4_18_17, VI0_D22_R6), + PINMUX_IPSR_GPSR(IP4_18_17, VI2_D14_Y6), + PINMUX_IPSR_GPSR(IP4_20_19, VI4_D8_Y0), + PINMUX_IPSR_GPSR(IP4_20_19, VI0_D23_R7), + PINMUX_IPSR_GPSR(IP4_20_19, VI2_D15_Y7), + PINMUX_IPSR_GPSR(IP4_21, VI4_D9_Y1), + PINMUX_IPSR_GPSR(IP4_21, VI3_D12_Y4), + PINMUX_IPSR_GPSR(IP4_22, VI4_D10_Y2), + PINMUX_IPSR_GPSR(IP4_22, VI3_D13_Y5), + PINMUX_IPSR_GPSR(IP4_23, VI4_D11_Y3), + PINMUX_IPSR_GPSR(IP4_23, VI3_D14_Y6), + PINMUX_IPSR_GPSR(IP4_24, VI4_FIELD), + PINMUX_IPSR_GPSR(IP4_24, VI3_D15_Y7), + + /* IPSR5 */ + PINMUX_IPSR_GPSR(IP5_0, VI5_CLKENB), + PINMUX_IPSR_MSEL(IP5_0, VI1_D12_G4_Y4_B, SEL_VI1_1), + PINMUX_IPSR_GPSR(IP5_1, VI5_HSYNC_N), + PINMUX_IPSR_MSEL(IP5_1, VI1_D13_G5_Y5_B, SEL_VI1_1), + PINMUX_IPSR_GPSR(IP5_2, VI5_VSYNC_N), + PINMUX_IPSR_MSEL(IP5_2, VI1_D14_G6_Y6_B, SEL_VI1_1), + PINMUX_IPSR_GPSR(IP5_3, VI5_D0_C0), + PINMUX_IPSR_MSEL(IP5_3, VI1_D15_G7_Y7_B, SEL_VI1_1), + PINMUX_IPSR_GPSR(IP5_4, VI5_D1_C1), + PINMUX_IPSR_GPSR(IP5_4, VI1_D16_R0), + PINMUX_IPSR_GPSR(IP5_5, VI5_D2_C2), + PINMUX_IPSR_GPSR(IP5_5, VI1_D17_R1), + PINMUX_IPSR_GPSR(IP5_6, VI5_D3_C3), + PINMUX_IPSR_GPSR(IP5_6, VI1_D18_R2), + PINMUX_IPSR_GPSR(IP5_7, VI5_D4_C4), + PINMUX_IPSR_GPSR(IP5_7, VI1_D19_R3), + PINMUX_IPSR_GPSR(IP5_8, VI5_D5_C5), + PINMUX_IPSR_GPSR(IP5_8, VI1_D20_R4), + PINMUX_IPSR_GPSR(IP5_9, VI5_D6_C6), + PINMUX_IPSR_GPSR(IP5_9, VI1_D21_R5), + PINMUX_IPSR_GPSR(IP5_10, VI5_D7_C7), + PINMUX_IPSR_GPSR(IP5_10, VI1_D22_R6), + PINMUX_IPSR_GPSR(IP5_11, VI5_D8_Y0), + PINMUX_IPSR_GPSR(IP5_11, VI1_D23_R7), + + /* IPSR6 */ + PINMUX_IPSR_GPSR(IP6_0, MSIOF0_SCK), + PINMUX_IPSR_GPSR(IP6_0, HSCK0), + PINMUX_IPSR_GPSR(IP6_1, MSIOF0_SYNC), + PINMUX_IPSR_GPSR(IP6_1, HCTS0_N), + PINMUX_IPSR_GPSR(IP6_2, MSIOF0_TXD), + PINMUX_IPSR_GPSR(IP6_2, HTX0), + PINMUX_IPSR_GPSR(IP6_3, MSIOF0_RXD), + PINMUX_IPSR_GPSR(IP6_3, HRX0), + PINMUX_IPSR_GPSR(IP6_4, MSIOF1_SCK), + PINMUX_IPSR_GPSR(IP6_4, HSCK1), + PINMUX_IPSR_GPSR(IP6_5, MSIOF1_SYNC), + PINMUX_IPSR_GPSR(IP6_5, HRTS1_N), + PINMUX_IPSR_GPSR(IP6_6, MSIOF1_TXD), + PINMUX_IPSR_GPSR(IP6_6, HTX1), + PINMUX_IPSR_GPSR(IP6_7, MSIOF1_RXD), + PINMUX_IPSR_GPSR(IP6_7, HRX1), + PINMUX_IPSR_GPSR(IP6_9_8, DRACK0), + PINMUX_IPSR_GPSR(IP6_9_8, SCK2), + PINMUX_IPSR_GPSR(IP6_11_10, DACK0), + PINMUX_IPSR_GPSR(IP6_11_10, TX2), + PINMUX_IPSR_GPSR(IP6_13_12, DREQ0_N), + PINMUX_IPSR_GPSR(IP6_13_12, RX2), + PINMUX_IPSR_GPSR(IP6_15_14, DACK1), + PINMUX_IPSR_GPSR(IP6_15_14, SCK3), + PINMUX_IPSR_GPSR(IP6_16, TX3), + PINMUX_IPSR_GPSR(IP6_18_17, DREQ1_N), + PINMUX_IPSR_GPSR(IP6_18_17, RX3), + + /* IPSR7 */ + PINMUX_IPSR_GPSR(IP7_1_0, PWM0), + PINMUX_IPSR_GPSR(IP7_1_0, TCLK1), + PINMUX_IPSR_GPSR(IP7_1_0, FSO_CFE_0), + PINMUX_IPSR_GPSR(IP7_3_2, PWM1), + PINMUX_IPSR_GPSR(IP7_3_2, TCLK2), + PINMUX_IPSR_GPSR(IP7_3_2, FSO_CFE_1), + PINMUX_IPSR_GPSR(IP7_5_4, PWM2), + PINMUX_IPSR_GPSR(IP7_5_4, TCLK3), + PINMUX_IPSR_GPSR(IP7_5_4, FSO_TOE), + PINMUX_IPSR_GPSR(IP7_6, PWM3), + PINMUX_IPSR_GPSR(IP7_7, PWM4), + PINMUX_IPSR_GPSR(IP7_9_8, SSI_SCK34), + PINMUX_IPSR_GPSR(IP7_9_8, TPU0TO0), + PINMUX_IPSR_GPSR(IP7_11_10, SSI_WS34), + PINMUX_IPSR_GPSR(IP7_11_10, TPU0TO1), + PINMUX_IPSR_GPSR(IP7_13_12, SSI_SDATA3), + PINMUX_IPSR_GPSR(IP7_13_12, TPU0TO2), + PINMUX_IPSR_GPSR(IP7_15_14, SSI_SCK4), + PINMUX_IPSR_GPSR(IP7_15_14, TPU0TO3), + PINMUX_IPSR_GPSR(IP7_16, SSI_WS4), + PINMUX_IPSR_GPSR(IP7_17, SSI_SDATA4), + PINMUX_IPSR_GPSR(IP7_18, AUDIO_CLKOUT), + PINMUX_IPSR_GPSR(IP7_19, AUDIO_CLKA), + PINMUX_IPSR_GPSR(IP7_20, AUDIO_CLKB), +}; + +static const struct sh_pfc_pin pinmux_pins[] = { + PINMUX_GPIO_GP_ALL(), +}; + +/* - INTC ------------------------------------------------------------------- */ +static const unsigned int intc_irq0_pins[] = { + /* IRQ0 */ + RCAR_GP_PIN(3, 19), +}; +static const unsigned int intc_irq0_mux[] = { + IRQ0_MARK, +}; +static const unsigned int intc_irq1_pins[] = { + /* IRQ1 */ + RCAR_GP_PIN(3, 20), +}; +static const unsigned int intc_irq1_mux[] = { + IRQ1_MARK, +}; +static const unsigned int intc_irq2_pins[] = { + /* IRQ2 */ + RCAR_GP_PIN(3, 21), +}; +static const unsigned int intc_irq2_mux[] = { + IRQ2_MARK, +}; +static const unsigned int intc_irq3_pins[] = { + /* IRQ3 */ + RCAR_GP_PIN(3, 22), +}; +static const unsigned int intc_irq3_mux[] = { + IRQ3_MARK, +}; +/* - LBSC ------------------------------------------------------------------- */ +static const unsigned int lbsc_cs0_pins[] = { + /* CS0# */ + RCAR_GP_PIN(3, 27), +}; +static const unsigned int lbsc_cs0_mux[] = { + CS0_N_MARK, +}; +static const unsigned int lbsc_cs1_pins[] = { + /* CS1#_A26 */ + RCAR_GP_PIN(3, 6), +}; +static const unsigned int lbsc_cs1_mux[] = { + CS1_N_A26_MARK, +}; +static const unsigned int lbsc_ex_cs0_pins[] = { + /* EX_CS0# */ + RCAR_GP_PIN(3, 7), +}; +static const unsigned int lbsc_ex_cs0_mux[] = { + EX_CS0_N_MARK, +}; +static const unsigned int lbsc_ex_cs1_pins[] = { + /* EX_CS1# */ + RCAR_GP_PIN(3, 8), +}; +static const unsigned int lbsc_ex_cs1_mux[] = { + EX_CS1_N_MARK, +}; +static const unsigned int lbsc_ex_cs2_pins[] = { + /* EX_CS2# */ + RCAR_GP_PIN(3, 9), +}; +static const unsigned int lbsc_ex_cs2_mux[] = { + EX_CS2_N_MARK, +}; +static const unsigned int lbsc_ex_cs3_pins[] = { + /* EX_CS3# */ + RCAR_GP_PIN(3, 10), +}; +static const unsigned int lbsc_ex_cs3_mux[] = { + EX_CS3_N_MARK, +}; +static const unsigned int lbsc_ex_cs4_pins[] = { + /* EX_CS4# */ + RCAR_GP_PIN(3, 11), +}; +static const unsigned int lbsc_ex_cs4_mux[] = { + EX_CS4_N_MARK, +}; +static const unsigned int lbsc_ex_cs5_pins[] = { + /* EX_CS5# */ + RCAR_GP_PIN(3, 12), +}; +static const unsigned int lbsc_ex_cs5_mux[] = { + EX_CS5_N_MARK, +}; +/* - SCIF0 ------------------------------------------------------------------ */ +static const unsigned int scif0_data_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(10, 14), RCAR_GP_PIN(10, 13), +}; +static const unsigned int scif0_data_mux[] = { + RX0_MARK, TX0_MARK, +}; +static const unsigned int scif0_clk_pins[] = { + /* SCK */ + RCAR_GP_PIN(10, 10), +}; +static const unsigned int scif0_clk_mux[] = { + SCK0_MARK, +}; +static const unsigned int scif0_ctrl_pins[] = { + /* RTS, CTS */ + RCAR_GP_PIN(10, 12), RCAR_GP_PIN(10, 11), +}; +static const unsigned int scif0_ctrl_mux[] = { + RTS0_N_MARK, CTS0_N_MARK, +}; +/* - SCIF3 ------------------------------------------------------------------ */ +static const unsigned int scif3_data_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(10, 25), RCAR_GP_PIN(10, 24), +}; +static const unsigned int scif3_data_mux[] = { + RX3_MARK, TX3_MARK, +}; +static const unsigned int scif3_clk_pins[] = { + /* SCK */ + RCAR_GP_PIN(10, 23), +}; +static const unsigned int scif3_clk_mux[] = { + SCK3_MARK, +}; + +static const struct sh_pfc_pin_group pinmux_groups[] = { + SH_PFC_PIN_GROUP(intc_irq0), + SH_PFC_PIN_GROUP(intc_irq1), + SH_PFC_PIN_GROUP(intc_irq2), + SH_PFC_PIN_GROUP(intc_irq3), + SH_PFC_PIN_GROUP(lbsc_cs0), + SH_PFC_PIN_GROUP(lbsc_cs1), + SH_PFC_PIN_GROUP(lbsc_ex_cs0), + SH_PFC_PIN_GROUP(lbsc_ex_cs1), + SH_PFC_PIN_GROUP(lbsc_ex_cs2), + SH_PFC_PIN_GROUP(lbsc_ex_cs3), + SH_PFC_PIN_GROUP(lbsc_ex_cs4), + SH_PFC_PIN_GROUP(lbsc_ex_cs5), + SH_PFC_PIN_GROUP(scif0_data), + SH_PFC_PIN_GROUP(scif0_clk), + SH_PFC_PIN_GROUP(scif0_ctrl), + SH_PFC_PIN_GROUP(scif3_data), + SH_PFC_PIN_GROUP(scif3_clk), +}; + +static const char * const intc_groups[] = { + "intc_irq0", + "intc_irq1", + "intc_irq2", + "intc_irq3", +}; + +static const char * const lbsc_groups[] = { + "lbsc_cs0", + "lbsc_cs1", + "lbsc_ex_cs0", + "lbsc_ex_cs1", + "lbsc_ex_cs2", + "lbsc_ex_cs3", + "lbsc_ex_cs4", + "lbsc_ex_cs5", +}; + +static const char * const scif0_groups[] = { + "scif0_data", + "scif0_clk", + "scif0_ctrl", +}; + +static const char * const scif3_groups[] = { + "scif3_data", + "scif3_clk", +}; + +static const struct sh_pfc_function pinmux_functions[] = { + SH_PFC_FUNCTION(intc), + SH_PFC_FUNCTION(lbsc), + SH_PFC_FUNCTION(scif0), + SH_PFC_FUNCTION(scif3), +}; + +static const struct pinmux_cfg_reg pinmux_config_regs[] = { + { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) { + 0, 0, + 0, 0, + 0, 0, + GP_0_28_FN, FN_IP1_4, + GP_0_27_FN, FN_IP1_3, + GP_0_26_FN, FN_IP1_2, + GP_0_25_FN, FN_IP1_1, + GP_0_24_FN, FN_IP1_0, + GP_0_23_FN, FN_IP0_23, + GP_0_22_FN, FN_IP0_22, + GP_0_21_FN, FN_IP0_21, + GP_0_20_FN, FN_IP0_20, + GP_0_19_FN, FN_IP0_19, + GP_0_18_FN, FN_IP0_18, + GP_0_17_FN, FN_IP0_17, + GP_0_16_FN, FN_IP0_16, + GP_0_15_FN, FN_IP0_15, + GP_0_14_FN, FN_IP0_14, + GP_0_13_FN, FN_IP0_13, + GP_0_12_FN, FN_IP0_12, + GP_0_11_FN, FN_IP0_11, + GP_0_10_FN, FN_IP0_10, + GP_0_9_FN, FN_IP0_9, + GP_0_8_FN, FN_IP0_8, + GP_0_7_FN, FN_IP0_7, + GP_0_6_FN, FN_IP0_6, + GP_0_5_FN, FN_IP0_5, + GP_0_4_FN, FN_IP0_4, + GP_0_3_FN, FN_IP0_3, + GP_0_2_FN, FN_IP0_2, + GP_0_1_FN, FN_IP0_1, + GP_0_0_FN, FN_IP0_0 } + }, + { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1) { + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + GP_1_22_FN, FN_DU1_CDE, + GP_1_21_FN, FN_DU1_DISP, + GP_1_20_FN, FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, + GP_1_19_FN, FN_DU1_EXVSYNC_DU1_VSYNC, + GP_1_18_FN, FN_DU1_EXHSYNC_DU1_HSYNC, + GP_1_17_FN, FN_DU1_DB7_C5, + GP_1_16_FN, FN_DU1_DB6_C4, + GP_1_15_FN, FN_DU1_DB5_C3_DATA15, + GP_1_14_FN, FN_DU1_DB4_C2_DATA14, + GP_1_13_FN, FN_DU1_DB3_C1_DATA13, + GP_1_12_FN, FN_DU1_DB2_C0_DATA12, + GP_1_11_FN, FN_IP1_16, + GP_1_10_FN, FN_IP1_15, + GP_1_9_FN, FN_IP1_14, + GP_1_8_FN, FN_IP1_13, + GP_1_7_FN, FN_IP1_12, + GP_1_6_FN, FN_IP1_11, + GP_1_5_FN, FN_IP1_10, + GP_1_4_FN, FN_IP1_9, + GP_1_3_FN, FN_IP1_8, + GP_1_2_FN, FN_IP1_7, + GP_1_1_FN, FN_IP1_6, + GP_1_0_FN, FN_IP1_5, } + }, + { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1) { + GP_2_31_FN, FN_A15, + GP_2_30_FN, FN_A14, + GP_2_29_FN, FN_A13, + GP_2_28_FN, FN_A12, + GP_2_27_FN, FN_A11, + GP_2_26_FN, FN_A10, + GP_2_25_FN, FN_A9, + GP_2_24_FN, FN_A8, + GP_2_23_FN, FN_A7, + GP_2_22_FN, FN_A6, + GP_2_21_FN, FN_A5, + GP_2_20_FN, FN_A4, + GP_2_19_FN, FN_A3, + GP_2_18_FN, FN_A2, + GP_2_17_FN, FN_A1, + GP_2_16_FN, FN_A0, + GP_2_15_FN, FN_D15, + GP_2_14_FN, FN_D14, + GP_2_13_FN, FN_D13, + GP_2_12_FN, FN_D12, + GP_2_11_FN, FN_D11, + GP_2_10_FN, FN_D10, + GP_2_9_FN, FN_D9, + GP_2_8_FN, FN_D8, + GP_2_7_FN, FN_D7, + GP_2_6_FN, FN_D6, + GP_2_5_FN, FN_D5, + GP_2_4_FN, FN_D4, + GP_2_3_FN, FN_D3, + GP_2_2_FN, FN_D2, + GP_2_1_FN, FN_D1, + GP_2_0_FN, FN_D0 } + }, + { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1) { + 0, 0, + 0, 0, + 0, 0, + 0, 0, + GP_3_27_FN, FN_CS0_N, + GP_3_26_FN, FN_IP1_22, + GP_3_25_FN, FN_IP1_21, + GP_3_24_FN, FN_IP1_20, + GP_3_23_FN, FN_IP1_19, + GP_3_22_FN, FN_IRQ3, + GP_3_21_FN, FN_IRQ2, + GP_3_20_FN, FN_IRQ1, + GP_3_19_FN, FN_IRQ0, + GP_3_18_FN, FN_EX_WAIT0, + GP_3_17_FN, FN_WE1_N, + GP_3_16_FN, FN_WE0_N, + GP_3_15_FN, FN_RD_WR_N, + GP_3_14_FN, FN_RD_N, + GP_3_13_FN, FN_BS_N, + GP_3_12_FN, FN_EX_CS5_N, + GP_3_11_FN, FN_EX_CS4_N, + GP_3_10_FN, FN_EX_CS3_N, + GP_3_9_FN, FN_EX_CS2_N, + GP_3_8_FN, FN_EX_CS1_N, + GP_3_7_FN, FN_EX_CS0_N, + GP_3_6_FN, FN_CS1_N_A26, + GP_3_5_FN, FN_IP1_18, + GP_3_4_FN, FN_IP1_17, + GP_3_3_FN, FN_A19, + GP_3_2_FN, FN_A18, + GP_3_1_FN, FN_A17, + GP_3_0_FN, FN_A16 } + }, + { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1) { + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + GP_4_16_FN, FN_VI0_FIELD, + GP_4_15_FN, FN_VI0_D11_G3_Y3, + GP_4_14_FN, FN_VI0_D10_G2_Y2, + GP_4_13_FN, FN_VI0_D9_G1_Y1, + GP_4_12_FN, FN_VI0_D8_G0_Y0, + GP_4_11_FN, FN_VI0_D7_B7_C7, + GP_4_10_FN, FN_VI0_D6_B6_C6, + GP_4_9_FN, FN_VI0_D5_B5_C5, + GP_4_8_FN, FN_VI0_D4_B4_C4, + GP_4_7_FN, FN_VI0_D3_B3_C3, + GP_4_6_FN, FN_VI0_D2_B2_C2, + GP_4_5_FN, FN_VI0_D1_B1_C1, + GP_4_4_FN, FN_VI0_D0_B0_C0, + GP_4_3_FN, FN_VI0_VSYNC_N, + GP_4_2_FN, FN_VI0_HSYNC_N, + GP_4_1_FN, FN_VI0_CLKENB, + GP_4_0_FN, FN_VI0_CLK } + }, + { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1) { + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + GP_5_16_FN, FN_VI1_FIELD, + GP_5_15_FN, FN_VI1_D11_G3_Y3, + GP_5_14_FN, FN_VI1_D10_G2_Y2, + GP_5_13_FN, FN_VI1_D9_G1_Y1, + GP_5_12_FN, FN_VI1_D8_G0_Y0, + GP_5_11_FN, FN_VI1_D7_B7_C7, + GP_5_10_FN, FN_VI1_D6_B6_C6, + GP_5_9_FN, FN_VI1_D5_B5_C5, + GP_5_8_FN, FN_VI1_D4_B4_C4, + GP_5_7_FN, FN_VI1_D3_B3_C3, + GP_5_6_FN, FN_VI1_D2_B2_C2, + GP_5_5_FN, FN_VI1_D1_B1_C1, + GP_5_4_FN, FN_VI1_D0_B0_C0, + GP_5_3_FN, FN_VI1_VSYNC_N, + GP_5_2_FN, FN_VI1_HSYNC_N, + GP_5_1_FN, FN_VI1_CLKENB, + GP_5_0_FN, FN_VI1_CLK } + }, + { PINMUX_CFG_REG("GPSR6", 0xE606001C, 32, 1) { + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + GP_6_16_FN, FN_IP2_16, + GP_6_15_FN, FN_IP2_15, + GP_6_14_FN, FN_IP2_14, + GP_6_13_FN, FN_IP2_13, + GP_6_12_FN, FN_IP2_12, + GP_6_11_FN, FN_IP2_11, + GP_6_10_FN, FN_IP2_10, + GP_6_9_FN, FN_IP2_9, + GP_6_8_FN, FN_IP2_8, + GP_6_7_FN, FN_IP2_7, + GP_6_6_FN, FN_IP2_6, + GP_6_5_FN, FN_IP2_5, + GP_6_4_FN, FN_IP2_4, + GP_6_3_FN, FN_IP2_3, + GP_6_2_FN, FN_IP2_2, + GP_6_1_FN, FN_IP2_1, + GP_6_0_FN, FN_IP2_0 } + }, + { PINMUX_CFG_REG("GPSR7", 0xE6060020, 32, 1) { + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + GP_7_16_FN, FN_VI3_FIELD, + GP_7_15_FN, FN_IP3_14, + GP_7_14_FN, FN_VI3_D10_Y2, + GP_7_13_FN, FN_IP3_13, + GP_7_12_FN, FN_IP3_12, + GP_7_11_FN, FN_IP3_11, + GP_7_10_FN, FN_IP3_10, + GP_7_9_FN, FN_IP3_9, + GP_7_8_FN, FN_IP3_8, + GP_7_7_FN, FN_IP3_7, + GP_7_6_FN, FN_IP3_6, + GP_7_5_FN, FN_IP3_5, + GP_7_4_FN, FN_IP3_4, + GP_7_3_FN, FN_IP3_3, + GP_7_2_FN, FN_IP3_2, + GP_7_1_FN, FN_IP3_1, + GP_7_0_FN, FN_IP3_0 } + }, + { PINMUX_CFG_REG("GPSR8", 0xE6060024, 32, 1) { + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + GP_8_16_FN, FN_IP4_24, + GP_8_15_FN, FN_IP4_23, + GP_8_14_FN, FN_IP4_22, + GP_8_13_FN, FN_IP4_21, + GP_8_12_FN, FN_IP4_20_19, + GP_8_11_FN, FN_IP4_18_17, + GP_8_10_FN, FN_IP4_16_15, + GP_8_9_FN, FN_IP4_14_13, + GP_8_8_FN, FN_IP4_12_11, + GP_8_7_FN, FN_IP4_10_9, + GP_8_6_FN, FN_IP4_8_7, + GP_8_5_FN, FN_IP4_6_5, + GP_8_4_FN, FN_IP4_4, + GP_8_3_FN, FN_IP4_3_2, + GP_8_2_FN, FN_IP4_1, + GP_8_1_FN, FN_IP4_0, + GP_8_0_FN, FN_VI4_CLK } + }, + { PINMUX_CFG_REG("GPSR9", 0xE6060028, 32, 1) { + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + GP_9_16_FN, FN_VI5_FIELD, + GP_9_15_FN, FN_VI5_D11_Y3, + GP_9_14_FN, FN_VI5_D10_Y2, + GP_9_13_FN, FN_VI5_D9_Y1, + GP_9_12_FN, FN_IP5_11, + GP_9_11_FN, FN_IP5_10, + GP_9_10_FN, FN_IP5_9, + GP_9_9_FN, FN_IP5_8, + GP_9_8_FN, FN_IP5_7, + GP_9_7_FN, FN_IP5_6, + GP_9_6_FN, FN_IP5_5, + GP_9_5_FN, FN_IP5_4, + GP_9_4_FN, FN_IP5_3, + GP_9_3_FN, FN_IP5_2, + GP_9_2_FN, FN_IP5_1, + GP_9_1_FN, FN_IP5_0, + GP_9_0_FN, FN_VI5_CLK } + }, + { PINMUX_CFG_REG("GPSR10", 0xE606002C, 32, 1) { + GP_10_31_FN, FN_CAN1_RX, + GP_10_30_FN, FN_CAN1_TX, + GP_10_29_FN, FN_CAN_CLK, + GP_10_28_FN, FN_CAN0_RX, + GP_10_27_FN, FN_CAN0_TX, + GP_10_26_FN, FN_SCIF_CLK, + GP_10_25_FN, FN_IP6_18_17, + GP_10_24_FN, FN_IP6_16, + GP_10_23_FN, FN_IP6_15_14, + GP_10_22_FN, FN_IP6_13_12, + GP_10_21_FN, FN_IP6_11_10, + GP_10_20_FN, FN_IP6_9_8, + GP_10_19_FN, FN_RX1, + GP_10_18_FN, FN_TX1, + GP_10_17_FN, FN_RTS1_N, + GP_10_16_FN, FN_CTS1_N, + GP_10_15_FN, FN_SCK1, + GP_10_14_FN, FN_RX0, + GP_10_13_FN, FN_TX0, + GP_10_12_FN, FN_RTS0_N, + GP_10_11_FN, FN_CTS0_N, + GP_10_10_FN, FN_SCK0, + GP_10_9_FN, FN_IP6_7, + GP_10_8_FN, FN_IP6_6, + GP_10_7_FN, FN_HCTS1_N, + GP_10_6_FN, FN_IP6_5, + GP_10_5_FN, FN_IP6_4, + GP_10_4_FN, FN_IP6_3, + GP_10_3_FN, FN_IP6_2, + GP_10_2_FN, FN_HRTS0_N, + GP_10_1_FN, FN_IP6_1, + GP_10_0_FN, FN_IP6_0 } + }, + { PINMUX_CFG_REG("GPSR11", 0xE6060030, 32, 1) { + 0, 0, + 0, 0, + GP_11_29_FN, FN_AVS2, + GP_11_28_FN, FN_AVS1, + GP_11_27_FN, FN_ADICHS2, + GP_11_26_FN, FN_ADICHS1, + GP_11_25_FN, FN_ADICHS0, + GP_11_24_FN, FN_ADIDATA, + GP_11_23_FN, FN_ADICS_SAMP, + GP_11_22_FN, FN_ADICLK, + GP_11_21_FN, FN_IP7_20, + GP_11_20_FN, FN_IP7_19, + GP_11_19_FN, FN_IP7_18, + GP_11_18_FN, FN_IP7_17, + GP_11_17_FN, FN_IP7_16, + GP_11_16_FN, FN_IP7_15_14, + GP_11_15_FN, FN_IP7_13_12, + GP_11_14_FN, FN_IP7_11_10, + GP_11_13_FN, FN_IP7_9_8, + GP_11_12_FN, FN_SD0_WP, + GP_11_11_FN, FN_SD0_CD, + GP_11_10_FN, FN_SD0_DAT3, + GP_11_9_FN, FN_SD0_DAT2, + GP_11_8_FN, FN_SD0_DAT1, + GP_11_7_FN, FN_SD0_DAT0, + GP_11_6_FN, FN_SD0_CMD, + GP_11_5_FN, FN_SD0_CLK, + GP_11_4_FN, FN_IP7_7, + GP_11_3_FN, FN_IP7_6, + GP_11_2_FN, FN_IP7_5_4, + GP_11_1_FN, FN_IP7_3_2, + GP_11_0_FN, FN_IP7_1_0 } + }, + { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060040, 32, + 4, 4, + 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1) { + /* IP0_31_28 [4] */ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* IP0_27_24 [4] */ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* IP0_23 [1] */ + FN_DU0_DB7_C5, 0, + /* IP0_22 [1] */ + FN_DU0_DB6_C4, 0, + /* IP0_21 [1] */ + FN_DU0_DB5_C3, 0, + /* IP0_20 [1] */ + FN_DU0_DB4_C2, 0, + /* IP0_19 [1] */ + FN_DU0_DB3_C1, 0, + /* IP0_18 [1] */ + FN_DU0_DB2_C0, 0, + /* IP0_17 [1] */ + FN_DU0_DB1, 0, + /* IP0_16 [1] */ + FN_DU0_DB0, 0, + /* IP0_15 [1] */ + FN_DU0_DG7_Y3_DATA15, 0, + /* IP0_14 [1] */ + FN_DU0_DG6_Y2_DATA14, 0, + /* IP0_13 [1] */ + FN_DU0_DG5_Y1_DATA13, 0, + /* IP0_12 [1] */ + FN_DU0_DG4_Y0_DATA12, 0, + /* IP0_11 [1] */ + FN_DU0_DG3_C7_DATA11, 0, + /* IP0_10 [1] */ + FN_DU0_DG2_C6_DATA10, 0, + /* IP0_9 [1] */ + FN_DU0_DG1_DATA9, 0, + /* IP0_8 [1] */ + FN_DU0_DG0_DATA8, 0, + /* IP0_7 [1] */ + FN_DU0_DR7_Y9_DATA7, 0, + /* IP0_6 [1] */ + FN_DU0_DR6_Y8_DATA6, 0, + /* IP0_5 [1] */ + FN_DU0_DR5_Y7_DATA5, 0, + /* IP0_4 [1] */ + FN_DU0_DR4_Y6_DATA4, 0, + /* IP0_3 [1] */ + FN_DU0_DR3_Y5_DATA3, 0, + /* IP0_2 [1] */ + FN_DU0_DR2_Y4_DATA2, 0, + /* IP0_1 [1] */ + FN_DU0_DR1_DATA1, 0, + /* IP0_0 [1] */ + FN_DU0_DR0_DATA0, 0 } + }, + { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060044, 32, + 4, 4, + 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1) { + /* IP1_31_28 [4] */ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* IP1_27_24 [4] */ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* IP1_23 [1] */ + 0, 0, + /* IP1_22 [1] */ + FN_A25, FN_SSL, + /* IP1_21 [1] */ + FN_A24, FN_SPCLK, + /* IP1_20 [1] */ + FN_A23, FN_IO3, + /* IP1_19 [1] */ + FN_A22, FN_IO2, + /* IP1_18 [1] */ + FN_A21, FN_MISO_IO1, + /* IP1_17 [1] */ + FN_A20, FN_MOSI_IO0, + /* IP1_16 [1] */ + FN_DU1_DG7_Y3_DATA11, 0, + /* IP1_15 [1] */ + FN_DU1_DG6_Y2_DATA10, 0, + /* IP1_14 [1] */ + FN_DU1_DG5_Y1_DATA9, 0, + /* IP1_13 [1] */ + FN_DU1_DG4_Y0_DATA8, 0, + /* IP1_12 [1] */ + FN_DU1_DG3_C7_DATA7, 0, + /* IP1_11 [1] */ + FN_DU1_DG2_C6_DATA6, 0, + /* IP1_10 [1] */ + FN_DU1_DR7_DATA5, 0, + /* IP1_9 [1] */ + FN_DU1_DR6_DATA4, 0, + /* IP1_8 [1] */ + FN_DU1_DR5_Y7_DATA3, 0, + /* IP1_7 [1] */ + FN_DU1_DR4_Y6_DATA2, 0, + /* IP1_6 [1] */ + FN_DU1_DR3_Y5_DATA1, 0, + /* IP1_5 [1] */ + FN_DU1_DR2_Y4_DATA0, 0, + /* IP1_4 [1] */ + FN_DU0_CDE, 0, + /* IP1_3 [1] */ + FN_DU0_DISP, 0, + /* IP1_2 [1] */ + FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, 0, + /* IP1_1 [1] */ + FN_DU0_EXVSYNC_DU0_VSYNC, 0, + /* IP1_0 [1] */ + FN_DU0_EXHSYNC_DU0_HSYNC, 0 } + }, + { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060048, 32, + 4, 4, + 4, 3, 1, + 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1) { + /* IP2_31_28 [4] */ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* IP2_27_24 [4] */ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* IP2_23_20 [4] */ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* IP2_19_17 [3] */ + 0, 0, 0, 0, 0, 0, 0, 0, + /* IP2_16 [1] */ + FN_VI2_FIELD, FN_AVB_TXD2, + /* IP2_15 [1] */ + FN_VI2_D11_Y3, FN_AVB_TXD1, + /* IP2_14 [1] */ + FN_VI2_D10_Y2, FN_AVB_TXD0, + /* IP2_13 [1] */ + FN_VI2_D9_Y1, FN_AVB_TX_EN, + /* IP2_12 [1] */ + FN_VI2_D8_Y0, FN_AVB_TXD3, + /* IP2_11 [1] */ + FN_VI2_D7_C7, FN_AVB_COL, + /* IP2_10 [1] */ + FN_VI2_D6_C6, FN_AVB_RX_ER, + /* IP2_9 [1] */ + FN_VI2_D5_C5, FN_AVB_RXD7, + /* IP2_8 [1] */ + FN_VI2_D4_C4, FN_AVB_RXD6, + /* IP2_7 [1] */ + FN_VI2_D3_C3, FN_AVB_RXD5, + /* IP2_6 [1] */ + FN_VI2_D2_C2, FN_AVB_RXD4, + /* IP2_5 [1] */ + FN_VI2_D1_C1, FN_AVB_RXD3, + /* IP2_4 [1] */ + FN_VI2_D0_C0, FN_AVB_RXD2, + /* IP2_3 [1] */ + FN_VI2_VSYNC_N, FN_AVB_RXD1, + /* IP2_2 [1] */ + FN_VI2_HSYNC_N, FN_AVB_RXD0, + /* IP2_1 [1] */ + FN_VI2_CLKENB, FN_AVB_RX_DV, + /* IP2_0 [1] */ + FN_VI2_CLK, FN_AVB_RX_CLK } + }, + { PINMUX_CFG_REG_VAR("IPSR3", 0xE606004C, 32, + 4, 4, + 4, 4, + 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1) { + /* IP3_31_28 [4] */ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* IP3_27_24 [4] */ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* IP3_23_20 [4] */ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* IP3_19_16 [4] */ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* IP3_15 [1] */ + 0, 0, + /* IP3_14 [1] */ + FN_VI3_D11_Y3, FN_AVB_AVTP_MATCH, + /* IP3_13 [1] */ + FN_VI3_D9_Y1, FN_AVB_GTXREFCLK, + /* IP3_12 [1] */ + FN_VI3_D8_Y0, FN_AVB_CRS, + /* IP3_11 [1] */ + FN_VI3_D7_C7, FN_AVB_PHY_INT, + /* IP3_10 [1] */ + FN_VI3_D6_C6, FN_AVB_MAGIC, + /* IP3_9 [1] */ + FN_VI3_D5_C5, FN_AVB_LINK, + /* IP3_8 [1] */ + FN_VI3_D4_C4, FN_AVB_MDIO, + /* IP3_7 [1] */ + FN_VI3_D3_C3, FN_AVB_MDC, + /* IP3_6 [1] */ + FN_VI3_D2_C2, FN_AVB_GTX_CLK, + /* IP3_5 [1] */ + FN_VI3_D1_C1, FN_AVB_TX_ER, + /* IP3_4 [1] */ + FN_VI3_D0_C0, FN_AVB_TXD7, + /* IP3_3 [1] */ + FN_VI3_VSYNC_N, FN_AVB_TXD6, + /* IP3_2 [1] */ + FN_VI3_HSYNC_N, FN_AVB_TXD5, + /* IP3_1 [1] */ + FN_VI3_CLKENB, FN_AVB_TXD4, + /* IP3_0 [1] */ + FN_VI3_CLK, FN_AVB_TX_CLK } + }, + { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060050, 32, + 4, 3, 1, + 1, 1, 1, 2, 2, 2, + 2, 2, 2, 2, 2, 1, 2, 1, 1) { + /* IP4_31_28 [4] */ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* IP4_27_25 [3] */ + 0, 0, 0, 0, 0, 0, 0, 0, + /* IP4_24 [1] */ + FN_VI4_FIELD, FN_VI3_D15_Y7, + /* IP4_23 [1] */ + FN_VI4_D11_Y3, FN_VI3_D14_Y6, + /* IP4_22 [1] */ + FN_VI4_D10_Y2, FN_VI3_D13_Y5, + /* IP4_21 [1] */ + FN_VI4_D9_Y1, FN_VI3_D12_Y4, + /* IP4_20_19 [2] */ + FN_VI4_D8_Y0, FN_VI0_D23_R7, FN_VI2_D15_Y7, 0, + /* IP4_18_17 [2] */ + FN_VI4_D7_C7, FN_VI0_D22_R6, FN_VI2_D14_Y6, 0, + /* IP4_16_15 [2] */ + FN_VI4_D6_C6, FN_VI0_D21_R5, FN_VI2_D13_Y5, 0, + /* IP4_14_13 [2] */ + FN_VI4_D5_C5, FN_VI0_D20_R4, FN_VI2_D12_Y4, 0, + /* IP4_12_11 [2] */ + FN_VI4_D4_C4, FN_VI0_D19_R3, FN_VI1_D15_G7_Y7, 0, + /* IP4_10_9 [2] */ + FN_VI4_D3_C3, FN_VI0_D18_R2, FN_VI1_D14_G6_Y6, 0, + /* IP4_8_7 [2] */ + FN_VI4_D2_C2, 0, FN_VI0_D17_R1, FN_VI1_D13_G5_Y5, + /* IP4_6_5 [2] */ + FN_VI4_D1_C1, FN_VI0_D16_R0, FN_VI1_D12_G4_Y4, 0, + /* IP4_4 [1] */ + FN_VI4_D0_C0, FN_VI0_D15_G7_Y7, + /* IP4_3_2 [2] */ + FN_VI4_VSYNC_N, FN_VI0_D14_G6_Y6, 0, 0, + /* IP4_1 [1] */ + FN_VI4_HSYNC_N, FN_VI0_D13_G5_Y5, + /* IP4_0 [1] */ + FN_VI4_CLKENB, FN_VI0_D12_G4_Y4 } + }, + { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060054, 32, + 4, 4, + 4, 4, + 4, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1) { + /* IP5_31_28 [4] */ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* IP5_27_24 [4] */ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* IP5_23_20 [4] */ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* IP5_19_16 [4] */ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* IP5_15_12 [4] */ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* IP5_11 [1] */ + FN_VI5_D8_Y0, FN_VI1_D23_R7, + /* IP5_10 [1] */ + FN_VI5_D7_C7, FN_VI1_D22_R6, + /* IP5_9 [1] */ + FN_VI5_D6_C6, FN_VI1_D21_R5, + /* IP5_8 [1] */ + FN_VI5_D5_C5, FN_VI1_D20_R4, + /* IP5_7 [1] */ + FN_VI5_D4_C4, FN_VI1_D19_R3, + /* IP5_6 [1] */ + FN_VI5_D3_C3, FN_VI1_D18_R2, + /* IP5_5 [1] */ + FN_VI5_D2_C2, FN_VI1_D17_R1, + /* IP5_4 [1] */ + FN_VI5_D1_C1, FN_VI1_D16_R0, + /* IP5_3 [1] */ + FN_VI5_D0_C0, FN_VI1_D15_G7_Y7_B, + /* IP5_2 [1] */ + FN_VI5_VSYNC_N, FN_VI1_D14_G6_Y6_B, + /* IP5_1 [1] */ + FN_VI5_HSYNC_N, FN_VI1_D13_G5_Y5_B, + /* IP5_0 [1] */ + FN_VI5_CLKENB, FN_VI1_D12_G4_Y4_B } + }, + { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060058, 32, + 4, 4, + 4, 1, 2, 1, + 2, 2, 2, 2, + 1, 1, 1, 1, 1, 1, 1, 1) { + /* IP6_31_28 [4] */ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* IP6_27_24 [4] */ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* IP6_23_20 [4] */ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* IP6_19 [1] */ + 0, 0, + /* IP6_18_17 [2] */ + FN_DREQ1_N, FN_RX3, 0, 0, + /* IP6_16 [1] */ + FN_TX3, 0, + /* IP6_15_14 [2] */ + FN_DACK1, FN_SCK3, 0, 0, + /* IP6_13_12 [2] */ + FN_DREQ0_N, FN_RX2, 0, 0, + /* IP6_11_10 [2] */ + FN_DACK0, FN_TX2, 0, 0, + /* IP6_9_8 [2] */ + FN_DRACK0, FN_SCK2, 0, 0, + /* IP6_7 [1] */ + FN_MSIOF1_RXD, FN_HRX1, + /* IP6_6 [1] */ + FN_MSIOF1_TXD, FN_HTX1, + /* IP6_5 [1] */ + FN_MSIOF1_SYNC, FN_HRTS1_N, + /* IP6_4 [1] */ + FN_MSIOF1_SCK, FN_HSCK1, + /* IP6_3 [1] */ + FN_MSIOF0_RXD, FN_HRX0, + /* IP6_2 [1] */ + FN_MSIOF0_TXD, FN_HTX0, + /* IP6_1 [1] */ + FN_MSIOF0_SYNC, FN_HCTS0_N, + /* IP6_0 [1] */ + FN_MSIOF0_SCK, FN_HSCK0 } + }, + { PINMUX_CFG_REG_VAR("IPSR7", 0xE606005C, 32, + 4, 4, + 3, 1, 1, 1, 1, 1, + 2, 2, 2, 2, + 1, 1, 2, 2, 2) { + /* IP7_31_28 [4] */ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* IP7_27_24 [4] */ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* IP7_23_21 [3] */ + 0, 0, 0, 0, 0, 0, 0, 0, + /* IP7_20 [1] */ + FN_AUDIO_CLKB, 0, + /* IP7_19 [1] */ + FN_AUDIO_CLKA, 0, + /* IP7_18 [1] */ + FN_AUDIO_CLKOUT, 0, + /* IP7_17 [1] */ + FN_SSI_SDATA4, 0, + /* IP7_16 [1] */ + FN_SSI_WS4, 0, + /* IP7_15_14 [2] */ + FN_SSI_SCK4, FN_TPU0TO3, 0, 0, + /* IP7_13_12 [2] */ + FN_SSI_SDATA3, FN_TPU0TO2, 0, 0, + /* IP7_11_10 [2] */ + FN_SSI_WS34, FN_TPU0TO1, 0, 0, + /* IP7_9_8 [2] */ + FN_SSI_SCK34, FN_TPU0TO0, 0, 0, + /* IP7_7 [1] */ + FN_PWM4, 0, + /* IP7_6 [1] */ + FN_PWM3, 0, + /* IP7_5_4 [2] */ + FN_PWM2, FN_TCLK3, FN_FSO_TOE, 0, + /* IP7_3_2 [2] */ + FN_PWM1, FN_TCLK2, FN_FSO_CFE_1, 0, + /* IP7_1_0 [2] */ + FN_PWM0, FN_TCLK1, FN_FSO_CFE_0, 0 } + }, + { }, +}; + +const struct sh_pfc_soc_info r8a7792_pinmux_info = { + .name = "r8a77920_pfc", + .unlock_reg = 0xe6060000, /* PMMR */ + + .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, + + .pins = pinmux_pins, + .nr_pins = ARRAY_SIZE(pinmux_pins), + .groups = pinmux_groups, + .nr_groups = ARRAY_SIZE(pinmux_groups), + .functions = pinmux_functions, + .nr_functions = ARRAY_SIZE(pinmux_functions), + + .cfg_regs = pinmux_config_regs, + + .pinmux_data = pinmux_data, + .pinmux_data_size = ARRAY_SIZE(pinmux_data), +}; diff --git a/drivers/pinctrl/sh-pfc/sh_pfc.h b/drivers/pinctrl/sh-pfc/sh_pfc.h index 11f18be532b8..ed12886d5bd5 100644 --- a/drivers/pinctrl/sh-pfc/sh_pfc.h +++ b/drivers/pinctrl/sh-pfc/sh_pfc.h @@ -257,6 +257,7 @@ extern const struct sh_pfc_soc_info r8a7778_pinmux_info; extern const struct sh_pfc_soc_info r8a7779_pinmux_info; extern const struct sh_pfc_soc_info r8a7790_pinmux_info; extern const struct sh_pfc_soc_info r8a7791_pinmux_info; +extern const struct sh_pfc_soc_info r8a7792_pinmux_info; extern const struct sh_pfc_soc_info r8a7793_pinmux_info; extern const struct sh_pfc_soc_info r8a7794_pinmux_info; extern const struct sh_pfc_soc_info r8a7795_pinmux_info; @@ -401,19 +402,27 @@ extern const struct sh_pfc_soc_info shx3_pinmux_info; PORT_GP_CFG_1(bank, 15, fn, sfx, cfg) #define PORT_GP_16(bank, fn, sfx) PORT_GP_CFG_16(bank, fn, sfx, 0) -#define PORT_GP_CFG_18(bank, fn, sfx, cfg) \ +#define PORT_GP_CFG_17(bank, fn, sfx, cfg) \ PORT_GP_CFG_16(bank, fn, sfx, cfg), \ - PORT_GP_CFG_1(bank, 16, fn, sfx, cfg), \ + PORT_GP_CFG_1(bank, 16, fn, sfx, cfg) +#define PORT_GP_17(bank, fn, sfx) PORT_GP_CFG_17(bank, fn, sfx, 0) + +#define PORT_GP_CFG_18(bank, fn, sfx, cfg) \ + PORT_GP_CFG_17(bank, fn, sfx, cfg), \ PORT_GP_CFG_1(bank, 17, fn, sfx, cfg) #define PORT_GP_18(bank, fn, sfx) PORT_GP_CFG_18(bank, fn, sfx, 0) -#define PORT_GP_CFG_26(bank, fn, sfx, cfg) \ +#define PORT_GP_CFG_23(bank, fn, sfx, cfg) \ PORT_GP_CFG_18(bank, fn, sfx, cfg), \ PORT_GP_CFG_1(bank, 18, fn, sfx, cfg), \ PORT_GP_CFG_1(bank, 19, fn, sfx, cfg), \ PORT_GP_CFG_1(bank, 20, fn, sfx, cfg), \ PORT_GP_CFG_1(bank, 21, fn, sfx, cfg), \ - PORT_GP_CFG_1(bank, 22, fn, sfx, cfg), \ + PORT_GP_CFG_1(bank, 22, fn, sfx, cfg) +#define PORT_GP_23(bank, fn, sfx) PORT_GP_CFG_23(bank, fn, sfx, 0) + +#define PORT_GP_CFG_26(bank, fn, sfx, cfg) \ + PORT_GP_CFG_23(bank, fn, sfx, cfg), \ PORT_GP_CFG_1(bank, 23, fn, sfx, cfg), \ PORT_GP_CFG_1(bank, 24, fn, sfx, cfg), \ PORT_GP_CFG_1(bank, 25, fn, sfx, cfg) @@ -425,9 +434,13 @@ extern const struct sh_pfc_soc_info shx3_pinmux_info; PORT_GP_CFG_1(bank, 27, fn, sfx, cfg) #define PORT_GP_28(bank, fn, sfx) PORT_GP_CFG_28(bank, fn, sfx, 0) -#define PORT_GP_CFG_30(bank, fn, sfx, cfg) \ +#define PORT_GP_CFG_29(bank, fn, sfx, cfg) \ PORT_GP_CFG_28(bank, fn, sfx, cfg), \ - PORT_GP_CFG_1(bank, 28, fn, sfx, cfg), \ + PORT_GP_CFG_1(bank, 28, fn, sfx, cfg) +#define PORT_GP_29(bank, fn, sfx) PORT_GP_CFG_29(bank, fn, sfx, 0) + +#define PORT_GP_CFG_30(bank, fn, sfx, cfg) \ + PORT_GP_CFG_29(bank, fn, sfx, cfg), \ PORT_GP_CFG_1(bank, 29, fn, sfx, cfg) #define PORT_GP_30(bank, fn, sfx) PORT_GP_CFG_30(bank, fn, sfx, 0) -- cgit 1.4.1 From 2e67216c8ca63b7e5c06f0e6cf9af570f7e56b6b Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Wed, 13 Jul 2016 00:38:44 +0300 Subject: pinctrl: sh-pfc: r8a7792: Add EtherAVB pin groups Add the EtherAVB pin groups to the R8A7792 PFC driver. Signed-off-by: Sergei Shtylyov Signed-off-by: Geert Uytterhoeven --- drivers/pinctrl/sh-pfc/pfc-r8a7792.c | 99 ++++++++++++++++++++++++++++++++++++ 1 file changed, 99 insertions(+) diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7792.c b/drivers/pinctrl/sh-pfc/pfc-r8a7792.c index b902e3ec221e..d51695d0d05f 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7792.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7792.c @@ -731,6 +731,87 @@ static const struct sh_pfc_pin pinmux_pins[] = { PINMUX_GPIO_GP_ALL(), }; +/* - AVB -------------------------------------------------------------------- */ +static const unsigned int avb_link_pins[] = { + RCAR_GP_PIN(7, 9), +}; +static const unsigned int avb_link_mux[] = { + AVB_LINK_MARK, +}; +static const unsigned int avb_magic_pins[] = { + RCAR_GP_PIN(7, 10), +}; +static const unsigned int avb_magic_mux[] = { + AVB_MAGIC_MARK, +}; +static const unsigned int avb_phy_int_pins[] = { + RCAR_GP_PIN(7, 11), +}; +static const unsigned int avb_phy_int_mux[] = { + AVB_PHY_INT_MARK, +}; +static const unsigned int avb_mdio_pins[] = { + RCAR_GP_PIN(7, 7), RCAR_GP_PIN(7, 8), +}; +static const unsigned int avb_mdio_mux[] = { + AVB_MDC_MARK, AVB_MDIO_MARK, +}; +static const unsigned int avb_mii_pins[] = { + RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15), RCAR_GP_PIN(6, 16), + RCAR_GP_PIN(6, 12), + + RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 3), RCAR_GP_PIN(6, 4), + RCAR_GP_PIN(6, 5), + + RCAR_GP_PIN(6, 10), RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1), + RCAR_GP_PIN(7, 12), RCAR_GP_PIN(6, 13), RCAR_GP_PIN(7, 5), + RCAR_GP_PIN(7, 0), RCAR_GP_PIN(6, 11), +}; +static const unsigned int avb_mii_mux[] = { + AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK, + AVB_TXD3_MARK, + + AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK, + AVB_RXD3_MARK, + + AVB_RX_ER_MARK, AVB_RX_CLK_MARK, AVB_RX_DV_MARK, + AVB_CRS_MARK, AVB_TX_EN_MARK, AVB_TX_ER_MARK, + AVB_TX_CLK_MARK, AVB_COL_MARK, +}; +static const unsigned int avb_gmii_pins[] = { + RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15), RCAR_GP_PIN(6, 16), + RCAR_GP_PIN(6, 12), RCAR_GP_PIN(7, 1), RCAR_GP_PIN(7, 2), + RCAR_GP_PIN(7, 3), RCAR_GP_PIN(7, 4), + + RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 3), RCAR_GP_PIN(6, 4), + RCAR_GP_PIN(6, 5), RCAR_GP_PIN(6, 6), RCAR_GP_PIN(6, 7), + RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9), + + RCAR_GP_PIN(6, 10), RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1), + RCAR_GP_PIN(7, 12), RCAR_GP_PIN(7, 6), RCAR_GP_PIN(7, 13), + RCAR_GP_PIN(6, 13), RCAR_GP_PIN(7, 5), RCAR_GP_PIN(7, 0), + RCAR_GP_PIN(6, 11), +}; +static const unsigned int avb_gmii_mux[] = { + AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK, + AVB_TXD3_MARK, AVB_TXD4_MARK, AVB_TXD5_MARK, + AVB_TXD6_MARK, AVB_TXD7_MARK, + + AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK, + AVB_RXD3_MARK, AVB_RXD4_MARK, AVB_RXD5_MARK, + AVB_RXD6_MARK, AVB_RXD7_MARK, + + AVB_RX_ER_MARK, AVB_RX_CLK_MARK, AVB_RX_DV_MARK, + AVB_CRS_MARK, AVB_GTX_CLK_MARK, AVB_GTXREFCLK_MARK, + AVB_TX_EN_MARK, AVB_TX_ER_MARK, AVB_TX_CLK_MARK, + AVB_COL_MARK, +}; +static const unsigned int avb_avtp_match_pins[] = { + RCAR_GP_PIN(7, 15), +}; +static const unsigned int avb_avtp_match_mux[] = { + AVB_AVTP_MATCH_MARK, +}; /* - INTC ------------------------------------------------------------------- */ static const unsigned int intc_irq0_pins[] = { /* IRQ0 */ @@ -856,6 +937,13 @@ static const unsigned int scif3_clk_mux[] = { }; static const struct sh_pfc_pin_group pinmux_groups[] = { + SH_PFC_PIN_GROUP(avb_link), + SH_PFC_PIN_GROUP(avb_magic), + SH_PFC_PIN_GROUP(avb_phy_int), + SH_PFC_PIN_GROUP(avb_mdio), + SH_PFC_PIN_GROUP(avb_mii), + SH_PFC_PIN_GROUP(avb_gmii), + SH_PFC_PIN_GROUP(avb_avtp_match), SH_PFC_PIN_GROUP(intc_irq0), SH_PFC_PIN_GROUP(intc_irq1), SH_PFC_PIN_GROUP(intc_irq2), @@ -875,6 +963,16 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(scif3_clk), }; +static const char * const avb_groups[] = { + "avb_link", + "avb_magic", + "avb_phy_int", + "avb_mdio", + "avb_mii", + "avb_gmii", + "avb_avtp_match", +}; + static const char * const intc_groups[] = { "intc_irq0", "intc_irq1", @@ -905,6 +1003,7 @@ static const char * const scif3_groups[] = { }; static const struct sh_pfc_function pinmux_functions[] = { + SH_PFC_FUNCTION(avb), SH_PFC_FUNCTION(intc), SH_PFC_FUNCTION(lbsc), SH_PFC_FUNCTION(scif0), -- cgit 1.4.1 From 1373eeeb3ed8651f44affea143dfc523bbcdc7e4 Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Wed, 13 Jul 2016 00:40:03 +0300 Subject: pinctrl: sh-pfc: r8a7792: Add SDHI pin groups Add SDHI0 pin groups to the R8A7792 PFC driver. Signed-off-by: Sergei Shtylyov Acked-by: Linus Walleij Signed-off-by: Geert Uytterhoeven --- drivers/pinctrl/sh-pfc/pfc-r8a7792.c | 51 ++++++++++++++++++++++++++++++++++++ 1 file changed, 51 insertions(+) diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7792.c b/drivers/pinctrl/sh-pfc/pfc-r8a7792.c index d51695d0d05f..4e52323ac783 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7792.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7792.c @@ -935,6 +935,43 @@ static const unsigned int scif3_clk_pins[] = { static const unsigned int scif3_clk_mux[] = { SCK3_MARK, }; +/* - SDHI0 ------------------------------------------------------------------ */ +static const unsigned int sdhi0_data1_pins[] = { + /* DAT0 */ + RCAR_GP_PIN(11, 7), +}; +static const unsigned int sdhi0_data1_mux[] = { + SD0_DAT0_MARK, +}; +static const unsigned int sdhi0_data4_pins[] = { + /* DAT[0-3] */ + RCAR_GP_PIN(11, 7), RCAR_GP_PIN(11, 8), + RCAR_GP_PIN(11, 9), RCAR_GP_PIN(11, 10), +}; +static const unsigned int sdhi0_data4_mux[] = { + SD0_DAT0_MARK, SD0_DAT1_MARK, SD0_DAT2_MARK, SD0_DAT3_MARK, +}; +static const unsigned int sdhi0_ctrl_pins[] = { + /* CLK, CMD */ + RCAR_GP_PIN(11, 5), RCAR_GP_PIN(11, 6), +}; +static const unsigned int sdhi0_ctrl_mux[] = { + SD0_CLK_MARK, SD0_CMD_MARK, +}; +static const unsigned int sdhi0_cd_pins[] = { + /* CD */ + RCAR_GP_PIN(11, 11), +}; +static const unsigned int sdhi0_cd_mux[] = { + SD0_CD_MARK, +}; +static const unsigned int sdhi0_wp_pins[] = { + /* WP */ + RCAR_GP_PIN(11, 12), +}; +static const unsigned int sdhi0_wp_mux[] = { + SD0_WP_MARK, +}; static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(avb_link), @@ -961,6 +998,11 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(scif0_ctrl), SH_PFC_PIN_GROUP(scif3_data), SH_PFC_PIN_GROUP(scif3_clk), + SH_PFC_PIN_GROUP(sdhi0_data1), + SH_PFC_PIN_GROUP(sdhi0_data4), + SH_PFC_PIN_GROUP(sdhi0_ctrl), + SH_PFC_PIN_GROUP(sdhi0_cd), + SH_PFC_PIN_GROUP(sdhi0_wp), }; static const char * const avb_groups[] = { @@ -1002,12 +1044,21 @@ static const char * const scif3_groups[] = { "scif3_clk", }; +static const char * const sdhi0_groups[] = { + "sdhi0_data1", + "sdhi0_data4", + "sdhi0_ctrl", + "sdhi0_cd", + "sdhi0_wp", +}; + static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(avb), SH_PFC_FUNCTION(intc), SH_PFC_FUNCTION(lbsc), SH_PFC_FUNCTION(scif0), SH_PFC_FUNCTION(scif3), + SH_PFC_FUNCTION(sdhi0), }; static const struct pinmux_cfg_reg pinmux_config_regs[] = { -- cgit 1.4.1 From 37d0d275bd36db1eae1fb2b08762ae6f95066d78 Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Thu, 14 Jul 2016 22:51:40 +0300 Subject: pinctrl: sh-pfc: r8a7792: Add CAN pin groups Add CAN0/1 data/clock pin groups to R8A7792 PFC driver. Signed-off-by: Sergei Shtylyov Signed-off-by: Geert Uytterhoeven --- drivers/pinctrl/sh-pfc/pfc-r8a7792.c | 37 ++++++++++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7792.c b/drivers/pinctrl/sh-pfc/pfc-r8a7792.c index 4e52323ac783..791f98d32d85 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7792.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7792.c @@ -812,6 +812,28 @@ static const unsigned int avb_avtp_match_pins[] = { static const unsigned int avb_avtp_match_mux[] = { AVB_AVTP_MATCH_MARK, }; +/* - CAN -------------------------------------------------------------------- */ +static const unsigned int can0_data_pins[] = { + /* TX, RX */ + RCAR_GP_PIN(10, 27), RCAR_GP_PIN(10, 28), +}; +static const unsigned int can0_data_mux[] = { + CAN0_TX_MARK, CAN0_RX_MARK, +}; +static const unsigned int can1_data_pins[] = { + /* TX, RX */ + RCAR_GP_PIN(10, 30), RCAR_GP_PIN(10, 31), +}; +static const unsigned int can1_data_mux[] = { + CAN1_TX_MARK, CAN1_RX_MARK, +}; +static const unsigned int can_clk_pins[] = { + /* CAN_CLK */ + RCAR_GP_PIN(10, 29), +}; +static const unsigned int can_clk_mux[] = { + CAN_CLK_MARK, +}; /* - INTC ------------------------------------------------------------------- */ static const unsigned int intc_irq0_pins[] = { /* IRQ0 */ @@ -981,6 +1003,9 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(avb_mii), SH_PFC_PIN_GROUP(avb_gmii), SH_PFC_PIN_GROUP(avb_avtp_match), + SH_PFC_PIN_GROUP(can0_data), + SH_PFC_PIN_GROUP(can1_data), + SH_PFC_PIN_GROUP(can_clk), SH_PFC_PIN_GROUP(intc_irq0), SH_PFC_PIN_GROUP(intc_irq1), SH_PFC_PIN_GROUP(intc_irq2), @@ -1015,6 +1040,16 @@ static const char * const avb_groups[] = { "avb_avtp_match", }; +static const char * const can0_groups[] = { + "can0_data", + "can_clk", +}; + +static const char * const can1_groups[] = { + "can1_data", + "can_clk", +}; + static const char * const intc_groups[] = { "intc_irq0", "intc_irq1", @@ -1054,6 +1089,8 @@ static const char * const sdhi0_groups[] = { static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(avb), + SH_PFC_FUNCTION(can0), + SH_PFC_FUNCTION(can1), SH_PFC_FUNCTION(intc), SH_PFC_FUNCTION(lbsc), SH_PFC_FUNCTION(scif0), -- cgit 1.4.1 From adc9ad09f722dd033be24bf8f3818c5d4b38315b Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 28 Jun 2016 16:12:41 +0200 Subject: pinctrl: sh-pfc: r8a7795: Correct header from R-Car Gen3 to R8A7795 This source file handles r8a7795 only, which is not the sole member of the R-Car Gen3 family. Signed-off-by: Geert Uytterhoeven Acked-by: Linus Walleij --- drivers/pinctrl/sh-pfc/pfc-r8a7795.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c index 0f1a111447c3..1b35ad9b538d 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c @@ -1,5 +1,5 @@ /* - * R-Car Gen3 processor support - PFC hardware block. + * R8A7795 processor support - PFC hardware block. * * Copyright (C) 2015 Renesas Electronics Corporation * -- cgit 1.4.1 From 7dd74bb1f058786e85922b595cde2972be436365 Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Fri, 5 Aug 2016 23:52:32 +0300 Subject: pinctrl: sh-pfc: r8a7792: Add VIN pin groups Add VIN[0-5] pin groups to the R8A7792 PFC driver. Signed-off-by: Sergei Shtylyov [geert: Fix VI1_D14_G6_Y6 and VI1_D15_G7_Y7 pins] Signed-off-by: Geert Uytterhoeven --- drivers/pinctrl/sh-pfc/pfc-r8a7792.c | 577 +++++++++++++++++++++++++++++++++++ 1 file changed, 577 insertions(+) diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7792.c b/drivers/pinctrl/sh-pfc/pfc-r8a7792.c index 791f98d32d85..a0fc276b29aa 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7792.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7792.c @@ -994,6 +994,448 @@ static const unsigned int sdhi0_wp_pins[] = { static const unsigned int sdhi0_wp_mux[] = { SD0_WP_MARK, }; +/* - VIN0 ------------------------------------------------------------------- */ +static const union vin_data vin0_data_pins = { + .data24 = { + /* B */ + RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5), + RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 7), + RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9), + RCAR_GP_PIN(4, 10), RCAR_GP_PIN(4, 11), + /* G */ + RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 13), + RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 15), + RCAR_GP_PIN(8, 1), RCAR_GP_PIN(8, 2), + RCAR_GP_PIN(8, 3), RCAR_GP_PIN(8, 4), + /* R */ + RCAR_GP_PIN(8, 5), RCAR_GP_PIN(8, 6), + RCAR_GP_PIN(8, 7), RCAR_GP_PIN(8, 8), + RCAR_GP_PIN(8, 9), RCAR_GP_PIN(8, 10), + RCAR_GP_PIN(8, 11), RCAR_GP_PIN(8, 12), + }, +}; +static const union vin_data vin0_data_mux = { + .data24 = { + /* B */ + VI0_D0_B0_C0_MARK, VI0_D1_B1_C1_MARK, + VI0_D2_B2_C2_MARK, VI0_D3_B3_C3_MARK, + VI0_D4_B4_C4_MARK, VI0_D5_B5_C5_MARK, + VI0_D6_B6_C6_MARK, VI0_D7_B7_C7_MARK, + /* G */ + VI0_D8_G0_Y0_MARK, VI0_D9_G1_Y1_MARK, + VI0_D10_G2_Y2_MARK, VI0_D11_G3_Y3_MARK, + VI0_D12_G4_Y4_MARK, VI0_D13_G5_Y5_MARK, + VI0_D14_G6_Y6_MARK, VI0_D15_G7_Y7_MARK, + /* R */ + VI0_D16_R0_MARK, VI0_D17_R1_MARK, + VI0_D18_R2_MARK, VI0_D19_R3_MARK, + VI0_D20_R4_MARK, VI0_D21_R5_MARK, + VI0_D22_R6_MARK, VI0_D23_R7_MARK, + }, +}; +static const unsigned int vin0_data18_pins[] = { + /* B */ + RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 7), + RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9), + RCAR_GP_PIN(4, 10), RCAR_GP_PIN(4, 11), + /* G */ + RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 15), + RCAR_GP_PIN(8, 1), RCAR_GP_PIN(8, 2), + RCAR_GP_PIN(8, 3), RCAR_GP_PIN(8, 4), + /* R */ + RCAR_GP_PIN(8, 7), RCAR_GP_PIN(8, 8), + RCAR_GP_PIN(8, 9), RCAR_GP_PIN(8, 10), + RCAR_GP_PIN(8, 11), RCAR_GP_PIN(8, 12), +}; +static const unsigned int vin0_data18_mux[] = { + /* B */ + VI0_D2_B2_C2_MARK, VI0_D3_B3_C3_MARK, + VI0_D4_B4_C4_MARK, VI0_D5_B5_C5_MARK, + VI0_D6_B6_C6_MARK, VI0_D7_B7_C7_MARK, + /* G */ + VI0_D10_G2_Y2_MARK, VI0_D11_G3_Y3_MARK, + VI0_D12_G4_Y4_MARK, VI0_D13_G5_Y5_MARK, + VI0_D14_G6_Y6_MARK, VI0_D15_G7_Y7_MARK, + /* R */ + VI0_D18_R2_MARK, VI0_D19_R3_MARK, + VI0_D20_R4_MARK, VI0_D21_R5_MARK, + VI0_D22_R6_MARK, VI0_D23_R7_MARK, +}; +static const unsigned int vin0_sync_pins[] = { + /* HSYNC#, VSYNC# */ + RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3), +}; +static const unsigned int vin0_sync_mux[] = { + VI0_HSYNC_N_MARK, VI0_VSYNC_N_MARK, +}; +static const unsigned int vin0_field_pins[] = { + RCAR_GP_PIN(4, 16), +}; +static const unsigned int vin0_field_mux[] = { + VI0_FIELD_MARK, +}; +static const unsigned int vin0_clkenb_pins[] = { + RCAR_GP_PIN(4, 1), +}; +static const unsigned int vin0_clkenb_mux[] = { + VI0_CLKENB_MARK, +}; +static const unsigned int vin0_clk_pins[] = { + RCAR_GP_PIN(4, 0), +}; +static const unsigned int vin0_clk_mux[] = { + VI0_CLK_MARK, +}; +/* - VIN1 ------------------------------------------------------------------- */ +static const union vin_data vin1_data_pins = { + .data24 = { + /* B */ + RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 5), + RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 7), + RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9), + RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 11), + /* G */ + RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 13), + RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15), + RCAR_GP_PIN(8, 5), RCAR_GP_PIN(8, 6), + RCAR_GP_PIN(8, 7), RCAR_GP_PIN(8, 8), + /* R */ + RCAR_GP_PIN(9, 5), RCAR_GP_PIN(9, 6), + RCAR_GP_PIN(9, 7), RCAR_GP_PIN(9, 8), + RCAR_GP_PIN(9, 9), RCAR_GP_PIN(9, 10), + RCAR_GP_PIN(9, 11), RCAR_GP_PIN(9, 12), + }, +}; +static const union vin_data vin1_data_mux = { + .data24 = { + /* B */ + VI1_D0_B0_C0_MARK, VI1_D1_B1_C1_MARK, + VI1_D2_B2_C2_MARK, VI1_D3_B3_C3_MARK, + VI1_D4_B4_C4_MARK, VI1_D5_B5_C5_MARK, + VI1_D6_B6_C6_MARK, VI1_D7_B7_C7_MARK, + /* G */ + VI1_D8_G0_Y0_MARK, VI1_D9_G1_Y1_MARK, + VI1_D10_G2_Y2_MARK, VI1_D11_G3_Y3_MARK, + VI1_D12_G4_Y4_MARK, VI1_D13_G5_Y5_MARK, + VI1_D14_G6_Y6_MARK, VI1_D15_G7_Y7_MARK, + /* R */ + VI1_D16_R0_MARK, VI1_D17_R1_MARK, + VI1_D18_R2_MARK, VI1_D19_R3_MARK, + VI1_D20_R4_MARK, VI1_D21_R5_MARK, + VI1_D22_R6_MARK, VI1_D23_R7_MARK, + }, +}; +static const unsigned int vin1_data18_pins[] = { + /* B */ + RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 7), + RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9), + RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 11), + /* G */ + RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15), + RCAR_GP_PIN(8, 5), RCAR_GP_PIN(8, 6), + RCAR_GP_PIN(8, 7), RCAR_GP_PIN(8, 8), + /* R */ + RCAR_GP_PIN(9, 7), RCAR_GP_PIN(9, 8), + RCAR_GP_PIN(9, 9), RCAR_GP_PIN(9, 10), + RCAR_GP_PIN(9, 11), RCAR_GP_PIN(9, 12), +}; +static const unsigned int vin1_data18_mux[] = { + /* B */ + VI1_D2_B2_C2_MARK, VI1_D3_B3_C3_MARK, + VI1_D4_B4_C4_MARK, VI1_D5_B5_C5_MARK, + VI1_D6_B6_C6_MARK, VI1_D7_B7_C7_MARK, + /* G */ + VI1_D10_G2_Y2_MARK, VI1_D11_G3_Y3_MARK, + VI1_D12_G4_Y4_MARK, VI1_D13_G5_Y5_MARK, + VI1_D14_G6_Y6_MARK, VI1_D15_G7_Y7_MARK, + /* R */ + VI1_D18_R2_MARK, VI1_D19_R3_MARK, + VI1_D20_R4_MARK, VI1_D21_R5_MARK, + VI1_D22_R6_MARK, VI1_D23_R7_MARK, +}; +static const union vin_data vin1_data_b_pins = { + .data24 = { + /* B */ + RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 5), + RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 7), + RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9), + RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 11), + /* G */ + RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 13), + RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15), + RCAR_GP_PIN(9, 1), RCAR_GP_PIN(9, 2), + RCAR_GP_PIN(9, 3), RCAR_GP_PIN(9, 4), + /* R */ + RCAR_GP_PIN(9, 5), RCAR_GP_PIN(9, 6), + RCAR_GP_PIN(9, 7), RCAR_GP_PIN(9, 8), + RCAR_GP_PIN(9, 9), RCAR_GP_PIN(9, 10), + RCAR_GP_PIN(9, 11), RCAR_GP_PIN(9, 12), + }, +}; +static const union vin_data vin1_data_b_mux = { + .data24 = { + /* B */ + VI1_D0_B0_C0_MARK, VI1_D1_B1_C1_MARK, + VI1_D2_B2_C2_MARK, VI1_D3_B3_C3_MARK, + VI1_D4_B4_C4_MARK, VI1_D5_B5_C5_MARK, + VI1_D6_B6_C6_MARK, VI1_D7_B7_C7_MARK, + /* G */ + VI1_D8_G0_Y0_MARK, VI1_D9_G1_Y1_MARK, + VI1_D10_G2_Y2_MARK, VI1_D11_G3_Y3_MARK, + VI1_D12_G4_Y4_B_MARK, VI1_D13_G5_Y5_B_MARK, + VI1_D14_G6_Y6_B_MARK, VI1_D15_G7_Y7_B_MARK, + /* R */ + VI1_D16_R0_MARK, VI1_D17_R1_MARK, + VI1_D18_R2_MARK, VI1_D19_R3_MARK, + VI1_D20_R4_MARK, VI1_D21_R5_MARK, + VI1_D22_R6_MARK, VI1_D23_R7_MARK, + }, +}; +static const unsigned int vin1_data18_b_pins[] = { + /* B */ + RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 7), + RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9), + RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 11), + /* G */ + RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15), + RCAR_GP_PIN(9, 1), RCAR_GP_PIN(9, 2), + RCAR_GP_PIN(9, 3), RCAR_GP_PIN(9, 4), + /* R */ + RCAR_GP_PIN(9, 7), RCAR_GP_PIN(9, 8), + RCAR_GP_PIN(9, 9), RCAR_GP_PIN(9, 10), + RCAR_GP_PIN(9, 11), RCAR_GP_PIN(9, 12), +}; +static const unsigned int vin1_data18_b_mux[] = { + /* B */ + VI1_D2_B2_C2_MARK, VI1_D3_B3_C3_MARK, + VI1_D4_B4_C4_MARK, VI1_D5_B5_C5_MARK, + VI1_D6_B6_C6_MARK, VI1_D7_B7_C7_MARK, + /* G */ + VI1_D10_G2_Y2_MARK, VI1_D11_G3_Y3_MARK, + VI1_D12_G4_Y4_B_MARK, VI1_D13_G5_Y5_B_MARK, + VI1_D14_G6_Y6_B_MARK, VI1_D15_G7_Y7_B_MARK, + /* R */ + VI1_D18_R2_MARK, VI1_D19_R3_MARK, + VI1_D20_R4_MARK, VI1_D21_R5_MARK, + VI1_D22_R6_MARK, VI1_D23_R7_MARK, +}; +static const unsigned int vin1_sync_pins[] = { + /* HSYNC#, VSYNC# */ + RCAR_GP_PIN(5, 2), RCAR_GP_PIN(5, 3), +}; +static const unsigned int vin1_sync_mux[] = { + VI1_HSYNC_N_MARK, VI1_VSYNC_N_MARK, +}; +static const unsigned int vin1_field_pins[] = { + RCAR_GP_PIN(5, 16), +}; +static const unsigned int vin1_field_mux[] = { + VI1_FIELD_MARK, +}; +static const unsigned int vin1_clkenb_pins[] = { + RCAR_GP_PIN(5, 1), +}; +static const unsigned int vin1_clkenb_mux[] = { + VI1_CLKENB_MARK, +}; +static const unsigned int vin1_clk_pins[] = { + RCAR_GP_PIN(5, 0), +}; +static const unsigned int vin1_clk_mux[] = { + VI1_CLK_MARK, +}; +/* - VIN2 ------------------------------------------------------------------- */ +static const union vin_data vin2_data_pins = { + .data16 = { + RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 5), + RCAR_GP_PIN(6, 6), RCAR_GP_PIN(6, 7), + RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9), + RCAR_GP_PIN(6, 10), RCAR_GP_PIN(6, 11), + RCAR_GP_PIN(6, 12), RCAR_GP_PIN(6, 13), + RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15), + RCAR_GP_PIN(8, 9), RCAR_GP_PIN(8, 10), + RCAR_GP_PIN(8, 11), RCAR_GP_PIN(8, 12), + }, +}; +static const union vin_data vin2_data_mux = { + .data16 = { + VI2_D0_C0_MARK, VI2_D1_C1_MARK, + VI2_D2_C2_MARK, VI2_D3_C3_MARK, + VI2_D4_C4_MARK, VI2_D5_C5_MARK, + VI2_D6_C6_MARK, VI2_D7_C7_MARK, + VI2_D8_Y0_MARK, VI2_D9_Y1_MARK, + VI2_D10_Y2_MARK, VI2_D11_Y3_MARK, + VI2_D12_Y4_MARK, VI2_D13_Y5_MARK, + VI2_D14_Y6_MARK, VI2_D15_Y7_MARK, + }, +}; +static const unsigned int vin2_sync_pins[] = { + /* HSYNC#, VSYNC# */ + RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 3), +}; +static const unsigned int vin2_sync_mux[] = { + VI2_HSYNC_N_MARK, VI2_VSYNC_N_MARK, +}; +static const unsigned int vin2_field_pins[] = { + RCAR_GP_PIN(6, 16), +}; +static const unsigned int vin2_field_mux[] = { + VI2_FIELD_MARK, +}; +static const unsigned int vin2_clkenb_pins[] = { + RCAR_GP_PIN(6, 1), +}; +static const unsigned int vin2_clkenb_mux[] = { + VI2_CLKENB_MARK, +}; +static const unsigned int vin2_clk_pins[] = { + RCAR_GP_PIN(6, 0), +}; +static const unsigned int vin2_clk_mux[] = { + VI2_CLK_MARK, +}; +/* - VIN3 ------------------------------------------------------------------- */ +static const union vin_data vin3_data_pins = { + .data16 = { + RCAR_GP_PIN(7, 4), RCAR_GP_PIN(7, 5), + RCAR_GP_PIN(7, 6), RCAR_GP_PIN(7, 7), + RCAR_GP_PIN(7, 8), RCAR_GP_PIN(7, 9), + RCAR_GP_PIN(7, 10), RCAR_GP_PIN(7, 11), + RCAR_GP_PIN(7, 12), RCAR_GP_PIN(7, 13), + RCAR_GP_PIN(7, 14), RCAR_GP_PIN(7, 15), + RCAR_GP_PIN(8, 13), RCAR_GP_PIN(8, 14), + RCAR_GP_PIN(8, 15), RCAR_GP_PIN(8, 16), + }, +}; +static const union vin_data vin3_data_mux = { + .data16 = { + VI3_D0_C0_MARK, VI3_D1_C1_MARK, + VI3_D2_C2_MARK, VI3_D3_C3_MARK, + VI3_D4_C4_MARK, VI3_D5_C5_MARK, + VI3_D6_C6_MARK, VI3_D7_C7_MARK, + VI3_D8_Y0_MARK, VI3_D9_Y1_MARK, + VI3_D10_Y2_MARK, VI3_D11_Y3_MARK, + VI3_D12_Y4_MARK, VI3_D13_Y5_MARK, + VI3_D14_Y6_MARK, VI3_D15_Y7_MARK, + }, +}; +static const unsigned int vin3_sync_pins[] = { + /* HSYNC#, VSYNC# */ + RCAR_GP_PIN(7, 2), RCAR_GP_PIN(7, 3), +}; +static const unsigned int vin3_sync_mux[] = { + VI3_HSYNC_N_MARK, VI3_VSYNC_N_MARK, +}; +static const unsigned int vin3_field_pins[] = { + RCAR_GP_PIN(7, 16), +}; +static const unsigned int vin3_field_mux[] = { + VI3_FIELD_MARK, +}; +static const unsigned int vin3_clkenb_pins[] = { + RCAR_GP_PIN(7, 1), +}; +static const unsigned int vin3_clkenb_mux[] = { + VI3_CLKENB_MARK, +}; +static const unsigned int vin3_clk_pins[] = { + RCAR_GP_PIN(7, 0), +}; +static const unsigned int vin3_clk_mux[] = { + VI3_CLK_MARK, +}; +/* - VIN4 ------------------------------------------------------------------- */ +static const union vin_data vin4_data_pins = { + .data12 = { + RCAR_GP_PIN(8, 4), RCAR_GP_PIN(8, 5), + RCAR_GP_PIN(8, 6), RCAR_GP_PIN(8, 7), + RCAR_GP_PIN(8, 8), RCAR_GP_PIN(8, 9), + RCAR_GP_PIN(8, 10), RCAR_GP_PIN(8, 11), + RCAR_GP_PIN(8, 12), RCAR_GP_PIN(8, 13), + RCAR_GP_PIN(8, 14), RCAR_GP_PIN(8, 15), + }, +}; +static const union vin_data vin4_data_mux = { + .data12 = { + VI4_D0_C0_MARK, VI4_D1_C1_MARK, + VI4_D2_C2_MARK, VI4_D3_C3_MARK, + VI4_D4_C4_MARK, VI4_D5_C5_MARK, + VI4_D6_C6_MARK, VI4_D7_C7_MARK, + VI4_D8_Y0_MARK, VI4_D9_Y1_MARK, + VI4_D10_Y2_MARK, VI4_D11_Y3_MARK, + }, +}; +static const unsigned int vin4_sync_pins[] = { + /* HSYNC#, VSYNC# */ + RCAR_GP_PIN(8, 2), RCAR_GP_PIN(8, 3), +}; +static const unsigned int vin4_sync_mux[] = { + VI4_HSYNC_N_MARK, VI4_VSYNC_N_MARK, +}; +static const unsigned int vin4_field_pins[] = { + RCAR_GP_PIN(8, 16), +}; +static const unsigned int vin4_field_mux[] = { + VI4_FIELD_MARK, +}; +static const unsigned int vin4_clkenb_pins[] = { + RCAR_GP_PIN(8, 1), +}; +static const unsigned int vin4_clkenb_mux[] = { + VI4_CLKENB_MARK, +}; +static const unsigned int vin4_clk_pins[] = { + RCAR_GP_PIN(8, 0), +}; +static const unsigned int vin4_clk_mux[] = { + VI4_CLK_MARK, +}; +/* - VIN5 ------------------------------------------------------------------- */ +static const union vin_data vin5_data_pins = { + .data12 = { + RCAR_GP_PIN(9, 4), RCAR_GP_PIN(9, 5), + RCAR_GP_PIN(9, 6), RCAR_GP_PIN(9, 7), + RCAR_GP_PIN(9, 8), RCAR_GP_PIN(9, 9), + RCAR_GP_PIN(9, 10), RCAR_GP_PIN(9, 11), + RCAR_GP_PIN(9, 12), RCAR_GP_PIN(9, 13), + RCAR_GP_PIN(9, 14), RCAR_GP_PIN(9, 15), + }, +}; +static const union vin_data vin5_data_mux = { + .data12 = { + VI5_D0_C0_MARK, VI5_D1_C1_MARK, + VI5_D2_C2_MARK, VI5_D3_C3_MARK, + VI5_D4_C4_MARK, VI5_D5_C5_MARK, + VI5_D6_C6_MARK, VI5_D7_C7_MARK, + VI5_D8_Y0_MARK, VI5_D9_Y1_MARK, + VI5_D10_Y2_MARK, VI5_D11_Y3_MARK, + }, +}; +static const unsigned int vin5_sync_pins[] = { + /* HSYNC#, VSYNC# */ + RCAR_GP_PIN(9, 2), RCAR_GP_PIN(9, 3), +}; +static const unsigned int vin5_sync_mux[] = { + VI5_HSYNC_N_MARK, VI5_VSYNC_N_MARK, +}; +static const unsigned int vin5_field_pins[] = { + RCAR_GP_PIN(9, 16), +}; +static const unsigned int vin5_field_mux[] = { + VI5_FIELD_MARK, +}; +static const unsigned int vin5_clkenb_pins[] = { + RCAR_GP_PIN(9, 1), +}; +static const unsigned int vin5_clkenb_mux[] = { + VI5_CLKENB_MARK, +}; +static const unsigned int vin5_clk_pins[] = { + RCAR_GP_PIN(9, 0), +}; +static const unsigned int vin5_clk_mux[] = { + VI5_CLK_MARK, +}; static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(avb_link), @@ -1028,6 +1470,62 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(sdhi0_ctrl), SH_PFC_PIN_GROUP(sdhi0_cd), SH_PFC_PIN_GROUP(sdhi0_wp), + VIN_DATA_PIN_GROUP(vin0_data, 24), + VIN_DATA_PIN_GROUP(vin0_data, 20), + SH_PFC_PIN_GROUP(vin0_data18), + VIN_DATA_PIN_GROUP(vin0_data, 16), + VIN_DATA_PIN_GROUP(vin0_data, 12), + VIN_DATA_PIN_GROUP(vin0_data, 10), + VIN_DATA_PIN_GROUP(vin0_data, 8), + SH_PFC_PIN_GROUP(vin0_sync), + SH_PFC_PIN_GROUP(vin0_field), + SH_PFC_PIN_GROUP(vin0_clkenb), + SH_PFC_PIN_GROUP(vin0_clk), + VIN_DATA_PIN_GROUP(vin1_data, 24), + VIN_DATA_PIN_GROUP(vin1_data, 20), + SH_PFC_PIN_GROUP(vin1_data18), + VIN_DATA_PIN_GROUP(vin1_data, 16), + VIN_DATA_PIN_GROUP(vin1_data, 12), + VIN_DATA_PIN_GROUP(vin1_data, 10), + VIN_DATA_PIN_GROUP(vin1_data, 8), + VIN_DATA_PIN_GROUP(vin1_data_b, 24), + VIN_DATA_PIN_GROUP(vin1_data_b, 20), + SH_PFC_PIN_GROUP(vin1_data18_b), + VIN_DATA_PIN_GROUP(vin1_data_b, 16), + SH_PFC_PIN_GROUP(vin1_sync), + SH_PFC_PIN_GROUP(vin1_field), + SH_PFC_PIN_GROUP(vin1_clkenb), + SH_PFC_PIN_GROUP(vin1_clk), + VIN_DATA_PIN_GROUP(vin2_data, 16), + VIN_DATA_PIN_GROUP(vin2_data, 12), + VIN_DATA_PIN_GROUP(vin2_data, 10), + VIN_DATA_PIN_GROUP(vin2_data, 8), + SH_PFC_PIN_GROUP(vin2_sync), + SH_PFC_PIN_GROUP(vin2_field), + SH_PFC_PIN_GROUP(vin2_clkenb), + SH_PFC_PIN_GROUP(vin2_clk), + VIN_DATA_PIN_GROUP(vin3_data, 16), + VIN_DATA_PIN_GROUP(vin3_data, 12), + VIN_DATA_PIN_GROUP(vin3_data, 10), + VIN_DATA_PIN_GROUP(vin3_data, 8), + SH_PFC_PIN_GROUP(vin3_sync), + SH_PFC_PIN_GROUP(vin3_field), + SH_PFC_PIN_GROUP(vin3_clkenb), + SH_PFC_PIN_GROUP(vin3_clk), + VIN_DATA_PIN_GROUP(vin4_data, 12), + VIN_DATA_PIN_GROUP(vin4_data, 10), + VIN_DATA_PIN_GROUP(vin4_data, 8), + SH_PFC_PIN_GROUP(vin4_sync), + SH_PFC_PIN_GROUP(vin4_field), + SH_PFC_PIN_GROUP(vin4_clkenb), + SH_PFC_PIN_GROUP(vin4_clk), + VIN_DATA_PIN_GROUP(vin5_data, 12), + VIN_DATA_PIN_GROUP(vin5_data, 10), + VIN_DATA_PIN_GROUP(vin5_data, 8), + SH_PFC_PIN_GROUP(vin5_sync), + SH_PFC_PIN_GROUP(vin5_field), + SH_PFC_PIN_GROUP(vin5_clkenb), + SH_PFC_PIN_GROUP(vin5_clk), }; static const char * const avb_groups[] = { @@ -1087,6 +1585,79 @@ static const char * const sdhi0_groups[] = { "sdhi0_wp", }; +static const char * const vin0_groups[] = { + "vin0_data24", + "vin0_data20", + "vin0_data18", + "vin0_data16", + "vin0_data12", + "vin0_data10", + "vin0_data8", + "vin0_sync", + "vin0_field", + "vin0_clkenb", + "vin0_clk", +}; + +static const char * const vin1_groups[] = { + "vin1_data24", + "vin1_data20", + "vin1_data18", + "vin1_data16", + "vin1_data12", + "vin1_data10", + "vin1_data8", + "vin1_data24_b", + "vin1_data20_b", + "vin1_data16_b", + "vin1_sync", + "vin1_field", + "vin1_clkenb", + "vin1_clk", +}; + +static const char * const vin2_groups[] = { + "vin2_data16", + "vin2_data12", + "vin2_data10", + "vin2_data8", + "vin2_sync", + "vin2_field", + "vin2_clkenb", + "vin2_clk", +}; + +static const char * const vin3_groups[] = { + "vin3_data16", + "vin3_data12", + "vin3_data10", + "vin3_data8", + "vin3_sync", + "vin3_field", + "vin3_clkenb", + "vin3_clk", +}; + +static const char * const vin4_groups[] = { + "vin4_data12", + "vin4_data10", + "vin4_data8", + "vin4_sync", + "vin4_field", + "vin4_clkenb", + "vin4_clk", +}; + +static const char * const vin5_groups[] = { + "vin5_data12", + "vin5_data10", + "vin5_data8", + "vin5_sync", + "vin5_field", + "vin5_clkenb", + "vin5_clk", +}; + static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(avb), SH_PFC_FUNCTION(can0), @@ -1096,6 +1667,12 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(scif0), SH_PFC_FUNCTION(scif3), SH_PFC_FUNCTION(sdhi0), + SH_PFC_FUNCTION(vin0), + SH_PFC_FUNCTION(vin1), + SH_PFC_FUNCTION(vin2), + SH_PFC_FUNCTION(vin3), + SH_PFC_FUNCTION(vin4), + SH_PFC_FUNCTION(vin5), }; static const struct pinmux_cfg_reg pinmux_config_regs[] = { -- cgit 1.4.1 From 2b84bf892956d7d0f7e35a187bc2109f1909850f Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Fri, 5 Aug 2016 23:54:20 +0300 Subject: pinctrl: sh-pfc: r8a7792: Add DU pin groups Add DU pin groups to the R8A7792 PFC driver. Signed-off-by: Sergei Shtylyov Signed-off-by: Geert Uytterhoeven --- drivers/pinctrl/sh-pfc/pfc-r8a7792.c | 144 +++++++++++++++++++++++++++++++++++ 1 file changed, 144 insertions(+) diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7792.c b/drivers/pinctrl/sh-pfc/pfc-r8a7792.c index a0fc276b29aa..92c670992b3d 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7792.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7792.c @@ -834,6 +834,120 @@ static const unsigned int can_clk_pins[] = { static const unsigned int can_clk_mux[] = { CAN_CLK_MARK, }; +/* - DU --------------------------------------------------------------------- */ +static const unsigned int du0_rgb666_pins[] = { + /* R[7:2], G[7:2], B[7:2] */ + RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 5), + RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 3), RCAR_GP_PIN(0, 2), + RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13), + RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10), + RCAR_GP_PIN(0, 23), RCAR_GP_PIN(0, 22), RCAR_GP_PIN(0, 21), + RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 18), +}; +static const unsigned int du0_rgb666_mux[] = { + DU0_DR7_Y9_DATA7_MARK, DU0_DR6_Y8_DATA6_MARK, DU0_DR5_Y7_DATA5_MARK, + DU0_DR4_Y6_DATA4_MARK, DU0_DR3_Y5_DATA3_MARK, DU0_DR2_Y4_DATA2_MARK, + DU0_DG7_Y3_DATA15_MARK, DU0_DG6_Y2_DATA14_MARK, DU0_DG5_Y1_DATA13_MARK, + DU0_DG4_Y0_DATA12_MARK, DU0_DG3_C7_DATA11_MARK, DU0_DG2_C6_DATA10_MARK, + DU0_DB7_C5_MARK, DU0_DB6_C4_MARK, DU0_DB5_C3_MARK, + DU0_DB4_C2_MARK, DU0_DB3_C1_MARK, DU0_DB2_C0_MARK, +}; +static const unsigned int du0_rgb888_pins[] = { + /* R[7:0], G[7:0], B[7:0] */ + RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 5), + RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 3), RCAR_GP_PIN(0, 2), + RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 0), + RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13), + RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10), + RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 8), + RCAR_GP_PIN(0, 23), RCAR_GP_PIN(0, 22), RCAR_GP_PIN(0, 21), + RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 18), + RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 16), +}; +static const unsigned int du0_rgb888_mux[] = { + DU0_DR7_Y9_DATA7_MARK, DU0_DR6_Y8_DATA6_MARK, DU0_DR5_Y7_DATA5_MARK, + DU0_DR4_Y6_DATA4_MARK, DU0_DR3_Y5_DATA3_MARK, DU0_DR2_Y4_DATA2_MARK, + DU0_DR1_DATA1_MARK, DU0_DR0_DATA0_MARK, + DU0_DG7_Y3_DATA15_MARK, DU0_DG6_Y2_DATA14_MARK, DU0_DG5_Y1_DATA13_MARK, + DU0_DG4_Y0_DATA12_MARK, DU0_DG3_C7_DATA11_MARK, DU0_DG2_C6_DATA10_MARK, + DU0_DG1_DATA9_MARK, DU0_DG0_DATA8_MARK, + DU0_DB7_C5_MARK, DU0_DB6_C4_MARK, DU0_DB5_C3_MARK, + DU0_DB4_C2_MARK, DU0_DB3_C1_MARK, DU0_DB2_C0_MARK, + DU0_DB1_MARK, DU0_DB0_MARK, +}; +static const unsigned int du0_sync_pins[] = { + /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */ + RCAR_GP_PIN(0, 25), RCAR_GP_PIN(0, 24), +}; +static const unsigned int du0_sync_mux[] = { + DU0_EXVSYNC_DU0_VSYNC_MARK, DU0_EXHSYNC_DU0_HSYNC_MARK, +}; +static const unsigned int du0_oddf_pins[] = { + /* EXODDF/ODDF/DISP/CDE */ + RCAR_GP_PIN(0, 26), +}; +static const unsigned int du0_oddf_mux[] = { + DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK +}; +static const unsigned int du0_disp_pins[] = { + /* DISP */ + RCAR_GP_PIN(0, 27), +}; +static const unsigned int du0_disp_mux[] = { + DU0_DISP_MARK, +}; +static const unsigned int du0_cde_pins[] = { + /* CDE */ + RCAR_GP_PIN(0, 28), +}; +static const unsigned int du0_cde_mux[] = { + DU0_CDE_MARK, +}; +static const unsigned int du1_rgb666_pins[] = { + /* R[7:2], G[7:2], B[7:2] */ + RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), + RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 0), + RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9), + RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), + RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 15), + RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 12), +}; +static const unsigned int du1_rgb666_mux[] = { + DU1_DR7_DATA5_MARK, DU1_DR6_DATA4_MARK, DU1_DR5_Y7_DATA3_MARK, + DU1_DR4_Y6_DATA2_MARK, DU1_DR3_Y5_DATA1_MARK, DU1_DR2_Y4_DATA0_MARK, + DU1_DG7_Y3_DATA11_MARK, DU1_DG6_Y2_DATA10_MARK, DU1_DG5_Y1_DATA9_MARK, + DU1_DG4_Y0_DATA8_MARK, DU1_DG3_C7_DATA7_MARK, DU1_DG2_C6_DATA6_MARK, + DU1_DB7_C5_MARK, DU1_DB6_C4_MARK, DU1_DB5_C3_DATA15_MARK, + DU1_DB4_C2_DATA14_MARK, DU1_DB3_C1_DATA13_MARK, DU1_DB2_C0_DATA12_MARK, +}; +static const unsigned int du1_sync_pins[] = { + /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */ + RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18), +}; +static const unsigned int du1_sync_mux[] = { + DU1_EXVSYNC_DU1_VSYNC_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK, +}; +static const unsigned int du1_oddf_pins[] = { + /* EXODDF/ODDF/DISP/CDE */ + RCAR_GP_PIN(1, 20), +}; +static const unsigned int du1_oddf_mux[] = { + DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK +}; +static const unsigned int du1_disp_pins[] = { + /* DISP */ + RCAR_GP_PIN(1, 21), +}; +static const unsigned int du1_disp_mux[] = { + DU1_DISP_MARK, +}; +static const unsigned int du1_cde_pins[] = { + /* CDE */ + RCAR_GP_PIN(1, 22), +}; +static const unsigned int du1_cde_mux[] = { + DU1_CDE_MARK, +}; /* - INTC ------------------------------------------------------------------- */ static const unsigned int intc_irq0_pins[] = { /* IRQ0 */ @@ -1448,6 +1562,17 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(can0_data), SH_PFC_PIN_GROUP(can1_data), SH_PFC_PIN_GROUP(can_clk), + SH_PFC_PIN_GROUP(du0_rgb666), + SH_PFC_PIN_GROUP(du0_rgb888), + SH_PFC_PIN_GROUP(du0_sync), + SH_PFC_PIN_GROUP(du0_oddf), + SH_PFC_PIN_GROUP(du0_disp), + SH_PFC_PIN_GROUP(du0_cde), + SH_PFC_PIN_GROUP(du1_rgb666), + SH_PFC_PIN_GROUP(du1_sync), + SH_PFC_PIN_GROUP(du1_oddf), + SH_PFC_PIN_GROUP(du1_disp), + SH_PFC_PIN_GROUP(du1_cde), SH_PFC_PIN_GROUP(intc_irq0), SH_PFC_PIN_GROUP(intc_irq1), SH_PFC_PIN_GROUP(intc_irq2), @@ -1548,6 +1673,23 @@ static const char * const can1_groups[] = { "can_clk", }; +static const char * const du0_groups[] = { + "du0_rgb666", + "du0_rgb888", + "du0_sync", + "du0_oddf", + "du0_disp", + "du0_cde", +}; + +static const char * const du1_groups[] = { + "du1_rgb666", + "du1_sync", + "du1_oddf", + "du1_disp", + "du1_cde", +}; + static const char * const intc_groups[] = { "intc_irq0", "intc_irq1", @@ -1662,6 +1804,8 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(avb), SH_PFC_FUNCTION(can0), SH_PFC_FUNCTION(can1), + SH_PFC_FUNCTION(du0), + SH_PFC_FUNCTION(du1), SH_PFC_FUNCTION(intc), SH_PFC_FUNCTION(lbsc), SH_PFC_FUNCTION(scif0), -- cgit 1.4.1 From 2e47707918b6208db26a5692d5be0fc2765c4e8a Mon Sep 17 00:00:00 2001 From: Marcus Cooper Date: Sat, 30 Jul 2016 16:20:22 +0200 Subject: pinctrl: sun6i: add SPDIF to pin description. Add the SPDIF mux functionality to the pinctrl for the Allwinner A31 SoC. Signed-off-by: Marcus Cooper Acked-by: Maxime Ripard Signed-off-by: Linus Walleij --- drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c b/drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c index 022863ab0c58..a70b52957e24 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c +++ b/drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c @@ -896,10 +896,18 @@ static const struct sunxi_desc_pin sun6i_a31_pins[] = { SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 27), SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + /* + * The SPDIF block is not referenced at all in the A31 user + * manual. However it is described in the code leaked and the + * configuration files supplied by vendors. + */ + SUNXI_FUNCTION(0x3, "spdif")), /* SPDIF IN */ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 28), SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + /* Undocumented mux function - see above */ + SUNXI_FUNCTION(0x3, "spdif")), /* SPDIF OUT */ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 29), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), -- cgit 1.4.1 From 647dbd1e84871f6c0548f7fbb46eefc4da21f783 Mon Sep 17 00:00:00 2001 From: Stephen Boyd Date: Mon, 11 Jul 2016 12:01:09 -0700 Subject: pinctrl: qcom: Add generic ssbi and spmi GPIO/MPP bindings The drivers don't really need to know which PMIC they're for, so make a generic binding for them. This alleviates us from updating the drivers every time a new PMIC comes out. It's still recommended that we update the binding with new PMIC models and always specify the specific model for the MPPs and gpios before the generic compatible string in devicetree, but this at least cuts down on adding more and more compatible strings to the drivers until we actually need them. Cc: Acked-by: "Ivan T. Ivanov" Reviewed-by: Bjorn Andersson Acked-by: Rob Herring Signed-off-by: Stephen Boyd Signed-off-by: Linus Walleij --- Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.txt | 5 ++++- Documentation/devicetree/bindings/pinctrl/qcom,pmic-mpp.txt | 5 ++++- drivers/pinctrl/qcom/pinctrl-spmi-gpio.c | 1 + drivers/pinctrl/qcom/pinctrl-spmi-mpp.c | 1 + 4 files changed, 10 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.txt b/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.txt index a54c39ebbf8b..8d893a874634 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.txt +++ b/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.txt @@ -17,6 +17,9 @@ PMIC's from Qualcomm. "qcom,pm8994-gpio" "qcom,pma8084-gpio" + And must contain either "qcom,spmi-gpio" or "qcom,ssbi-gpio" + if the device is on an spmi bus or an ssbi bus respectively + - reg: Usage: required Value type: @@ -183,7 +186,7 @@ to specify in a pin configuration subnode: Example: pm8921_gpio: gpio@150 { - compatible = "qcom,pm8921-gpio"; + compatible = "qcom,pm8921-gpio", "qcom,ssbi-gpio"; reg = <0x150 0x160>; interrupts = <192 1>, <193 1>, <194 1>, <195 1>, <196 1>, <197 1>, diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,pmic-mpp.txt b/Documentation/devicetree/bindings/pinctrl/qcom,pmic-mpp.txt index b484ba1af78c..2ab95bc26066 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,pmic-mpp.txt +++ b/Documentation/devicetree/bindings/pinctrl/qcom,pmic-mpp.txt @@ -19,6 +19,9 @@ of PMIC's from Qualcomm. "qcom,pm8994-mpp", "qcom,pma8084-mpp", + And must contain either "qcom,spmi-mpp" or "qcom,ssbi-mpp" + if the device is on an spmi bus or an ssbi bus respectively. + - reg: Usage: required Value type: @@ -158,7 +161,7 @@ to specify in a pin configuration subnode: Example: mpps@a000 { - compatible = "qcom,pm8841-mpp"; + compatible = "qcom,pm8841-mpp", "qcom,spmi-mpp"; reg = <0xa000>; gpio-controller; #gpio-cells = <2>; diff --git a/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c b/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c index 686accb89f52..664b641fd776 100644 --- a/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c +++ b/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c @@ -800,6 +800,7 @@ static const struct of_device_id pmic_gpio_of_match[] = { { .compatible = "qcom,pm8941-gpio" }, /* 36 GPIO's */ { .compatible = "qcom,pm8994-gpio" }, /* 22 GPIO's */ { .compatible = "qcom,pma8084-gpio" }, /* 22 GPIO's */ + { .compatible = "qcom,spmi-gpio" }, /* Generic */ { }, }; diff --git a/drivers/pinctrl/qcom/pinctrl-spmi-mpp.c b/drivers/pinctrl/qcom/pinctrl-spmi-mpp.c index 1735ffef9d5c..6556dbeae65e 100644 --- a/drivers/pinctrl/qcom/pinctrl-spmi-mpp.c +++ b/drivers/pinctrl/qcom/pinctrl-spmi-mpp.c @@ -914,6 +914,7 @@ static const struct of_device_id pmic_mpp_of_match[] = { { .compatible = "qcom,pm8941-mpp" }, /* 8 MPP's */ { .compatible = "qcom,pm8994-mpp" }, /* 8 MPP's */ { .compatible = "qcom,pma8084-mpp" }, /* 8 MPP's */ + { .compatible = "qcom,spmi-mpp" }, /* Generic */ { }, }; -- cgit 1.4.1 From 0f9d85b7aca3764d7f93699129a89c11535abe1a Mon Sep 17 00:00:00 2001 From: Julia Lawall Date: Fri, 5 Aug 2016 13:26:11 +0200 Subject: pinctrl: nomadik: use of_property_read_bool Use of_property_read_bool to check for the existence of a property. The semantic patch that makes this change is as follows: (http://coccinelle.lip6.fr/) // @@ expression e1,e2,x; @@ - if (of_get_property(e1,e2,NULL)) - x = true; - else - x = false; + x = of_property_read_bool(e1,e2); // Signed-off-by: Julia Lawall Signed-off-by: Linus Walleij --- drivers/pinctrl/nomadik/pinctrl-nomadik.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/pinctrl/nomadik/pinctrl-nomadik.c b/drivers/pinctrl/nomadik/pinctrl-nomadik.c index 35f62180db4e..6f2e1da11b1e 100644 --- a/drivers/pinctrl/nomadik/pinctrl-nomadik.c +++ b/drivers/pinctrl/nomadik/pinctrl-nomadik.c @@ -1110,10 +1110,8 @@ static int nmk_gpio_probe(struct platform_device *dev) return PTR_ERR(nmk_chip); } - if (of_get_property(np, "st,supports-sleepmode", NULL)) - supports_sleepmode = true; - else - supports_sleepmode = false; + supports_sleepmode = + of_property_read_bool(np, "st,supports-sleepmode"); /* Correct platform device ID */ dev->id = nmk_chip->bank; -- cgit 1.4.1 From 1e23437563dd3ad57e30c5d6c29995a982fd649b Mon Sep 17 00:00:00 2001 From: Patrice Chotard Date: Wed, 10 Aug 2016 15:12:58 +0200 Subject: pinctrl: st: Use second parameter to gpio specifier This patch allows to use the second parameter of gpio specifier, which is used to specify whether the gpio is active high or low. Simply remove specific of_xlate callback() and of_gpio_n_cells and use default one set by of_gpiochip_add() which allows to use second parameter gpio specifier. Signed-off-by: Maxime Coquelin Signed-off-by: Patrice Chotard Signed-off-by: Linus Walleij --- .../devicetree/bindings/pinctrl/pinctrl-st.txt | 8 ++++++-- drivers/pinctrl/pinctrl-st.c | 17 ----------------- 2 files changed, 6 insertions(+), 19 deletions(-) diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-st.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-st.txt index 26bcb18f4e60..e6cc5e8f6438 100644 --- a/Documentation/devicetree/bindings/pinctrl/pinctrl-st.txt +++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-st.txt @@ -50,7 +50,11 @@ Optional properties: GPIO controller/bank node. Required properties: - gpio-controller : Indicates this device is a GPIO controller -- #gpio-cells : Should be one. The first cell is the pin number. +- #gpio-cells : Must be two. + - First cell: specifies the pin number inside the controller + - Second cell: specifies whether the pin is logically inverted. + - 0 = active high + - 1 = active low - st,bank-name : Should be a name string for this bank as specified in datasheet. @@ -88,7 +92,7 @@ Example: PIO0: gpio@fe610000 { gpio-controller; - #gpio-cells = <1>; + #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0 0x100>; diff --git a/drivers/pinctrl/pinctrl-st.c b/drivers/pinctrl/pinctrl-st.c index 0de1c67dfb94..2e5c545f5040 100644 --- a/drivers/pinctrl/pinctrl-st.c +++ b/drivers/pinctrl/pinctrl-st.c @@ -799,21 +799,6 @@ static int st_gpio_get_direction(struct gpio_chip *chip, unsigned offset) return (direction == ST_GPIO_DIRECTION_IN); } -static int st_gpio_xlate(struct gpio_chip *gc, - const struct of_phandle_args *gpiospec, u32 *flags) -{ - if (WARN_ON(gc->of_gpio_n_cells < 1)) - return -EINVAL; - - if (WARN_ON(gpiospec->args_count < gc->of_gpio_n_cells)) - return -EINVAL; - - if (gpiospec->args[0] > gc->ngpio) - return -EINVAL; - - return gpiospec->args[0]; -} - /* Pinctrl Groups */ static int st_pctl_get_groups_count(struct pinctrl_dev *pctldev) { @@ -1486,8 +1471,6 @@ static struct gpio_chip st_gpio_template = { .direction_output = st_gpio_direction_output, .get_direction = st_gpio_get_direction, .ngpio = ST_GPIO_PINS_PER_BANK, - .of_gpio_n_cells = 1, - .of_xlate = st_gpio_xlate, }; static struct irq_chip st_gpio_irqchip = { -- cgit 1.4.1 From 7955dac1b7efab7ae1e7522ea9af3fdc18a257d0 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Fri, 12 Aug 2016 12:14:28 +0300 Subject: pinctrl: sh-pfc: r8a7795: Add DU support Only the DU parallel RGB output signals are included, HDMI and TCON pins will be added in separate groups. Signed-off-by: Laurent Pinchart Signed-off-by: Geert Uytterhoeven --- drivers/pinctrl/sh-pfc/pfc-r8a7795.c | 100 +++++++++++++++++++++++++++++++++++ 1 file changed, 100 insertions(+) diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c index 1b35ad9b538d..2e8cc2adbed7 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c @@ -1875,6 +1875,86 @@ static const unsigned int drif3_data1_b_mux[] = { RIF3_D1_B_MARK, }; +/* - DU --------------------------------------------------------------------- */ +static const unsigned int du_rgb666_pins[] = { + /* R[7:2], G[7:2], B[7:2] */ + RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13), + RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10), + RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13), + RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18), + RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5), + RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2), +}; +static const unsigned int du_rgb666_mux[] = { + DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK, + DU_DR3_MARK, DU_DR2_MARK, + DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK, + DU_DG3_MARK, DU_DG2_MARK, + DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK, + DU_DB3_MARK, DU_DB2_MARK, +}; +static const unsigned int du_rgb888_pins[] = { + /* R[7:0], G[7:0], B[7:0] */ + RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13), + RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10), + RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 8), + RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13), + RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18), + RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16), + RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5), + RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2), + RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 0), +}; +static const unsigned int du_rgb888_mux[] = { + DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK, + DU_DR3_MARK, DU_DR2_MARK, DU_DR1_MARK, DU_DR0_MARK, + DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK, + DU_DG3_MARK, DU_DG2_MARK, DU_DG1_MARK, DU_DG0_MARK, + DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK, + DU_DB3_MARK, DU_DB2_MARK, DU_DB1_MARK, DU_DB0_MARK, +}; +static const unsigned int du_clk_out_0_pins[] = { + /* CLKOUT */ + RCAR_GP_PIN(1, 27), +}; +static const unsigned int du_clk_out_0_mux[] = { + DU_DOTCLKOUT0_MARK +}; +static const unsigned int du_clk_out_1_pins[] = { + /* CLKOUT */ + RCAR_GP_PIN(2, 3), +}; +static const unsigned int du_clk_out_1_mux[] = { + DU_DOTCLKOUT1_MARK +}; +static const unsigned int du_sync_pins[] = { + /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */ + RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 4), +}; +static const unsigned int du_sync_mux[] = { + DU_EXVSYNC_DU_VSYNC_MARK, DU_EXHSYNC_DU_HSYNC_MARK +}; +static const unsigned int du_oddf_pins[] = { + /* EXDISP/EXODDF/EXCDE */ + RCAR_GP_PIN(2, 2), +}; +static const unsigned int du_oddf_mux[] = { + DU_EXODDF_DU_ODDF_DISP_CDE_MARK, +}; +static const unsigned int du_cde_pins[] = { + /* CDE */ + RCAR_GP_PIN(2, 0), +}; +static const unsigned int du_cde_mux[] = { + DU_CDE_MARK, +}; +static const unsigned int du_disp_pins[] = { + /* DISP */ + RCAR_GP_PIN(2, 1), +}; +static const unsigned int du_disp_mux[] = { + DU_DISP_MARK, +}; /* - HSCIF0 ----------------------------------------------------------------- */ static const unsigned int hscif0_data_pins[] = { /* RX, TX */ @@ -3597,6 +3677,14 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(drif3_ctrl_b), SH_PFC_PIN_GROUP(drif3_data0_b), SH_PFC_PIN_GROUP(drif3_data1_b), + SH_PFC_PIN_GROUP(du_rgb666), + SH_PFC_PIN_GROUP(du_rgb888), + SH_PFC_PIN_GROUP(du_clk_out_0), + SH_PFC_PIN_GROUP(du_clk_out_1), + SH_PFC_PIN_GROUP(du_sync), + SH_PFC_PIN_GROUP(du_oddf), + SH_PFC_PIN_GROUP(du_cde), + SH_PFC_PIN_GROUP(du_disp), SH_PFC_PIN_GROUP(hscif0_data), SH_PFC_PIN_GROUP(hscif0_clk), SH_PFC_PIN_GROUP(hscif0_ctrl), @@ -3922,6 +4010,17 @@ static const char * const drif3_groups[] = { "drif3_data1_b", }; +static const char * const du_groups[] = { + "du_rgb666", + "du_rgb888", + "du_clk_out_0", + "du_clk_out_1", + "du_sync", + "du_oddf", + "du_cde", + "du_disp", +}; + static const char * const hscif0_groups[] = { "hscif0_data", "hscif0_clk", @@ -4269,6 +4368,7 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(drif1), SH_PFC_FUNCTION(drif2), SH_PFC_FUNCTION(drif3), + SH_PFC_FUNCTION(du), SH_PFC_FUNCTION(hscif0), SH_PFC_FUNCTION(hscif1), SH_PFC_FUNCTION(hscif2), -- cgit 1.4.1 From f9aece7344bd81ce16bafc15f8e90ef0dbd18714 Mon Sep 17 00:00:00 2001 From: Takeshi Kihara Date: Thu, 18 Aug 2016 15:12:32 +0200 Subject: pinctrl: sh-pfc: Initial R8A7796 PFC support This patch adds initial pinctrl driver to support for the R8A7796 SoC. Signed-off-by: Takeshi Kihara [uli: rebased on top of renesas-drivers] Signed-off-by: Ulrich Hecht Signed-off-by: Geert Uytterhoeven --- .../bindings/pinctrl/renesas,pfc-pinctrl.txt | 1 + drivers/pinctrl/sh-pfc/Kconfig | 5 + drivers/pinctrl/sh-pfc/Makefile | 1 + drivers/pinctrl/sh-pfc/core.c | 6 + drivers/pinctrl/sh-pfc/pfc-r8a7796.c | 2072 ++++++++++++++++++++ drivers/pinctrl/sh-pfc/sh_pfc.h | 1 + 6 files changed, 2086 insertions(+) create mode 100644 drivers/pinctrl/sh-pfc/pfc-r8a7796.c diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt index 48db27cadba0..13df9498311a 100644 --- a/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt @@ -21,6 +21,7 @@ Required Properties: - "renesas,pfc-r8a7793": for R8A7793 (R-Car M2-N) compatible pin-controller. - "renesas,pfc-r8a7794": for R8A7794 (R-Car E2) compatible pin-controller. - "renesas,pfc-r8a7795": for R8A7795 (R-Car H3) compatible pin-controller. + - "renesas,pfc-r8a7796": for R8A7796 (R-Car M3-W) compatible pin-controller. - "renesas,pfc-sh73a0": for SH73A0 (SH-Mobile AG5) compatible pin-controller. - reg: Base address and length of each memory resource used by the pin diff --git a/drivers/pinctrl/sh-pfc/Kconfig b/drivers/pinctrl/sh-pfc/Kconfig index 8858c3ee2c61..07eca54bdc1c 100644 --- a/drivers/pinctrl/sh-pfc/Kconfig +++ b/drivers/pinctrl/sh-pfc/Kconfig @@ -74,6 +74,11 @@ config PINCTRL_PFC_R8A7795 depends on ARCH_R8A7795 select PINCTRL_SH_PFC +config PINCTRL_PFC_R8A7796 + def_bool y + depends on ARCH_R8A7796 + select PINCTRL_SH_PFC + config PINCTRL_PFC_SH7203 def_bool y depends on CPU_SUBTYPE_SH7203 diff --git a/drivers/pinctrl/sh-pfc/Makefile b/drivers/pinctrl/sh-pfc/Makefile index ffe7eb7da395..2dda8c63f3cf 100644 --- a/drivers/pinctrl/sh-pfc/Makefile +++ b/drivers/pinctrl/sh-pfc/Makefile @@ -11,6 +11,7 @@ obj-$(CONFIG_PINCTRL_PFC_R8A7792) += pfc-r8a7792.o obj-$(CONFIG_PINCTRL_PFC_R8A7793) += pfc-r8a7791.o obj-$(CONFIG_PINCTRL_PFC_R8A7794) += pfc-r8a7794.o obj-$(CONFIG_PINCTRL_PFC_R8A7795) += pfc-r8a7795.o +obj-$(CONFIG_PINCTRL_PFC_R8A7796) += pfc-r8a7796.o obj-$(CONFIG_PINCTRL_PFC_SH7203) += pfc-sh7203.o obj-$(CONFIG_PINCTRL_PFC_SH7264) += pfc-sh7264.o obj-$(CONFIG_PINCTRL_PFC_SH7269) += pfc-sh7269.o diff --git a/drivers/pinctrl/sh-pfc/core.c b/drivers/pinctrl/sh-pfc/core.c index d74169edf35d..f3a8897d4e8f 100644 --- a/drivers/pinctrl/sh-pfc/core.c +++ b/drivers/pinctrl/sh-pfc/core.c @@ -518,6 +518,12 @@ static const struct of_device_id sh_pfc_of_table[] = { .data = &r8a7795_pinmux_info, }, #endif +#ifdef CONFIG_PINCTRL_PFC_R8A7796 + { + .compatible = "renesas,pfc-r8a7796", + .data = &r8a7796_pinmux_info, + }, +#endif #ifdef CONFIG_PINCTRL_PFC_SH73A0 { .compatible = "renesas,pfc-sh73a0", diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c new file mode 100644 index 000000000000..0d14ca956859 --- /dev/null +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c @@ -0,0 +1,2072 @@ +/* + * R8A7796 processor support - PFC hardware block. + * + * Copyright (C) 2016 Renesas Electronics Corp. + * + * This file is based on the drivers/pinctrl/sh-pfc/pfc-r8a7795.c + * + * R-Car Gen3 processor support - PFC hardware block. + * + * Copyright (C) 2015 Renesas Electronics Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + */ + +#include + +#include "core.h" +#include "sh_pfc.h" + +#define CPU_ALL_PORT(fn, sfx) \ + PORT_GP_16(0, fn, sfx), \ + PORT_GP_29(1, fn, sfx), \ + PORT_GP_15(2, fn, sfx), \ + PORT_GP_16(3, fn, sfx), \ + PORT_GP_18(4, fn, sfx), \ + PORT_GP_26(5, fn, sfx), \ + PORT_GP_32(6, fn, sfx), \ + PORT_GP_4(7, fn, sfx) +/* + * F_() : just information + * FM() : macro for FN_xxx / xxx_MARK + */ + +/* GPSR0 */ +#define GPSR0_15 F_(D15, IP7_11_8) +#define GPSR0_14 F_(D14, IP7_7_4) +#define GPSR0_13 F_(D13, IP7_3_0) +#define GPSR0_12 F_(D12, IP6_31_28) +#define GPSR0_11 F_(D11, IP6_27_24) +#define GPSR0_10 F_(D10, IP6_23_20) +#define GPSR0_9 F_(D9, IP6_19_16) +#define GPSR0_8 F_(D8, IP6_15_12) +#define GPSR0_7 F_(D7, IP6_11_8) +#define GPSR0_6 F_(D6, IP6_7_4) +#define GPSR0_5 F_(D5, IP6_3_0) +#define GPSR0_4 F_(D4, IP5_31_28) +#define GPSR0_3 F_(D3, IP5_27_24) +#define GPSR0_2 F_(D2, IP5_23_20) +#define GPSR0_1 F_(D1, IP5_19_16) +#define GPSR0_0 F_(D0, IP5_15_12) + +/* GPSR1 */ +#define GPSR1_28 FM(CLKOUT) +#define GPSR1_27 F_(EX_WAIT0_A, IP5_11_8) +#define GPSR1_26 F_(WE1_N, IP5_7_4) +#define GPSR1_25 F_(WE0_N, IP5_3_0) +#define GPSR1_24 F_(RD_WR_N, IP4_31_28) +#define GPSR1_23 F_(RD_N, IP4_27_24) +#define GPSR1_22 F_(BS_N, IP4_23_20) +#define GPSR1_21 F_(CS1_N_A26, IP4_19_16) +#define GPSR1_20 F_(CS0_N, IP4_15_12) +#define GPSR1_19 F_(A19, IP4_11_8) +#define GPSR1_18 F_(A18, IP4_7_4) +#define GPSR1_17 F_(A17, IP4_3_0) +#define GPSR1_16 F_(A16, IP3_31_28) +#define GPSR1_15 F_(A15, IP3_27_24) +#define GPSR1_14 F_(A14, IP3_23_20) +#define GPSR1_13 F_(A13, IP3_19_16) +#define GPSR1_12 F_(A12, IP3_15_12) +#define GPSR1_11 F_(A11, IP3_11_8) +#define GPSR1_10 F_(A10, IP3_7_4) +#define GPSR1_9 F_(A9, IP3_3_0) +#define GPSR1_8 F_(A8, IP2_31_28) +#define GPSR1_7 F_(A7, IP2_27_24) +#define GPSR1_6 F_(A6, IP2_23_20) +#define GPSR1_5 F_(A5, IP2_19_16) +#define GPSR1_4 F_(A4, IP2_15_12) +#define GPSR1_3 F_(A3, IP2_11_8) +#define GPSR1_2 F_(A2, IP2_7_4) +#define GPSR1_1 F_(A1, IP2_3_0) +#define GPSR1_0 F_(A0, IP1_31_28) + +/* GPSR2 */ +#define GPSR2_14 F_(AVB_AVTP_CAPTURE_A, IP0_23_20) +#define GPSR2_13 F_(AVB_AVTP_MATCH_A, IP0_19_16) +#define GPSR2_12 F_(AVB_LINK, IP0_15_12) +#define GPSR2_11 F_(AVB_PHY_INT, IP0_11_8) +#define GPSR2_10 F_(AVB_MAGIC, IP0_7_4) +#define GPSR2_9 F_(AVB_MDC, IP0_3_0) +#define GPSR2_8 F_(PWM2_A, IP1_27_24) +#define GPSR2_7 F_(PWM1_A, IP1_23_20) +#define GPSR2_6 F_(PWM0, IP1_19_16) +#define GPSR2_5 F_(IRQ5, IP1_15_12) +#define GPSR2_4 F_(IRQ4, IP1_11_8) +#define GPSR2_3 F_(IRQ3, IP1_7_4) +#define GPSR2_2 F_(IRQ2, IP1_3_0) +#define GPSR2_1 F_(IRQ1, IP0_31_28) +#define GPSR2_0 F_(IRQ0, IP0_27_24) + +/* GPSR3 */ +#define GPSR3_15 F_(SD1_WP, IP11_23_20) +#define GPSR3_14 F_(SD1_CD, IP11_19_16) +#define GPSR3_13 F_(SD0_WP, IP11_15_12) +#define GPSR3_12 F_(SD0_CD, IP11_11_8) +#define GPSR3_11 F_(SD1_DAT3, IP8_31_28) +#define GPSR3_10 F_(SD1_DAT2, IP8_27_24) +#define GPSR3_9 F_(SD1_DAT1, IP8_23_20) +#define GPSR3_8 F_(SD1_DAT0, IP8_19_16) +#define GPSR3_7 F_(SD1_CMD, IP8_15_12) +#define GPSR3_6 F_(SD1_CLK, IP8_11_8) +#define GPSR3_5 F_(SD0_DAT3, IP8_7_4) +#define GPSR3_4 F_(SD0_DAT2, IP8_3_0) +#define GPSR3_3 F_(SD0_DAT1, IP7_31_28) +#define GPSR3_2 F_(SD0_DAT0, IP7_27_24) +#define GPSR3_1 F_(SD0_CMD, IP7_23_20) +#define GPSR3_0 F_(SD0_CLK, IP7_19_16) + +/* GPSR4 */ +#define GPSR4_17 F_(SD3_DS, IP11_11_8) +#define GPSR4_16 F_(SD3_DAT7, IP10_7_4) +#define GPSR4_15 F_(SD3_DAT6, IP10_3_0) +#define GPSR4_14 F_(SD3_DAT5, IP9_31_28) +#define GPSR4_13 F_(SD3_DAT4, IP9_27_24) +#define GPSR4_12 F_(SD3_DAT3, IP10_19_16) +#define GPSR4_11 F_(SD3_DAT2, IP10_15_12) +#define GPSR4_10 F_(SD3_DAT1, IP10_11_8) +#define GPSR4_9 F_(SD3_DAT0, IP10_7_4) +#define GPSR4_8 F_(SD3_CMD, IP10_3_0) +#define GPSR4_7 F_(SD3_CLK, IP9_31_28) +#define GPSR4_6 F_(SD2_DS, IP9_23_20) +#define GPSR4_5 F_(SD2_DAT3, IP9_19_16) +#define GPSR4_4 F_(SD2_DAT2, IP9_15_12) +#define GPSR4_3 F_(SD2_DAT1, IP9_11_8) +#define GPSR4_2 F_(SD2_DAT0, IP9_7_4) +#define GPSR4_1 F_(SD2_CMD, IP9_7_4) +#define GPSR4_0 F_(SD2_CLK, IP9_3_0) + +/* GPSR5 */ +#define GPSR5_25 F_(MLB_DAT, IP14_19_16) +#define GPSR5_24 F_(MLB_SIG, IP14_15_12) +#define GPSR5_23 F_(MLB_CLK, IP14_11_8) +#define GPSR5_22 FM(MSIOF0_RXD) +#define GPSR5_21 F_(MSIOF0_SS2, IP14_7_4) +#define GPSR5_20 FM(MSIOF0_TXD) +#define GPSR5_19 F_(MSIOF0_SS1, IP14_3_0) +#define GPSR5_18 F_(MSIOF0_SYNC, IP13_31_28) +#define GPSR5_17 FM(MSIOF0_SCK) +#define GPSR5_16 F_(HRTS0_N, IP13_27_24) +#define GPSR5_15 F_(HCTS0_N, IP13_23_20) +#define GPSR5_14 F_(HTX0, IP13_19_16) +#define GPSR5_13 F_(HRX0, IP13_15_12) +#define GPSR5_12 F_(HSCK0, IP13_11_8) +#define GPSR5_11 F_(RX2_A, IP13_7_4) +#define GPSR5_10 F_(TX2_A, IP13_3_0) +#define GPSR5_9 F_(SCK2, IP12_31_28) +#define GPSR5_8 F_(RTS1_N_TANS, IP12_27_24) +#define GPSR5_7 F_(CTS1_N, IP12_23_20) +#define GPSR5_6 F_(TX1_A, IP12_19_16) +#define GPSR5_5 F_(RX1_A, IP12_15_12) +#define GPSR5_4 F_(RTS0_N_TANS, IP12_11_8) +#define GPSR5_3 F_(CTS0_N, IP12_7_4) +#define GPSR5_2 F_(TX0, IP12_3_0) +#define GPSR5_1 F_(RX0, IP11_31_28) +#define GPSR5_0 F_(SCK0, IP11_27_24) + +/* GPSR6 */ +#define GPSR6_31 F_(GP6_31, IP18_7_4) +#define GPSR6_30 F_(GP6_30, IP18_3_0) +#define GPSR6_29 F_(USB30_OVC, IP17_31_28) +#define GPSR6_28 F_(USB30_PWEN, IP17_27_24) +#define GPSR6_27 F_(USB1_OVC, IP17_23_20) +#define GPSR6_26 F_(USB1_PWEN, IP17_19_16) +#define GPSR6_25 F_(USB0_OVC, IP17_15_12) +#define GPSR6_24 F_(USB0_PWEN, IP17_11_8) +#define GPSR6_23 F_(AUDIO_CLKB_B, IP17_7_4) +#define GPSR6_22 F_(AUDIO_CLKA_A, IP17_3_0) +#define GPSR6_21 F_(SSI_SDATA9_A, IP16_31_28) +#define GPSR6_20 F_(SSI_SDATA8, IP16_27_24) +#define GPSR6_19 F_(SSI_SDATA7, IP16_23_20) +#define GPSR6_18 F_(SSI_WS78, IP16_19_16) +#define GPSR6_17 F_(SSI_SCK78, IP16_15_12) +#define GPSR6_16 F_(SSI_SDATA6, IP16_11_8) +#define GPSR6_15 F_(SSI_WS6, IP16_7_4) +#define GPSR6_14 F_(SSI_SCK6, IP16_3_0) +#define GPSR6_13 FM(SSI_SDATA5) +#define GPSR6_12 FM(SSI_WS5) +#define GPSR6_11 FM(SSI_SCK5) +#define GPSR6_10 F_(SSI_SDATA4, IP15_31_28) +#define GPSR6_9 F_(SSI_WS4, IP15_27_24) +#define GPSR6_8 F_(SSI_SCK4, IP15_23_20) +#define GPSR6_7 F_(SSI_SDATA3, IP15_19_16) +#define GPSR6_6 F_(SSI_WS34, IP15_15_12) +#define GPSR6_5 F_(SSI_SCK34, IP15_11_8) +#define GPSR6_4 F_(SSI_SDATA2_A, IP15_7_4) +#define GPSR6_3 F_(SSI_SDATA1_A, IP15_3_0) +#define GPSR6_2 F_(SSI_SDATA0, IP14_31_28) +#define GPSR6_1 F_(SSI_WS0129, IP14_27_24) +#define GPSR6_0 F_(SSI_SCK0129, IP14_23_20) + +/* GPSR7 */ +#define GPSR7_3 FM(GP7_03) +#define GPSR7_2 FM(HDMI0_CEC) +#define GPSR7_1 FM(AVS2) +#define GPSR7_0 FM(AVS1) + + +/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */ +#define IP0_3_0 FM(AVB_MDC) F_(0, 0) FM(MSIOF2_SS2_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0_7_4 FM(AVB_MAGIC) F_(0, 0) FM(MSIOF2_SS1_C) FM(SCK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0_11_8 FM(AVB_PHY_INT) F_(0, 0) FM(MSIOF2_SYNC_C) FM(RX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0_15_12 FM(AVB_LINK) F_(0, 0) FM(MSIOF2_SCK_C) FM(TX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0_19_16 FM(AVB_AVTP_MATCH_A) F_(0, 0) FM(MSIOF2_RXD_C) FM(CTS4_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0_23_20 FM(AVB_AVTP_CAPTURE_A) F_(0, 0) FM(MSIOF2_TXD_C) FM(RTS4_N_TANS_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0_27_24 FM(IRQ0) FM(QPOLB) F_(0, 0) FM(DU_CDE) FM(VI4_DATA0_B) FM(CAN0_TX_B) FM(CANFD0_TX_B) FM(MSIOF3_SS1_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0_31_28 FM(IRQ1) FM(QPOLA) F_(0, 0) FM(DU_DISP) FM(VI4_DATA1_B) FM(CAN0_RX_B) FM(CANFD0_RX_B) FM(MSIOF3_SS2_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1_3_0 FM(IRQ2) FM(QCPV_QDE) F_(0, 0) FM(DU_EXODDF_DU_ODDF_DISP_CDE) FM(VI4_DATA2_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SYNC_E) F_(0, 0) FM(PWM3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1_7_4 FM(IRQ3) FM(QSTVB_QVE) FM(A25) FM(DU_DOTCLKOUT1) FM(VI4_DATA3_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SCK_E) F_(0, 0) FM(PWM4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1_11_8 FM(IRQ4) FM(QSTH_QHS) FM(A24) FM(DU_EXHSYNC_DU_HSYNC) FM(VI4_DATA4_B) F_(0, 0) F_(0, 0) FM(MSIOF3_RXD_E) F_(0, 0) FM(PWM5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1_15_12 FM(IRQ5) FM(QSTB_QHE) FM(A23) FM(DU_EXVSYNC_DU_VSYNC) FM(VI4_DATA5_B) F_(0, 0) F_(0, 0) FM(MSIOF3_TXD_E) F_(0, 0) FM(PWM6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1_19_16 FM(PWM0) FM(AVB_AVTP_PPS)FM(A22) F_(0, 0) FM(VI4_DATA6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IECLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1_23_20 FM(PWM1_A) F_(0, 0) FM(A21) FM(HRX3_D) FM(VI4_DATA7_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IERX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1_27_24 FM(PWM2_A) F_(0, 0) FM(A20) FM(HTX3_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IETX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1_31_28 FM(A0) FM(LCDOUT16) FM(MSIOF3_SYNC_B) F_(0, 0) FM(VI4_DATA8) F_(0, 0) FM(DU_DB0) F_(0, 0) F_(0, 0) FM(PWM3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2_3_0 FM(A1) FM(LCDOUT17) FM(MSIOF3_TXD_B) F_(0, 0) FM(VI4_DATA9) F_(0, 0) FM(DU_DB1) F_(0, 0) F_(0, 0) FM(PWM4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2_7_4 FM(A2) FM(LCDOUT18) FM(MSIOF3_SCK_B) F_(0, 0) FM(VI4_DATA10) F_(0, 0) FM(DU_DB2) F_(0, 0) F_(0, 0) FM(PWM5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2_11_8 FM(A3) FM(LCDOUT19) FM(MSIOF3_RXD_B) F_(0, 0) FM(VI4_DATA11) F_(0, 0) FM(DU_DB3) F_(0, 0) F_(0, 0) FM(PWM6_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2_15_12 FM(A4) FM(LCDOUT20) FM(MSIOF3_SS1_B) F_(0, 0) FM(VI4_DATA12) FM(VI5_DATA12) FM(DU_DB4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2_19_16 FM(A5) FM(LCDOUT21) FM(MSIOF3_SS2_B) FM(SCK4_B) FM(VI4_DATA13) FM(VI5_DATA13) FM(DU_DB5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2_23_20 FM(A6) FM(LCDOUT22) FM(MSIOF2_SS1_A) FM(RX4_B) FM(VI4_DATA14) FM(VI5_DATA14) FM(DU_DB6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2_27_24 FM(A7) FM(LCDOUT23) FM(MSIOF2_SS2_A) FM(TX4_B) FM(VI4_DATA15) FM(VI5_DATA15) FM(DU_DB7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2_31_28 FM(A8) FM(RX3_B) FM(MSIOF2_SYNC_A) FM(HRX4_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(SDA6_A) FM(AVB_AVTP_MATCH_B) FM(PWM1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP3_3_0 FM(A9) F_(0, 0) FM(MSIOF2_SCK_A) FM(CTS4_N_B) F_(0, 0) FM(VI5_VSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP3_7_4 FM(A10) F_(0, 0) FM(MSIOF2_RXD_A) FM(RTS4_N_TANS_B) F_(0, 0) FM(VI5_HSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP3_11_8 FM(A11) FM(TX3_B) FM(MSIOF2_TXD_A) FM(HTX4_B) FM(HSCK4) FM(VI5_FIELD) F_(0, 0) FM(SCL6_A) FM(AVB_AVTP_CAPTURE_B) FM(PWM2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) + +/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */ +#define IP3_15_12 FM(A12) FM(LCDOUT12) FM(MSIOF3_SCK_C) F_(0, 0) FM(HRX4_A) FM(VI5_DATA8) FM(DU_DG4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP3_19_16 FM(A13) FM(LCDOUT13) FM(MSIOF3_SYNC_C) F_(0, 0) FM(HTX4_A) FM(VI5_DATA9) FM(DU_DG5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP3_23_20 FM(A14) FM(LCDOUT14) FM(MSIOF3_RXD_C) F_(0, 0) FM(HCTS4_N) FM(VI5_DATA10) FM(DU_DG6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP3_27_24 FM(A15) FM(LCDOUT15) FM(MSIOF3_TXD_C) F_(0, 0) FM(HRTS4_N) FM(VI5_DATA11) FM(DU_DG7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP3_31_28 FM(A16) FM(LCDOUT8) F_(0, 0) F_(0, 0) FM(VI4_FIELD) F_(0, 0) FM(DU_DG0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP4_3_0 FM(A17) FM(LCDOUT9) F_(0, 0) F_(0, 0) FM(VI4_VSYNC_N) F_(0, 0) FM(DU_DG1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP4_7_4 FM(A18) FM(LCDOUT10) F_(0, 0) F_(0, 0) FM(VI4_HSYNC_N) F_(0, 0) FM(DU_DG2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP4_11_8 FM(A19) FM(LCDOUT11) F_(0, 0) F_(0, 0) FM(VI4_CLKENB) F_(0, 0) FM(DU_DG3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP4_15_12 FM(CS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLKENB) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP4_19_16 FM(CS1_N_A26) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLK) F_(0, 0) FM(EX_WAIT0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP4_23_20 FM(BS_N) FM(QSTVA_QVS) FM(MSIOF3_SCK_D) FM(SCK3) FM(HSCK3) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN1_TX) FM(CANFD1_TX) FM(IETX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP4_27_24 FM(RD_N) F_(0, 0) FM(MSIOF3_SYNC_D) FM(RX3_A) FM(HRX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_TX_A) FM(CANFD0_TX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP4_31_28 FM(RD_WR_N) F_(0, 0) FM(MSIOF3_RXD_D) FM(TX3_A) FM(HTX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_RX_A) FM(CANFD0_RX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP5_3_0 FM(WE0_N) F_(0, 0) FM(MSIOF3_TXD_D) FM(CTS3_N) FM(HCTS3_N) F_(0, 0) F_(0, 0) FM(SCL6_B) FM(CAN_CLK) F_(0, 0) FM(IECLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP5_7_4 FM(WE1_N) F_(0, 0) FM(MSIOF3_SS1_D) FM(RTS3_N_TANS) FM(HRTS3_N) F_(0, 0) F_(0, 0) FM(SDA6_B) FM(CAN1_RX) FM(CANFD1_RX) FM(IERX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP5_11_8 FM(EX_WAIT0_A) FM(QCLK) F_(0, 0) F_(0, 0) FM(VI4_CLK) F_(0, 0) FM(DU_DOTCLKOUT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP5_15_12 FM(D0) FM(MSIOF2_SS1_B)FM(MSIOF3_SCK_A) F_(0, 0) FM(VI4_DATA16) FM(VI5_DATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP5_19_16 FM(D1) FM(MSIOF2_SS2_B)FM(MSIOF3_SYNC_A) F_(0, 0) FM(VI4_DATA17) FM(VI5_DATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP5_23_20 FM(D2) F_(0, 0) FM(MSIOF3_RXD_A) F_(0, 0) FM(VI4_DATA18) FM(VI5_DATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP5_27_24 FM(D3) F_(0, 0) FM(MSIOF3_TXD_A) F_(0, 0) FM(VI4_DATA19) FM(VI5_DATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP5_31_28 FM(D4) FM(MSIOF2_SCK_B)F_(0, 0) F_(0, 0) FM(VI4_DATA20) FM(VI5_DATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP6_3_0 FM(D5) FM(MSIOF2_SYNC_B)F_(0, 0) F_(0, 0) FM(VI4_DATA21) FM(VI5_DATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP6_7_4 FM(D6) FM(MSIOF2_RXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA22) FM(VI5_DATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP6_11_8 FM(D7) FM(MSIOF2_TXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA23) FM(VI5_DATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP6_15_12 FM(D8) FM(LCDOUT0) FM(MSIOF2_SCK_D) FM(SCK4_C) FM(VI4_DATA0_A) F_(0, 0) FM(DU_DR0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP6_19_16 FM(D9) FM(LCDOUT1) FM(MSIOF2_SYNC_D) F_(0, 0) FM(VI4_DATA1_A) F_(0, 0) FM(DU_DR1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP6_23_20 FM(D10) FM(LCDOUT2) FM(MSIOF2_RXD_D) FM(HRX3_B) FM(VI4_DATA2_A) FM(CTS4_N_C) FM(DU_DR2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP6_27_24 FM(D11) FM(LCDOUT3) FM(MSIOF2_TXD_D) FM(HTX3_B) FM(VI4_DATA3_A) FM(RTS4_N_TANS_C)FM(DU_DR3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP6_31_28 FM(D12) FM(LCDOUT4) FM(MSIOF2_SS1_D) FM(RX4_C) FM(VI4_DATA4_A) F_(0, 0) FM(DU_DR4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) + +/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */ +#define IP7_3_0 FM(D13) FM(LCDOUT5) FM(MSIOF2_SS2_D) FM(TX4_C) FM(VI4_DATA5_A) F_(0, 0) FM(DU_DR5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP7_7_4 FM(D14) FM(LCDOUT6) FM(MSIOF3_SS1_A) FM(HRX3_C) FM(VI4_DATA6_A) F_(0, 0) FM(DU_DR6) FM(SCL6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP7_11_8 FM(D15) FM(LCDOUT7) FM(MSIOF3_SS2_A) FM(HTX3_C) FM(VI4_DATA7_A) F_(0, 0) FM(DU_DR7) FM(SDA6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP7_15_12 FM(FSCLKST) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP7_19_16 FM(SD0_CLK) F_(0, 0) FM(MSIOF1_SCK_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP7_23_20 FM(SD0_CMD) F_(0, 0) FM(MSIOF1_SYNC_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP7_27_24 FM(SD0_DAT0) F_(0, 0) FM(MSIOF1_RXD_E) F_(0, 0) F_(0, 0) FM(TS_SCK0_B) FM(STP_ISCLK_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP7_31_28 FM(SD0_DAT1) F_(0, 0) FM(MSIOF1_TXD_E) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_B)FM(STP_ISSYNC_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP8_3_0 FM(SD0_DAT2) F_(0, 0) FM(MSIOF1_SS1_E) F_(0, 0) F_(0, 0) FM(TS_SDAT0_B) FM(STP_ISD_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP8_7_4 FM(SD0_DAT3) F_(0, 0) FM(MSIOF1_SS2_E) F_(0, 0) F_(0, 0) FM(TS_SDEN0_B) FM(STP_ISEN_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP8_11_8 FM(SD1_CLK) F_(0, 0) FM(MSIOF1_SCK_G) F_(0, 0) F_(0, 0) FM(SIM0_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP8_15_12 FM(SD1_CMD) F_(0, 0) FM(MSIOF1_SYNC_G) FM(NFCE_N_B) F_(0, 0) FM(SIM0_D_A) FM(STP_IVCXO27_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP8_19_16 FM(SD1_DAT0) FM(SD2_DAT4) FM(MSIOF1_RXD_G) FM(NFWP_N_B) F_(0, 0) FM(TS_SCK1_B) FM(STP_ISCLK_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP8_23_20 FM(SD1_DAT1) FM(SD2_DAT5) FM(MSIOF1_TXD_G) FM(NFDATA14_B) F_(0, 0) FM(TS_SPSYNC1_B)FM(STP_ISSYNC_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP8_27_24 FM(SD1_DAT2) FM(SD2_DAT6) FM(MSIOF1_SS1_G) FM(NFDATA15_B) F_(0, 0) FM(TS_SDAT1_B) FM(STP_ISD_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP8_31_28 FM(SD1_DAT3) FM(SD2_DAT7) FM(MSIOF1_SS2_G) FM(NFRB_N_B) F_(0, 0) FM(TS_SDEN1_B) FM(STP_ISEN_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP9_3_0 FM(SD2_CLK) F_(0, 0) F_(0, 0) FM(NFDATA8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP9_7_4 FM(SD2_CMD) F_(0, 0) F_(0, 0) FM(NFDATA9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP9_11_8 FM(SD2_DAT0) F_(0, 0) F_(0, 0) FM(NFDATA10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP9_15_12 FM(SD2_DAT1) F_(0, 0) F_(0, 0) FM(NFDATA11) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP9_19_16 FM(SD2_DAT2) F_(0, 0) F_(0, 0) FM(NFDATA12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP9_23_20 FM(SD2_DAT3) F_(0, 0) F_(0, 0) FM(NFDATA13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP9_27_24 FM(SD2_DS) F_(0, 0) F_(0, 0) FM(NFALE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SATA_DEVSLP_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP9_31_28 FM(SD3_CLK) F_(0, 0) F_(0, 0) FM(NFWE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP10_3_0 FM(SD3_CMD) F_(0, 0) F_(0, 0) FM(NFRE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP10_7_4 FM(SD3_DAT0) F_(0, 0) F_(0, 0) FM(NFDATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP10_11_8 FM(SD3_DAT1) F_(0, 0) F_(0, 0) FM(NFDATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP10_15_12 FM(SD3_DAT2) F_(0, 0) F_(0, 0) FM(NFDATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP10_19_16 FM(SD3_DAT3) F_(0, 0) F_(0, 0) FM(NFDATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP10_23_20 FM(SD3_DAT4) FM(SD2_CD_A) F_(0, 0) FM(NFDATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP10_27_24 FM(SD3_DAT5) FM(SD2_WP_A) F_(0, 0) FM(NFDATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP10_31_28 FM(SD3_DAT6) FM(SD3_CD) F_(0, 0) FM(NFDATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP11_3_0 FM(SD3_DAT7) FM(SD3_WP) F_(0, 0) FM(NFDATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP11_7_4 FM(SD3_DS) F_(0, 0) F_(0, 0) FM(NFCLE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP11_11_8 FM(SD0_CD) F_(0, 0) FM(NFDATA14_A) F_(0, 0) FM(SCL2_B) FM(SIM0_RST_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) + +/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */ +#define IP11_15_12 FM(SD0_WP) F_(0, 0) FM(NFDATA15_A) F_(0, 0) FM(SDA2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP11_19_16 FM(SD1_CD) F_(0, 0) FM(NFRB_N_A) F_(0, 0) F_(0, 0) FM(SIM0_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP11_23_20 FM(SD1_WP) F_(0, 0) FM(NFCE_N_A) F_(0, 0) F_(0, 0) FM(SIM0_D_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP11_27_24 FM(SCK0) FM(HSCK1_B) FM(MSIOF1_SS2_B) FM(AUDIO_CLKC_B) FM(SDA2_A) FM(SIM0_RST_B) FM(STP_OPWM_0_C) FM(RIF0_CLK_B) F_(0, 0) FM(ADICHS2) FM(SCK5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP11_31_28 FM(RX0) FM(HRX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SCK0_C) FM(STP_ISCLK_0_C) FM(RIF0_D0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP12_3_0 FM(TX0) FM(HTX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_C)FM(STP_ISSYNC_0_C) FM(RIF0_D1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP12_7_4 FM(CTS0_N) FM(HCTS1_N_B) FM(MSIOF1_SYNC_B) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_C)FM(STP_ISSYNC_1_C) FM(RIF1_SYNC_B) FM(AUDIO_CLKOUT_C) FM(ADICS_SAMP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP12_11_8 FM(RTS0_N_TANS) FM(HRTS1_N_B) FM(MSIOF1_SS1_B) FM(AUDIO_CLKA_B) FM(SCL2_A) F_(0, 0) FM(STP_IVCXO27_1_C) FM(RIF0_SYNC_B) FM(FSO_TOE_A) FM(ADICHS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP12_15_12 FM(RX1_A) FM(HRX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDAT0_C) FM(STP_ISD_0_C) FM(RIF1_CLK_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP12_19_16 FM(TX1_A) FM(HTX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDEN0_C) FM(STP_ISEN_0_C) FM(RIF1_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP12_23_20 FM(CTS1_N) FM(HCTS1_N_A) FM(MSIOF1_RXD_B) F_(0, 0) F_(0, 0) FM(TS_SDEN1_C) FM(STP_ISEN_1_C) FM(RIF1_D0_B) F_(0, 0) FM(ADIDATA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP12_27_24 FM(RTS1_N_TANS) FM(HRTS1_N_A) FM(MSIOF1_TXD_B) F_(0, 0) F_(0, 0) FM(TS_SDAT1_C) FM(STP_ISD_1_C) FM(RIF1_D1_B) F_(0, 0) FM(ADICHS0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP12_31_28 FM(SCK2) FM(SCIF_CLK_B) FM(MSIOF1_SCK_B) F_(0, 0) F_(0, 0) FM(TS_SCK1_C) FM(STP_ISCLK_1_C) FM(RIF1_CLK_B) F_(0, 0) FM(ADICLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP13_3_0 FM(TX2_A) F_(0, 0) F_(0, 0) FM(SD2_CD_B) FM(SCL1_A) F_(0, 0) FM(FMCLK_A) FM(RIF1_D1_C) F_(0, 0) FM(FSO_CFE_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP13_7_4 FM(RX2_A) F_(0, 0) F_(0, 0) FM(SD2_WP_B) FM(SDA1_A) F_(0, 0) FM(FMIN_A) FM(RIF1_SYNC_C) F_(0, 0) FM(FSO_CFE_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP13_11_8 FM(HSCK0) F_(0, 0) FM(MSIOF1_SCK_D) FM(AUDIO_CLKB_A) FM(SSI_SDATA1_B)FM(TS_SCK0_D) FM(STP_ISCLK_0_D) FM(RIF0_CLK_C) F_(0, 0) F_(0, 0) FM(RX5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP13_15_12 FM(HRX0) F_(0, 0) FM(MSIOF1_RXD_D) F_(0, 0) FM(SSI_SDATA2_B)FM(TS_SDEN0_D) FM(STP_ISEN_0_D) FM(RIF0_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP13_19_16 FM(HTX0) F_(0, 0) FM(MSIOF1_TXD_D) F_(0, 0) FM(SSI_SDATA9_B)FM(TS_SDAT0_D) FM(STP_ISD_0_D) FM(RIF0_D1_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP13_23_20 FM(HCTS0_N) FM(RX2_B) FM(MSIOF1_SYNC_D) F_(0, 0) FM(SSI_SCK9_A) FM(TS_SPSYNC0_D)FM(STP_ISSYNC_0_D) FM(RIF0_SYNC_C) FM(AUDIO_CLKOUT1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP13_27_24 FM(HRTS0_N) FM(TX2_B) FM(MSIOF1_SS1_D) F_(0, 0) FM(SSI_WS9_A) F_(0, 0) FM(STP_IVCXO27_0_D) FM(BPFCLK_A) FM(AUDIO_CLKOUT2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP13_31_28 FM(MSIOF0_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_A) F_(0, 0) FM(TX5_B) F_(0, 0) F_(0, 0) FM(BPFCLK_D) F_(0, 0) F_(0, 0) +#define IP14_3_0 FM(MSIOF0_SS1) FM(RX5_A) FM(NFWP_N_A) FM(AUDIO_CLKA_C) FM(SSI_SCK2_A) F_(0, 0) FM(STP_IVCXO27_0_C) F_(0, 0) FM(AUDIO_CLKOUT3_A) F_(0, 0) FM(TCLK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP14_7_4 FM(MSIOF0_SS2) FM(TX5_A) FM(MSIOF1_SS2_D) FM(AUDIO_CLKC_A) FM(SSI_WS2_A) F_(0, 0) FM(STP_OPWM_0_D) F_(0, 0) FM(AUDIO_CLKOUT_D) F_(0, 0) FM(SPEEDIN_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP14_11_8 FM(MLB_CLK) F_(0, 0) FM(MSIOF1_SCK_F) F_(0, 0) FM(SCL1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP14_15_12 FM(MLB_SIG) FM(RX1_B) FM(MSIOF1_SYNC_F) F_(0, 0) FM(SDA1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP14_19_16 FM(MLB_DAT) FM(TX1_B) FM(MSIOF1_RXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP14_23_20 FM(SSI_SCK0129) F_(0, 0) FM(MSIOF1_TXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP14_27_24 FM(SSI_WS0129) F_(0, 0) FM(MSIOF1_SS1_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) + +/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */ +#define IP14_31_28 FM(SSI_SDATA0) F_(0, 0) FM(MSIOF1_SS2_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP15_3_0 FM(SSI_SDATA1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP15_7_4 FM(SSI_SDATA2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(SSI_SCK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP15_11_8 FM(SSI_SCK34) F_(0, 0) FM(MSIOF1_SS1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP15_15_12 FM(SSI_WS34) FM(HCTS2_N_A) FM(MSIOF1_SS2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP15_19_16 FM(SSI_SDATA3) FM(HRTS2_N_A) FM(MSIOF1_TXD_A) F_(0, 0) F_(0, 0) FM(TS_SCK0_A) FM(STP_ISCLK_0_A) FM(RIF0_D1_A) FM(RIF2_D0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP15_23_20 FM(SSI_SCK4) FM(HRX2_A) FM(MSIOF1_SCK_A) F_(0, 0) F_(0, 0) FM(TS_SDAT0_A) FM(STP_ISD_0_A) FM(RIF0_CLK_A) FM(RIF2_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP15_27_24 FM(SSI_WS4) FM(HTX2_A) FM(MSIOF1_SYNC_A) F_(0, 0) F_(0, 0) FM(TS_SDEN0_A) FM(STP_ISEN_0_A) FM(RIF0_SYNC_A) FM(RIF2_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP15_31_28 FM(SSI_SDATA4) FM(HSCK2_A) FM(MSIOF1_RXD_A) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_A)FM(STP_ISSYNC_0_A) FM(RIF0_D0_A) FM(RIF2_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP16_3_0 FM(SSI_SCK6) F_(0, 0) F_(0, 0) FM(SIM0_RST_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP16_7_4 FM(SSI_WS6) F_(0, 0) F_(0, 0) FM(SIM0_D_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP16_11_8 FM(SSI_SDATA6) F_(0, 0) F_(0, 0) FM(SIM0_CLK_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP16_15_12 FM(SSI_SCK78) FM(HRX2_B) FM(MSIOF1_SCK_C) F_(0, 0) F_(0, 0) FM(TS_SCK1_A) FM(STP_ISCLK_1_A) FM(RIF1_CLK_A) FM(RIF3_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP16_19_16 FM(SSI_WS78) FM(HTX2_B) FM(MSIOF1_SYNC_C) F_(0, 0) F_(0, 0) FM(TS_SDAT1_A) FM(STP_ISD_1_A) FM(RIF1_SYNC_A) FM(RIF3_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP16_23_20 FM(SSI_SDATA7) FM(HCTS2_N_B) FM(MSIOF1_RXD_C) F_(0, 0) F_(0, 0) FM(TS_SDEN1_A) FM(STP_ISEN_1_A) FM(RIF1_D0_A) FM(RIF3_D0_A) F_(0, 0) FM(TCLK2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP16_27_24 FM(SSI_SDATA8) FM(HRTS2_N_B) FM(MSIOF1_TXD_C) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_A)FM(STP_ISSYNC_1_A) FM(RIF1_D1_A) FM(RIF3_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP16_31_28 FM(SSI_SDATA9_A) FM(HSCK2_B) FM(MSIOF1_SS1_C) FM(HSCK1_A) FM(SSI_WS1_B) FM(SCK1) FM(STP_IVCXO27_1_A) FM(SCK5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP17_3_0 FM(AUDIO_CLKA_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(CC5_OSCOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP17_7_4 FM(AUDIO_CLKB_B) FM(SCIF_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_1_D) FM(REMOCON_A) F_(0, 0) F_(0, 0) FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP17_11_8 FM(USB0_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_RST_C) F_(0, 0) FM(TS_SCK1_D) FM(STP_ISCLK_1_D) FM(BPFCLK_B) FM(RIF3_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HSCK2_C) F_(0, 0) F_(0, 0) +#define IP17_15_12 FM(USB0_OVC) F_(0, 0) F_(0, 0) FM(SIM0_D_C) F_(0, 0) FM(TS_SDAT1_D) FM(STP_ISD_1_D) F_(0, 0) FM(RIF3_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HRX2_C) F_(0, 0) F_(0, 0) +#define IP17_19_16 FM(USB1_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_CLK_C) FM(SSI_SCK1_A) FM(TS_SCK0_E) FM(STP_ISCLK_0_E) FM(FMCLK_B) FM(RIF2_CLK_B) F_(0, 0) FM(SPEEDIN_A) F_(0, 0) F_(0, 0) FM(HTX2_C) F_(0, 0) F_(0, 0) +#define IP17_23_20 FM(USB1_OVC) F_(0, 0) FM(MSIOF1_SS2_C) F_(0, 0) FM(SSI_WS1_A) FM(TS_SDAT0_E) FM(STP_ISD_0_E) FM(FMIN_B) FM(RIF2_SYNC_B) F_(0, 0) FM(REMOCON_B) F_(0, 0) F_(0, 0) FM(HCTS2_N_C) F_(0, 0) F_(0, 0) +#define IP17_27_24 FM(USB30_PWEN) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_B) FM(SSI_SCK2_B) FM(TS_SDEN1_D) FM(STP_ISEN_1_D) FM(STP_OPWM_0_E)FM(RIF3_D0_B) F_(0, 0) FM(TCLK2_B) FM(TPU0TO0) FM(BPFCLK_C) FM(HRTS2_N_C) F_(0, 0) F_(0, 0) +#define IP17_31_28 FM(USB30_OVC) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT1_B) FM(SSI_WS2_B) FM(TS_SPSYNC1_D)FM(STP_ISSYNC_1_D) FM(STP_IVCXO27_0_E)FM(RIF3_D1_B) F_(0, 0) FM(FSO_TOE_B) FM(TPU0TO1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP18_3_0 FM(GP6_30) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT2_B) FM(SSI_SCK9_B) FM(TS_SDEN0_E) FM(STP_ISEN_0_E) F_(0, 0) FM(RIF2_D0_B) F_(0, 0) FM(FSO_CFE_0_A) FM(TPU0TO2) F_(0, 0) FM(FMCLK_C) FM(FMCLK_D) F_(0, 0) +#define IP18_7_4 FM(GP6_31) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT3_B) FM(SSI_WS9_B) FM(TS_SPSYNC0_E)FM(STP_ISSYNC_0_E) F_(0, 0) FM(RIF2_D1_B) F_(0, 0) FM(FSO_CFE_1_A) FM(TPU0TO3) F_(0, 0) FM(FMIN_C) FM(FMIN_D) F_(0, 0) + +#define PINMUX_GPSR \ +\ + GPSR6_31 \ + GPSR6_30 \ + GPSR6_29 \ + GPSR1_28 GPSR6_28 \ + GPSR1_27 GPSR6_27 \ + GPSR1_26 GPSR6_26 \ + GPSR1_25 GPSR5_25 GPSR6_25 \ + GPSR1_24 GPSR5_24 GPSR6_24 \ + GPSR1_23 GPSR5_23 GPSR6_23 \ + GPSR1_22 GPSR5_22 GPSR6_22 \ + GPSR1_21 GPSR5_21 GPSR6_21 \ + GPSR1_20 GPSR5_20 GPSR6_20 \ + GPSR1_19 GPSR5_19 GPSR6_19 \ + GPSR1_18 GPSR5_18 GPSR6_18 \ + GPSR1_17 GPSR4_17 GPSR5_17 GPSR6_17 \ + GPSR1_16 GPSR4_16 GPSR5_16 GPSR6_16 \ +GPSR0_15 GPSR1_15 GPSR3_15 GPSR4_15 GPSR5_15 GPSR6_15 \ +GPSR0_14 GPSR1_14 GPSR2_14 GPSR3_14 GPSR4_14 GPSR5_14 GPSR6_14 \ +GPSR0_13 GPSR1_13 GPSR2_13 GPSR3_13 GPSR4_13 GPSR5_13 GPSR6_13 \ +GPSR0_12 GPSR1_12 GPSR2_12 GPSR3_12 GPSR4_12 GPSR5_12 GPSR6_12 \ +GPSR0_11 GPSR1_11 GPSR2_11 GPSR3_11 GPSR4_11 GPSR5_11 GPSR6_11 \ +GPSR0_10 GPSR1_10 GPSR2_10 GPSR3_10 GPSR4_10 GPSR5_10 GPSR6_10 \ +GPSR0_9 GPSR1_9 GPSR2_9 GPSR3_9 GPSR4_9 GPSR5_9 GPSR6_9 \ +GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR4_8 GPSR5_8 GPSR6_8 \ +GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR4_7 GPSR5_7 GPSR6_7 \ +GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR4_6 GPSR5_6 GPSR6_6 \ +GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 GPSR6_5 \ +GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 GPSR6_4 \ +GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 GPSR6_3 GPSR7_3 \ +GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 GPSR6_2 GPSR7_2 \ +GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 GPSR6_1 GPSR7_1 \ +GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0 GPSR6_0 GPSR7_0 + +#define PINMUX_IPSR \ +\ +FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \ +FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \ +FM(IP0_11_8) IP0_11_8 FM(IP1_11_8) IP1_11_8 FM(IP2_11_8) IP2_11_8 FM(IP3_11_8) IP3_11_8 \ +FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \ +FM(IP0_19_16) IP0_19_16 FM(IP1_19_16) IP1_19_16 FM(IP2_19_16) IP2_19_16 FM(IP3_19_16) IP3_19_16 \ +FM(IP0_23_20) IP0_23_20 FM(IP1_23_20) IP1_23_20 FM(IP2_23_20) IP2_23_20 FM(IP3_23_20) IP3_23_20 \ +FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \ +FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \ +\ +FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \ +FM(IP4_7_4) IP4_7_4 FM(IP5_7_4) IP5_7_4 FM(IP6_7_4) IP6_7_4 FM(IP7_7_4) IP7_7_4 \ +FM(IP4_11_8) IP4_11_8 FM(IP5_11_8) IP5_11_8 FM(IP6_11_8) IP6_11_8 FM(IP7_11_8) IP7_11_8 \ +FM(IP4_15_12) IP4_15_12 FM(IP5_15_12) IP5_15_12 FM(IP6_15_12) IP6_15_12 FM(IP7_15_12) IP7_15_12 \ +FM(IP4_19_16) IP4_19_16 FM(IP5_19_16) IP5_19_16 FM(IP6_19_16) IP6_19_16 FM(IP7_19_16) IP7_19_16 \ +FM(IP4_23_20) IP4_23_20 FM(IP5_23_20) IP5_23_20 FM(IP6_23_20) IP6_23_20 FM(IP7_23_20) IP7_23_20 \ +FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \ +FM(IP4_31_28) IP4_31_28 FM(IP5_31_28) IP5_31_28 FM(IP6_31_28) IP6_31_28 FM(IP7_31_28) IP7_31_28 \ +\ +FM(IP8_3_0) IP8_3_0 FM(IP9_3_0) IP9_3_0 FM(IP10_3_0) IP10_3_0 FM(IP11_3_0) IP11_3_0 \ +FM(IP8_7_4) IP8_7_4 FM(IP9_7_4) IP9_7_4 FM(IP10_7_4) IP10_7_4 FM(IP11_7_4) IP11_7_4 \ +FM(IP8_11_8) IP8_11_8 FM(IP9_11_8) IP9_11_8 FM(IP10_11_8) IP10_11_8 FM(IP11_11_8) IP11_11_8 \ +FM(IP8_15_12) IP8_15_12 FM(IP9_15_12) IP9_15_12 FM(IP10_15_12) IP10_15_12 FM(IP11_15_12) IP11_15_12 \ +FM(IP8_19_16) IP8_19_16 FM(IP9_19_16) IP9_19_16 FM(IP10_19_16) IP10_19_16 FM(IP11_19_16) IP11_19_16 \ +FM(IP8_23_20) IP8_23_20 FM(IP9_23_20) IP9_23_20 FM(IP10_23_20) IP10_23_20 FM(IP11_23_20) IP11_23_20 \ +FM(IP8_27_24) IP8_27_24 FM(IP9_27_24) IP9_27_24 FM(IP10_27_24) IP10_27_24 FM(IP11_27_24) IP11_27_24 \ +FM(IP8_31_28) IP8_31_28 FM(IP9_31_28) IP9_31_28 FM(IP10_31_28) IP10_31_28 FM(IP11_31_28) IP11_31_28 \ +\ +FM(IP12_3_0) IP12_3_0 FM(IP13_3_0) IP13_3_0 FM(IP14_3_0) IP14_3_0 FM(IP15_3_0) IP15_3_0 \ +FM(IP12_7_4) IP12_7_4 FM(IP13_7_4) IP13_7_4 FM(IP14_7_4) IP14_7_4 FM(IP15_7_4) IP15_7_4 \ +FM(IP12_11_8) IP12_11_8 FM(IP13_11_8) IP13_11_8 FM(IP14_11_8) IP14_11_8 FM(IP15_11_8) IP15_11_8 \ +FM(IP12_15_12) IP12_15_12 FM(IP13_15_12) IP13_15_12 FM(IP14_15_12) IP14_15_12 FM(IP15_15_12) IP15_15_12 \ +FM(IP12_19_16) IP12_19_16 FM(IP13_19_16) IP13_19_16 FM(IP14_19_16) IP14_19_16 FM(IP15_19_16) IP15_19_16 \ +FM(IP12_23_20) IP12_23_20 FM(IP13_23_20) IP13_23_20 FM(IP14_23_20) IP14_23_20 FM(IP15_23_20) IP15_23_20 \ +FM(IP12_27_24) IP12_27_24 FM(IP13_27_24) IP13_27_24 FM(IP14_27_24) IP14_27_24 FM(IP15_27_24) IP15_27_24 \ +FM(IP12_31_28) IP12_31_28 FM(IP13_31_28) IP13_31_28 FM(IP14_31_28) IP14_31_28 FM(IP15_31_28) IP15_31_28 \ +\ +FM(IP16_3_0) IP16_3_0 FM(IP17_3_0) IP17_3_0 FM(IP18_3_0) IP18_3_0 \ +FM(IP16_7_4) IP16_7_4 FM(IP17_7_4) IP17_7_4 FM(IP18_7_4) IP18_7_4 \ +FM(IP16_11_8) IP16_11_8 FM(IP17_11_8) IP17_11_8 \ +FM(IP16_15_12) IP16_15_12 FM(IP17_15_12) IP17_15_12 \ +FM(IP16_19_16) IP16_19_16 FM(IP17_19_16) IP17_19_16 \ +FM(IP16_23_20) IP16_23_20 FM(IP17_23_20) IP17_23_20 \ +FM(IP16_27_24) IP16_27_24 FM(IP17_27_24) IP17_27_24 \ +FM(IP16_31_28) IP16_31_28 FM(IP17_31_28) IP17_31_28 + +/* MOD_SEL0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ +#define MOD_SEL0_31_30_29 FM(SEL_MSIOF3_0) FM(SEL_MSIOF3_1) FM(SEL_MSIOF3_2) FM(SEL_MSIOF3_3) FM(SEL_MSIOF3_4) F_(0, 0) F_(0, 0) F_(0, 0) +#define MOD_SEL0_28_27 FM(SEL_MSIOF2_0) FM(SEL_MSIOF2_1) FM(SEL_MSIOF2_2) FM(SEL_MSIOF2_3) +#define MOD_SEL0_26_25_24 FM(SEL_MSIOF1_0) FM(SEL_MSIOF1_1) FM(SEL_MSIOF1_2) FM(SEL_MSIOF1_3) FM(SEL_MSIOF1_4) FM(SEL_MSIOF1_5) FM(SEL_MSIOF1_6) F_(0, 0) +#define MOD_SEL0_23 FM(SEL_LBSC_0) FM(SEL_LBSC_1) +#define MOD_SEL0_22 FM(SEL_IEBUS_0) FM(SEL_IEBUS_1) +#define MOD_SEL0_21 FM(SEL_I2C2_0) FM(SEL_I2C2_1) +#define MOD_SEL0_20 FM(SEL_I2C1_0) FM(SEL_I2C1_1) +#define MOD_SEL0_19 FM(SEL_HSCIF4_0) FM(SEL_HSCIF4_1) +#define MOD_SEL0_18_17 FM(SEL_HSCIF3_0) FM(SEL_HSCIF3_1) FM(SEL_HSCIF3_2) FM(SEL_HSCIF3_3) +#define MOD_SEL0_16 FM(SEL_HSCIF1_0) FM(SEL_HSCIF1_1) +#define MOD_SEL0_15 FM(SEL_FSO_0) FM(SEL_FSO_1) +#define MOD_SEL0_14_13 FM(SEL_HSCIF2_0) FM(SEL_HSCIF2_1) FM(SEL_HSCIF2_2) F_(0, 0) +#define MOD_SEL0_12 FM(SEL_ETHERAVB_0) FM(SEL_ETHERAVB_1) +#define MOD_SEL0_11 FM(SEL_DRIF3_0) FM(SEL_DRIF3_1) +#define MOD_SEL0_10 FM(SEL_DRIF2_0) FM(SEL_DRIF2_1) +#define MOD_SEL0_9_8 FM(SEL_DRIF1_0) FM(SEL_DRIF1_1) FM(SEL_DRIF1_2) F_(0, 0) +#define MOD_SEL0_7_6 FM(SEL_DRIF0_0) FM(SEL_DRIF0_1) FM(SEL_DRIF0_2) F_(0, 0) +#define MOD_SEL0_5 FM(SEL_CANFD0_0) FM(SEL_CANFD0_1) +#define MOD_SEL0_4_3 FM(SEL_ADG_A_0) FM(SEL_ADG_A_1) FM(SEL_ADG_A_2) FM(SEL_ADG_A_3) +#define MOD_SEL0_2 FM(SEL_5LINE_0) FM(SEL_5LINE_1) + +/* MOD_SEL1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ +#define MOD_SEL1_31_30 FM(SEL_TSIF1_0) FM(SEL_TSIF1_1) FM(SEL_TSIF1_2) FM(SEL_TSIF1_3) +#define MOD_SEL1_29_28_27 FM(SEL_TSIF0_0) FM(SEL_TSIF0_1) FM(SEL_TSIF0_2) FM(SEL_TSIF0_3) FM(SEL_TSIF0_4) F_(0, 0) F_(0, 0) F_(0, 0) +#define MOD_SEL1_26 FM(SEL_TIMER_TMU_0) FM(SEL_TIMER_TMU_1) +#define MOD_SEL1_25_24 FM(SEL_SSP1_1_0) FM(SEL_SSP1_1_1) FM(SEL_SSP1_1_2) FM(SEL_SSP1_1_3) +#define MOD_SEL1_23_22_21 FM(SEL_SSP1_0_0) FM(SEL_SSP1_0_1) FM(SEL_SSP1_0_2) FM(SEL_SSP1_0_3) FM(SEL_SSP1_0_4) F_(0, 0) F_(0, 0) F_(0, 0) +#define MOD_SEL1_20 FM(SEL_SSI_0) FM(SEL_SSI_1) +#define MOD_SEL1_19 FM(SEL_SPEED_PULSE_0) FM(SEL_SPEED_PULSE_1) +#define MOD_SEL1_18_17 FM(SEL_SIMCARD_0) FM(SEL_SIMCARD_1) FM(SEL_SIMCARD_2) FM(SEL_SIMCARD_3) +#define MOD_SEL1_16 FM(SEL_SDHI2_0) FM(SEL_SDHI2_1) +#define MOD_SEL1_15_14 FM(SEL_SCIF4_0) FM(SEL_SCIF4_1) FM(SEL_SCIF4_2) F_(0, 0) +#define MOD_SEL1_13 FM(SEL_SCIF3_0) FM(SEL_SCIF3_1) +#define MOD_SEL1_12 FM(SEL_SCIF2_0) FM(SEL_SCIF2_1) +#define MOD_SEL1_11 FM(SEL_SCIF1_0) FM(SEL_SCIF1_1) +#define MOD_SEL1_10 FM(SEL_SATA_0) FM(SEL_SATA_1) +#define MOD_SEL1_9 FM(SEL_REMOCON_0) FM(SEL_REMOCON_1) +#define MOD_SEL1_6 FM(SEL_RCAN0_0) FM(SEL_RCAN0_1) +#define MOD_SEL1_5 FM(SEL_PWM6_0) FM(SEL_PWM6_1) +#define MOD_SEL1_4 FM(SEL_PWM5_0) FM(SEL_PWM5_1) +#define MOD_SEL1_3 FM(SEL_PWM4_0) FM(SEL_PWM4_1) +#define MOD_SEL1_2 FM(SEL_PWM3_0) FM(SEL_PWM3_1) +#define MOD_SEL1_1 FM(SEL_PWM2_0) FM(SEL_PWM2_1) +#define MOD_SEL1_0 FM(SEL_PWM1_0) FM(SEL_PWM1_1) + +/* MOD_SEL1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ +#define MOD_SEL2_31 FM(I2C_SEL_5_0) FM(I2C_SEL_5_1) +#define MOD_SEL2_30 FM(I2C_SEL_3_0) FM(I2C_SEL_3_1) +#define MOD_SEL2_29 FM(I2C_SEL_0_0) FM(I2C_SEL_0_1) +#define MOD_SEL2_28_27 FM(SEL_FM_0) FM(SEL_FM_1) FM(SEL_FM_2) FM(SEL_FM_3) +#define MOD_SEL2_26 FM(SEL_SCIF5_0) FM(SEL_SCIF5_1) +#define MOD_SEL2_25_24_23 FM(SEL_I2C6_0) FM(SEL_I2C6_1) FM(SEL_I2C6_2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define MOD_SEL2_22 FM(SEL_NDF_0) FM(SEL_NDF_1) +#define MOD_SEL2_21 FM(SEL_SSI2_0) FM(SEL_SSI2_1) +#define MOD_SEL2_20 FM(SEL_SSI9_0) FM(SEL_SSI9_1) +#define MOD_SEL2_19 FM(SEL_TIMER_TMU2_0) FM(SEL_TIMER_TMU2_1) +#define MOD_SEL2_18 FM(SEL_ADG_B_0) FM(SEL_ADG_B_1) +#define MOD_SEL2_17 FM(SEL_ADG_C_0) FM(SEL_ADG_C_1) +#define MOD_SEL2_0 FM(SEL_VIN4_0) FM(SEL_VIN4_1) + +#define PINMUX_MOD_SELS \ +\ +MOD_SEL0_31_30_29 MOD_SEL1_31_30 MOD_SEL2_31 \ + MOD_SEL2_30 \ + MOD_SEL1_29_28_27 MOD_SEL2_29 \ +MOD_SEL0_28_27 MOD_SEL2_28_27 \ +MOD_SEL0_26_25_24 MOD_SEL1_26 MOD_SEL2_26 \ + MOD_SEL1_25_24 MOD_SEL2_25_24_23 \ +MOD_SEL0_23 MOD_SEL1_23_22_21 \ +MOD_SEL0_22 MOD_SEL2_22 \ +MOD_SEL0_21 MOD_SEL2_21 \ +MOD_SEL0_20 MOD_SEL1_20 MOD_SEL2_20 \ +MOD_SEL0_19 MOD_SEL1_19 MOD_SEL2_19 \ +MOD_SEL0_18_17 MOD_SEL1_18_17 MOD_SEL2_18 \ + MOD_SEL2_17 \ +MOD_SEL0_16 MOD_SEL1_16 \ +MOD_SEL0_15 MOD_SEL1_15_14 \ +MOD_SEL0_14_13 \ + MOD_SEL1_13 \ +MOD_SEL0_12 MOD_SEL1_12 \ +MOD_SEL0_11 MOD_SEL1_11 \ +MOD_SEL0_10 MOD_SEL1_10 \ +MOD_SEL0_9_8 MOD_SEL1_9 \ +MOD_SEL0_7_6 \ + MOD_SEL1_6 \ +MOD_SEL0_5 MOD_SEL1_5 \ +MOD_SEL0_4_3 MOD_SEL1_4 \ + MOD_SEL1_3 \ +MOD_SEL0_2 MOD_SEL1_2 \ + MOD_SEL1_1 \ + MOD_SEL1_0 MOD_SEL2_0 + +enum { + PINMUX_RESERVED = 0, + + PINMUX_DATA_BEGIN, + GP_ALL(DATA), + PINMUX_DATA_END, + +#define F_(x, y) +#define FM(x) FN_##x, + PINMUX_FUNCTION_BEGIN, + GP_ALL(FN), + PINMUX_GPSR + PINMUX_IPSR + PINMUX_MOD_SELS + PINMUX_FUNCTION_END, +#undef F_ +#undef FM + +#define F_(x, y) +#define FM(x) x##_MARK, + PINMUX_MARK_BEGIN, + PINMUX_GPSR + PINMUX_IPSR + PINMUX_MOD_SELS + PINMUX_MARK_END, +#undef F_ +#undef FM +}; + +static const u16 pinmux_data[] = { + PINMUX_DATA_GP_ALL(), + + PINMUX_SINGLE(AVS1), + PINMUX_SINGLE(AVS2), + PINMUX_SINGLE(CLKOUT), + PINMUX_SINGLE(GP7_03), + PINMUX_SINGLE(HDMI0_CEC), + PINMUX_SINGLE(MSIOF0_RXD), + PINMUX_SINGLE(MSIOF0_SCK), + PINMUX_SINGLE(MSIOF0_TXD), + PINMUX_SINGLE(SSI_SCK5), + PINMUX_SINGLE(SSI_SDATA5), + PINMUX_SINGLE(SSI_WS5), + + /* IPSR0 */ + PINMUX_IPSR_GPSR(IP0_3_0, AVB_MDC), + PINMUX_IPSR_MSEL(IP0_3_0, MSIOF2_SS2_C, SEL_MSIOF2_2), + + PINMUX_IPSR_GPSR(IP0_7_4, AVB_MAGIC), + PINMUX_IPSR_MSEL(IP0_7_4, MSIOF2_SS1_C, SEL_MSIOF2_2), + PINMUX_IPSR_MSEL(IP0_7_4, SCK4_A, SEL_SCIF4_0), + + PINMUX_IPSR_GPSR(IP0_11_8, AVB_PHY_INT), + PINMUX_IPSR_MSEL(IP0_11_8, MSIOF2_SYNC_C, SEL_MSIOF2_2), + PINMUX_IPSR_MSEL(IP0_11_8, RX4_A, SEL_SCIF4_0), + + PINMUX_IPSR_GPSR(IP0_15_12, AVB_LINK), + PINMUX_IPSR_MSEL(IP0_15_12, MSIOF2_SCK_C, SEL_MSIOF2_2), + PINMUX_IPSR_MSEL(IP0_15_12, TX4_A, SEL_SCIF4_0), + + PINMUX_IPSR_MSEL(IP0_19_16, AVB_AVTP_MATCH_A, SEL_ETHERAVB_0), + PINMUX_IPSR_MSEL(IP0_19_16, MSIOF2_RXD_C, SEL_MSIOF2_2), + PINMUX_IPSR_MSEL(IP0_19_16, CTS4_N_A, SEL_SCIF4_0), + + PINMUX_IPSR_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A, SEL_ETHERAVB_0), + PINMUX_IPSR_MSEL(IP0_23_20, MSIOF2_TXD_C, SEL_MSIOF2_2), + PINMUX_IPSR_MSEL(IP0_23_20, RTS4_N_TANS_A, SEL_SCIF4_0), + + PINMUX_IPSR_GPSR(IP0_27_24, IRQ0), + PINMUX_IPSR_GPSR(IP0_27_24, QPOLB), + PINMUX_IPSR_GPSR(IP0_27_24, DU_CDE), + PINMUX_IPSR_MSEL(IP0_27_24, VI4_DATA0_B, SEL_VIN4_1), + PINMUX_IPSR_MSEL(IP0_27_24, CAN0_TX_B, SEL_RCAN0_1), + PINMUX_IPSR_MSEL(IP0_27_24, CANFD0_TX_B, SEL_CANFD0_1), + PINMUX_IPSR_MSEL(IP0_27_24, MSIOF3_SS2_E, SEL_MSIOF3_4), + + PINMUX_IPSR_GPSR(IP0_31_28, IRQ1), + PINMUX_IPSR_GPSR(IP0_31_28, QPOLA), + PINMUX_IPSR_GPSR(IP0_31_28, DU_DISP), + PINMUX_IPSR_MSEL(IP0_31_28, VI4_DATA1_B, SEL_VIN4_1), + PINMUX_IPSR_MSEL(IP0_31_28, CAN0_RX_B, SEL_RCAN0_1), + PINMUX_IPSR_MSEL(IP0_31_28, CANFD0_RX_B, SEL_CANFD0_1), + PINMUX_IPSR_MSEL(IP0_27_24, MSIOF3_SS1_E, SEL_MSIOF3_4), + + /* IPSR1 */ + PINMUX_IPSR_GPSR(IP1_3_0, IRQ2), + PINMUX_IPSR_GPSR(IP1_3_0, QCPV_QDE), + PINMUX_IPSR_GPSR(IP1_3_0, DU_EXODDF_DU_ODDF_DISP_CDE), + PINMUX_IPSR_MSEL(IP1_3_0, VI4_DATA2_B, SEL_VIN4_1), + PINMUX_IPSR_MSEL(IP1_3_0, PWM3_B, SEL_PWM3_1), + PINMUX_IPSR_MSEL(IP1_3_0, MSIOF3_SYNC_E, SEL_MSIOF3_4), + + PINMUX_IPSR_GPSR(IP1_7_4, IRQ3), + PINMUX_IPSR_GPSR(IP1_7_4, QSTVB_QVE), + PINMUX_IPSR_GPSR(IP1_7_4, A25), + PINMUX_IPSR_GPSR(IP1_7_4, DU_DOTCLKOUT1), + PINMUX_IPSR_MSEL(IP1_7_4, VI4_DATA3_B, SEL_VIN4_1), + PINMUX_IPSR_MSEL(IP1_7_4, PWM4_B, SEL_PWM4_1), + PINMUX_IPSR_MSEL(IP1_7_4, MSIOF3_SCK_E, SEL_MSIOF3_4), + + PINMUX_IPSR_GPSR(IP1_11_8, IRQ4), + PINMUX_IPSR_GPSR(IP1_11_8, QSTH_QHS), + PINMUX_IPSR_GPSR(IP1_11_8, A24), + PINMUX_IPSR_GPSR(IP1_11_8, DU_EXHSYNC_DU_HSYNC), + PINMUX_IPSR_MSEL(IP1_11_8, VI4_DATA4_B, SEL_VIN4_1), + PINMUX_IPSR_MSEL(IP1_11_8, PWM5_B, SEL_PWM5_1), + PINMUX_IPSR_MSEL(IP1_11_8, MSIOF3_RXD_E, SEL_MSIOF3_4), + + PINMUX_IPSR_GPSR(IP1_15_12, IRQ5), + PINMUX_IPSR_GPSR(IP1_15_12, QSTB_QHE), + PINMUX_IPSR_GPSR(IP1_15_12, A23), + PINMUX_IPSR_GPSR(IP1_15_12, DU_EXVSYNC_DU_VSYNC), + PINMUX_IPSR_MSEL(IP1_15_12, VI4_DATA5_B, SEL_VIN4_1), + PINMUX_IPSR_MSEL(IP1_15_12, PWM6_B, SEL_PWM6_1), + PINMUX_IPSR_MSEL(IP1_15_12, MSIOF3_TXD_E, SEL_MSIOF3_4), + + PINMUX_IPSR_GPSR(IP1_19_16, PWM0), + PINMUX_IPSR_GPSR(IP1_19_16, AVB_AVTP_PPS), + PINMUX_IPSR_GPSR(IP1_19_16, A22), + PINMUX_IPSR_MSEL(IP1_19_16, VI4_DATA6_B, SEL_VIN4_1), + PINMUX_IPSR_MSEL(IP1_19_16, IECLK_B, SEL_IEBUS_1), + + PINMUX_IPSR_MSEL(IP1_23_20, PWM1_A, SEL_PWM1_0), + PINMUX_IPSR_GPSR(IP1_23_20, A21), + PINMUX_IPSR_MSEL(IP1_23_20, HRX3_D, SEL_HSCIF3_3), + PINMUX_IPSR_MSEL(IP1_23_20, VI4_DATA7_B, SEL_VIN4_1), + PINMUX_IPSR_MSEL(IP1_23_20, IERX_B, SEL_IEBUS_1), + + PINMUX_IPSR_MSEL(IP1_27_24, PWM2_A, SEL_PWM2_0), + PINMUX_IPSR_GPSR(IP1_27_24, A20), + PINMUX_IPSR_MSEL(IP1_27_24, HTX3_D, SEL_HSCIF3_3), + PINMUX_IPSR_MSEL(IP1_27_24, IETX_B, SEL_IEBUS_1), + + PINMUX_IPSR_GPSR(IP1_31_28, A0), + PINMUX_IPSR_GPSR(IP1_31_28, LCDOUT16), + PINMUX_IPSR_MSEL(IP1_31_28, MSIOF3_SYNC_B, SEL_MSIOF3_1), + PINMUX_IPSR_GPSR(IP1_31_28, VI4_DATA8), + PINMUX_IPSR_GPSR(IP1_31_28, DU_DB0), + PINMUX_IPSR_MSEL(IP1_31_28, PWM3_A, SEL_PWM3_0), + + /* IPSR2 */ + PINMUX_IPSR_GPSR(IP2_3_0, A1), + PINMUX_IPSR_GPSR(IP2_3_0, LCDOUT17), + PINMUX_IPSR_MSEL(IP2_3_0, MSIOF3_TXD_B, SEL_MSIOF3_1), + PINMUX_IPSR_GPSR(IP2_3_0, VI4_DATA9), + PINMUX_IPSR_GPSR(IP2_3_0, DU_DB1), + PINMUX_IPSR_MSEL(IP2_3_0, PWM4_A, SEL_PWM4_0), + + PINMUX_IPSR_GPSR(IP2_7_4, A2), + PINMUX_IPSR_GPSR(IP2_7_4, LCDOUT18), + PINMUX_IPSR_MSEL(IP2_7_4, MSIOF3_SCK_B, SEL_MSIOF3_1), + PINMUX_IPSR_GPSR(IP2_7_4, VI4_DATA10), + PINMUX_IPSR_GPSR(IP2_7_4, DU_DB2), + PINMUX_IPSR_MSEL(IP2_7_4, PWM5_A, SEL_PWM5_0), + + PINMUX_IPSR_GPSR(IP2_11_8, A3), + PINMUX_IPSR_GPSR(IP2_11_8, LCDOUT19), + PINMUX_IPSR_MSEL(IP2_11_8, MSIOF3_RXD_B, SEL_MSIOF3_1), + PINMUX_IPSR_GPSR(IP2_11_8, VI4_DATA11), + PINMUX_IPSR_GPSR(IP2_11_8, DU_DB3), + PINMUX_IPSR_MSEL(IP2_11_8, PWM6_A, SEL_PWM6_0), + + PINMUX_IPSR_GPSR(IP2_15_12, A4), + PINMUX_IPSR_GPSR(IP2_15_12, LCDOUT20), + PINMUX_IPSR_MSEL(IP2_15_12, MSIOF3_SS1_B, SEL_MSIOF3_1), + PINMUX_IPSR_GPSR(IP2_15_12, VI4_DATA12), + PINMUX_IPSR_GPSR(IP2_15_12, VI5_DATA12), + PINMUX_IPSR_GPSR(IP2_15_12, DU_DB4), + + PINMUX_IPSR_GPSR(IP2_19_16, A5), + PINMUX_IPSR_GPSR(IP2_19_16, LCDOUT21), + PINMUX_IPSR_MSEL(IP2_19_16, MSIOF3_SS2_B, SEL_MSIOF3_1), + PINMUX_IPSR_MSEL(IP2_19_16, SCK4_B, SEL_SCIF4_1), + PINMUX_IPSR_GPSR(IP2_19_16, VI4_DATA13), + PINMUX_IPSR_GPSR(IP2_19_16, VI5_DATA13), + PINMUX_IPSR_GPSR(IP2_19_16, DU_DB5), + + PINMUX_IPSR_GPSR(IP2_23_20, A6), + PINMUX_IPSR_GPSR(IP2_23_20, LCDOUT22), + PINMUX_IPSR_MSEL(IP2_23_20, MSIOF2_SS1_A, SEL_MSIOF2_0), + PINMUX_IPSR_MSEL(IP2_23_20, RX4_B, SEL_SCIF4_1), + PINMUX_IPSR_GPSR(IP2_23_20, VI4_DATA14), + PINMUX_IPSR_GPSR(IP2_23_20, VI5_DATA14), + PINMUX_IPSR_GPSR(IP2_23_20, DU_DB6), + + PINMUX_IPSR_GPSR(IP2_27_24, A7), + PINMUX_IPSR_GPSR(IP2_27_24, LCDOUT23), + PINMUX_IPSR_MSEL(IP2_27_24, MSIOF2_SS2_A, SEL_MSIOF2_0), + PINMUX_IPSR_MSEL(IP2_27_24, TX4_B, SEL_SCIF4_1), + PINMUX_IPSR_GPSR(IP2_27_24, VI4_DATA15), + PINMUX_IPSR_GPSR(IP2_27_24, VI5_DATA15), + PINMUX_IPSR_GPSR(IP2_27_24, DU_DB7), + + PINMUX_IPSR_GPSR(IP2_31_28, A8), + PINMUX_IPSR_MSEL(IP2_31_28, RX3_B, SEL_SCIF3_1), + PINMUX_IPSR_MSEL(IP2_31_28, MSIOF2_SYNC_A, SEL_MSIOF2_0), + PINMUX_IPSR_MSEL(IP2_31_28, HRX4_B, SEL_HSCIF4_1), + PINMUX_IPSR_MSEL(IP2_31_28, SDA6_A, SEL_I2C6_0), + PINMUX_IPSR_MSEL(IP2_31_28, AVB_AVTP_MATCH_B, SEL_ETHERAVB_1), + PINMUX_IPSR_MSEL(IP2_31_28, PWM1_B, SEL_PWM1_1), + + /* IPSR3 */ + PINMUX_IPSR_GPSR(IP3_3_0, A9), + PINMUX_IPSR_MSEL(IP3_3_0, MSIOF2_SCK_A, SEL_MSIOF2_0), + PINMUX_IPSR_MSEL(IP3_3_0, CTS4_N_B, SEL_SCIF4_1), + PINMUX_IPSR_GPSR(IP3_3_0, VI5_VSYNC_N), + + PINMUX_IPSR_GPSR(IP3_7_4, A10), + PINMUX_IPSR_MSEL(IP3_7_4, MSIOF2_RXD_A, SEL_MSIOF2_0), + PINMUX_IPSR_MSEL(IP3_7_4, RTS4_N_TANS_B, SEL_SCIF4_1), + PINMUX_IPSR_GPSR(IP3_7_4, VI5_HSYNC_N), + + PINMUX_IPSR_GPSR(IP3_11_8, A11), + PINMUX_IPSR_MSEL(IP3_11_8, TX3_B, SEL_SCIF3_1), + PINMUX_IPSR_MSEL(IP3_11_8, MSIOF2_TXD_A, SEL_MSIOF2_0), + PINMUX_IPSR_MSEL(IP3_11_8, HTX4_B, SEL_HSCIF4_1), + PINMUX_IPSR_GPSR(IP3_11_8, HSCK4), + PINMUX_IPSR_GPSR(IP3_11_8, VI5_FIELD), + PINMUX_IPSR_MSEL(IP3_11_8, SCL6_A, SEL_I2C6_0), + PINMUX_IPSR_MSEL(IP3_11_8, AVB_AVTP_CAPTURE_B, SEL_ETHERAVB_1), + PINMUX_IPSR_MSEL(IP3_11_8, PWM2_B, SEL_PWM2_1), + + PINMUX_IPSR_GPSR(IP3_15_12, A12), + PINMUX_IPSR_GPSR(IP3_15_12, LCDOUT12), + PINMUX_IPSR_MSEL(IP3_15_12, MSIOF3_SCK_C, SEL_MSIOF3_2), + PINMUX_IPSR_MSEL(IP3_15_12, HRX4_A, SEL_HSCIF4_0), + PINMUX_IPSR_GPSR(IP3_15_12, VI5_DATA8), + PINMUX_IPSR_GPSR(IP3_15_12, DU_DG4), + + PINMUX_IPSR_GPSR(IP3_19_16, A13), + PINMUX_IPSR_GPSR(IP3_19_16, LCDOUT13), + PINMUX_IPSR_MSEL(IP3_19_16, MSIOF3_SYNC_C, SEL_MSIOF3_2), + PINMUX_IPSR_MSEL(IP3_19_16, HTX4_A, SEL_HSCIF4_0), + PINMUX_IPSR_GPSR(IP3_19_16, VI5_DATA9), + PINMUX_IPSR_GPSR(IP3_19_16, DU_DG5), + + PINMUX_IPSR_GPSR(IP3_23_20, A14), + PINMUX_IPSR_GPSR(IP3_23_20, LCDOUT14), + PINMUX_IPSR_MSEL(IP3_23_20, MSIOF3_RXD_C, SEL_MSIOF3_2), + PINMUX_IPSR_GPSR(IP3_23_20, HCTS4_N), + PINMUX_IPSR_GPSR(IP3_23_20, VI5_DATA10), + PINMUX_IPSR_GPSR(IP3_23_20, DU_DG6), + + PINMUX_IPSR_GPSR(IP3_27_24, A15), + PINMUX_IPSR_GPSR(IP3_27_24, LCDOUT15), + PINMUX_IPSR_MSEL(IP3_27_24, MSIOF3_TXD_C, SEL_MSIOF3_2), + PINMUX_IPSR_GPSR(IP3_27_24, HRTS4_N), + PINMUX_IPSR_GPSR(IP3_27_24, VI5_DATA11), + PINMUX_IPSR_GPSR(IP3_27_24, DU_DG7), + + PINMUX_IPSR_GPSR(IP3_31_28, A16), + PINMUX_IPSR_GPSR(IP3_31_28, LCDOUT8), + PINMUX_IPSR_GPSR(IP3_31_28, VI4_FIELD), + PINMUX_IPSR_GPSR(IP3_31_28, DU_DG0), + + /* IPSR4 */ + PINMUX_IPSR_GPSR(IP4_3_0, A17), + PINMUX_IPSR_GPSR(IP4_3_0, LCDOUT9), + PINMUX_IPSR_GPSR(IP4_3_0, VI4_VSYNC_N), + PINMUX_IPSR_GPSR(IP4_3_0, DU_DG1), + + PINMUX_IPSR_GPSR(IP4_7_4, A18), + PINMUX_IPSR_GPSR(IP4_7_4, LCDOUT10), + PINMUX_IPSR_GPSR(IP4_7_4, VI4_HSYNC_N), + PINMUX_IPSR_GPSR(IP4_7_4, DU_DG2), + + PINMUX_IPSR_GPSR(IP4_11_8, A19), + PINMUX_IPSR_GPSR(IP4_11_8, LCDOUT11), + PINMUX_IPSR_GPSR(IP4_11_8, VI4_CLKENB), + PINMUX_IPSR_GPSR(IP4_11_8, DU_DG3), + + PINMUX_IPSR_GPSR(IP4_15_12, CS0_N), + PINMUX_IPSR_GPSR(IP4_15_12, VI5_CLKENB), + + PINMUX_IPSR_GPSR(IP4_19_16, CS1_N_A26), + PINMUX_IPSR_GPSR(IP4_19_16, VI5_CLK), + PINMUX_IPSR_MSEL(IP4_19_16, EX_WAIT0_B, SEL_LBSC_1), + + PINMUX_IPSR_GPSR(IP4_23_20, BS_N), + PINMUX_IPSR_GPSR(IP4_23_20, QSTVA_QVS), + PINMUX_IPSR_MSEL(IP4_23_20, MSIOF3_SCK_D, SEL_MSIOF3_3), + PINMUX_IPSR_GPSR(IP4_23_20, SCK3), + PINMUX_IPSR_GPSR(IP4_23_20, HSCK3), + PINMUX_IPSR_GPSR(IP4_23_20, CAN1_TX), + PINMUX_IPSR_GPSR(IP4_23_20, CANFD1_TX), + PINMUX_IPSR_MSEL(IP4_23_20, IETX_A, SEL_IEBUS_0), + + PINMUX_IPSR_GPSR(IP4_27_24, RD_N), + PINMUX_IPSR_MSEL(IP4_27_24, MSIOF3_SYNC_D, SEL_MSIOF3_3), + PINMUX_IPSR_MSEL(IP4_27_24, RX3_A, SEL_SCIF3_0), + PINMUX_IPSR_MSEL(IP4_27_24, HRX3_A, SEL_HSCIF3_0), + PINMUX_IPSR_MSEL(IP4_27_24, CAN0_TX_A, SEL_RCAN0_0), + PINMUX_IPSR_MSEL(IP4_27_24, CANFD0_TX_A, SEL_CANFD0_0), + + PINMUX_IPSR_GPSR(IP4_31_28, RD_WR_N), + PINMUX_IPSR_MSEL(IP4_31_28, MSIOF3_RXD_D, SEL_MSIOF3_3), + PINMUX_IPSR_MSEL(IP4_31_28, TX3_A, SEL_SCIF3_0), + PINMUX_IPSR_MSEL(IP4_31_28, HTX3_A, SEL_HSCIF3_0), + PINMUX_IPSR_MSEL(IP4_31_28, CAN0_RX_A, SEL_RCAN0_0), + PINMUX_IPSR_MSEL(IP4_31_28, CANFD0_RX_A, SEL_CANFD0_0), + + /* IPSR5 */ + PINMUX_IPSR_GPSR(IP5_3_0, WE0_N), + PINMUX_IPSR_MSEL(IP5_3_0, MSIOF3_TXD_D, SEL_MSIOF3_3), + PINMUX_IPSR_GPSR(IP5_3_0, CTS3_N), + PINMUX_IPSR_GPSR(IP5_3_0, HCTS3_N), + PINMUX_IPSR_MSEL(IP5_3_0, SCL6_B, SEL_I2C6_1), + PINMUX_IPSR_GPSR(IP5_3_0, CAN_CLK), + PINMUX_IPSR_MSEL(IP5_3_0, IECLK_A, SEL_IEBUS_0), + + PINMUX_IPSR_GPSR(IP5_7_4, WE1_N), + PINMUX_IPSR_MSEL(IP5_7_4, MSIOF3_SS1_D, SEL_MSIOF3_3), + PINMUX_IPSR_GPSR(IP5_7_4, RTS3_N_TANS), + PINMUX_IPSR_GPSR(IP5_7_4, HRTS3_N), + PINMUX_IPSR_MSEL(IP5_7_4, SDA6_B, SEL_I2C6_1), + PINMUX_IPSR_GPSR(IP5_7_4, CAN1_RX), + PINMUX_IPSR_GPSR(IP5_7_4, CANFD1_RX), + PINMUX_IPSR_MSEL(IP5_7_4, IERX_A, SEL_IEBUS_0), + + PINMUX_IPSR_MSEL(IP5_11_8, EX_WAIT0_A, SEL_LBSC_0), + PINMUX_IPSR_GPSR(IP5_11_8, QCLK), + PINMUX_IPSR_GPSR(IP5_11_8, VI4_CLK), + PINMUX_IPSR_GPSR(IP5_11_8, DU_DOTCLKOUT0), + + PINMUX_IPSR_GPSR(IP5_15_12, D0), + PINMUX_IPSR_MSEL(IP5_15_12, MSIOF2_SS1_B, SEL_MSIOF2_1), + PINMUX_IPSR_MSEL(IP5_15_12, MSIOF3_SCK_A, SEL_MSIOF3_0), + PINMUX_IPSR_GPSR(IP5_15_12, VI4_DATA16), + PINMUX_IPSR_GPSR(IP5_15_12, VI5_DATA0), + + PINMUX_IPSR_GPSR(IP5_19_16, D1), + PINMUX_IPSR_MSEL(IP5_19_16, MSIOF2_SS2_B, SEL_MSIOF2_1), + PINMUX_IPSR_MSEL(IP5_19_16, MSIOF3_SYNC_A, SEL_MSIOF3_0), + PINMUX_IPSR_GPSR(IP5_19_16, VI4_DATA17), + PINMUX_IPSR_GPSR(IP5_19_16, VI5_DATA1), + + PINMUX_IPSR_GPSR(IP5_23_20, D2), + PINMUX_IPSR_MSEL(IP5_23_20, MSIOF3_RXD_A, SEL_MSIOF3_0), + PINMUX_IPSR_GPSR(IP5_23_20, VI4_DATA18), + PINMUX_IPSR_GPSR(IP5_23_20, VI5_DATA2), + + PINMUX_IPSR_GPSR(IP5_27_24, D3), + PINMUX_IPSR_MSEL(IP5_27_24, MSIOF3_TXD_A, SEL_MSIOF3_0), + PINMUX_IPSR_GPSR(IP5_27_24, VI4_DATA19), + PINMUX_IPSR_GPSR(IP5_27_24, VI5_DATA3), + + PINMUX_IPSR_GPSR(IP5_31_28, D4), + PINMUX_IPSR_MSEL(IP5_31_28, MSIOF2_SCK_B, SEL_MSIOF2_1), + PINMUX_IPSR_GPSR(IP5_31_28, VI4_DATA20), + PINMUX_IPSR_GPSR(IP5_31_28, VI5_DATA4), + + /* IPSR6 */ + PINMUX_IPSR_GPSR(IP6_3_0, D5), + PINMUX_IPSR_MSEL(IP6_3_0, MSIOF2_SYNC_B, SEL_MSIOF2_1), + PINMUX_IPSR_GPSR(IP6_3_0, VI4_DATA21), + PINMUX_IPSR_GPSR(IP6_3_0, VI5_DATA5), + + PINMUX_IPSR_GPSR(IP6_7_4, D6), + PINMUX_IPSR_MSEL(IP6_7_4, MSIOF2_RXD_B, SEL_MSIOF2_1), + PINMUX_IPSR_GPSR(IP6_7_4, VI4_DATA22), + PINMUX_IPSR_GPSR(IP6_7_4, VI5_DATA6), + + PINMUX_IPSR_GPSR(IP6_11_8, D7), + PINMUX_IPSR_MSEL(IP6_11_8, MSIOF2_TXD_B, SEL_MSIOF2_1), + PINMUX_IPSR_GPSR(IP6_11_8, VI4_DATA23), + PINMUX_IPSR_GPSR(IP6_11_8, VI5_DATA7), + + PINMUX_IPSR_GPSR(IP6_15_12, D8), + PINMUX_IPSR_GPSR(IP6_15_12, LCDOUT0), + PINMUX_IPSR_MSEL(IP6_15_12, MSIOF2_SCK_D, SEL_MSIOF2_3), + PINMUX_IPSR_MSEL(IP6_15_12, SCK4_C, SEL_SCIF4_2), + PINMUX_IPSR_MSEL(IP6_15_12, VI4_DATA0_A, SEL_VIN4_0), + PINMUX_IPSR_GPSR(IP6_15_12, DU_DR0), + + PINMUX_IPSR_GPSR(IP6_19_16, D9), + PINMUX_IPSR_GPSR(IP6_19_16, LCDOUT1), + PINMUX_IPSR_MSEL(IP6_19_16, MSIOF2_SYNC_D, SEL_MSIOF2_3), + PINMUX_IPSR_MSEL(IP6_19_16, VI4_DATA1_A, SEL_VIN4_0), + PINMUX_IPSR_GPSR(IP6_19_16, DU_DR1), + + PINMUX_IPSR_GPSR(IP6_23_20, D10), + PINMUX_IPSR_GPSR(IP6_23_20, LCDOUT2), + PINMUX_IPSR_MSEL(IP6_23_20, MSIOF2_RXD_D, SEL_MSIOF2_3), + PINMUX_IPSR_MSEL(IP6_23_20, HRX3_B, SEL_HSCIF3_1), + PINMUX_IPSR_MSEL(IP6_23_20, VI4_DATA2_A, SEL_VIN4_0), + PINMUX_IPSR_MSEL(IP6_23_20, CTS4_N_C, SEL_SCIF4_2), + PINMUX_IPSR_GPSR(IP6_23_20, DU_DR2), + + PINMUX_IPSR_GPSR(IP6_27_24, D11), + PINMUX_IPSR_GPSR(IP6_27_24, LCDOUT3), + PINMUX_IPSR_MSEL(IP6_27_24, MSIOF2_TXD_D, SEL_MSIOF2_3), + PINMUX_IPSR_MSEL(IP6_27_24, HTX3_B, SEL_HSCIF3_1), + PINMUX_IPSR_MSEL(IP6_27_24, VI4_DATA3_A, SEL_VIN4_0), + PINMUX_IPSR_MSEL(IP6_27_24, RTS4_N_TANS_C, SEL_SCIF4_2), + PINMUX_IPSR_GPSR(IP6_27_24, DU_DR3), + + PINMUX_IPSR_GPSR(IP6_31_28, D12), + PINMUX_IPSR_GPSR(IP6_31_28, LCDOUT4), + PINMUX_IPSR_MSEL(IP6_31_28, MSIOF2_SS1_D, SEL_MSIOF2_3), + PINMUX_IPSR_MSEL(IP6_31_28, RX4_C, SEL_SCIF4_2), + PINMUX_IPSR_MSEL(IP6_31_28, VI4_DATA4_A, SEL_VIN4_0), + PINMUX_IPSR_GPSR(IP6_31_28, DU_DR4), + + /* IPSR7 */ + PINMUX_IPSR_GPSR(IP7_3_0, D13), + PINMUX_IPSR_GPSR(IP7_3_0, LCDOUT5), + PINMUX_IPSR_MSEL(IP7_3_0, MSIOF2_SS2_D, SEL_MSIOF2_3), + PINMUX_IPSR_MSEL(IP7_3_0, TX4_C, SEL_SCIF4_2), + PINMUX_IPSR_MSEL(IP7_3_0, VI4_DATA5_A, SEL_VIN4_0), + PINMUX_IPSR_GPSR(IP7_3_0, DU_DR5), + + PINMUX_IPSR_GPSR(IP7_7_4, D14), + PINMUX_IPSR_GPSR(IP7_7_4, LCDOUT6), + PINMUX_IPSR_MSEL(IP7_7_4, MSIOF3_SS1_A, SEL_MSIOF3_0), + PINMUX_IPSR_MSEL(IP7_7_4, HRX3_C, SEL_HSCIF3_2), + PINMUX_IPSR_MSEL(IP7_7_4, VI4_DATA6_A, SEL_VIN4_0), + PINMUX_IPSR_GPSR(IP7_7_4, DU_DR6), + PINMUX_IPSR_MSEL(IP7_7_4, SCL6_C, SEL_I2C6_2), + + PINMUX_IPSR_GPSR(IP7_11_8, D15), + PINMUX_IPSR_GPSR(IP7_11_8, LCDOUT7), + PINMUX_IPSR_MSEL(IP7_11_8, MSIOF3_SS2_A, SEL_MSIOF3_0), + PINMUX_IPSR_MSEL(IP7_11_8, HTX3_C, SEL_HSCIF3_2), + PINMUX_IPSR_MSEL(IP7_11_8, VI4_DATA7_A, SEL_VIN4_0), + PINMUX_IPSR_GPSR(IP7_11_8, DU_DR7), + PINMUX_IPSR_MSEL(IP7_11_8, SDA6_C, SEL_I2C6_2), + + PINMUX_IPSR_GPSR(IP7_15_12, FSCLKST), + + PINMUX_IPSR_GPSR(IP7_19_16, SD0_CLK), + PINMUX_IPSR_MSEL(IP7_19_16, MSIOF1_SCK_E, SEL_MSIOF1_4), + PINMUX_IPSR_MSEL(IP7_19_16, STP_OPWM_0_B, SEL_SSP1_0_1), + + PINMUX_IPSR_GPSR(IP7_23_20, SD0_CMD), + PINMUX_IPSR_MSEL(IP7_23_20, MSIOF1_SYNC_E, SEL_MSIOF1_4), + PINMUX_IPSR_MSEL(IP7_23_20, STP_IVCXO27_0_B, SEL_SSP1_0_1), + + PINMUX_IPSR_GPSR(IP7_27_24, SD0_DAT0), + PINMUX_IPSR_MSEL(IP7_27_24, MSIOF1_RXD_E, SEL_MSIOF1_4), + PINMUX_IPSR_MSEL(IP7_27_24, TS_SCK0_B, SEL_TSIF0_1), + PINMUX_IPSR_MSEL(IP7_27_24, STP_ISCLK_0_B, SEL_SSP1_0_1), + + PINMUX_IPSR_GPSR(IP7_31_28, SD0_DAT1), + PINMUX_IPSR_MSEL(IP7_31_28, MSIOF1_TXD_E, SEL_MSIOF1_4), + PINMUX_IPSR_MSEL(IP7_31_28, TS_SPSYNC0_B, SEL_TSIF0_1), + PINMUX_IPSR_MSEL(IP7_31_28, STP_ISSYNC_0_B, SEL_SSP1_0_1), + + /* IPSR8 */ + PINMUX_IPSR_GPSR(IP8_3_0, SD0_DAT2), + PINMUX_IPSR_MSEL(IP8_3_0, MSIOF1_SS1_E, SEL_MSIOF1_4), + PINMUX_IPSR_MSEL(IP8_3_0, TS_SDAT0_B, SEL_TSIF0_1), + PINMUX_IPSR_MSEL(IP8_3_0, STP_ISD_0_B, SEL_SSP1_0_1), + + PINMUX_IPSR_GPSR(IP8_7_4, SD0_DAT3), + PINMUX_IPSR_MSEL(IP8_7_4, MSIOF1_SS2_E, SEL_MSIOF1_4), + PINMUX_IPSR_MSEL(IP8_7_4, TS_SDEN0_B, SEL_TSIF0_1), + PINMUX_IPSR_MSEL(IP8_7_4, STP_ISEN_0_B, SEL_SSP1_0_1), + + PINMUX_IPSR_GPSR(IP8_11_8, SD1_CLK), + PINMUX_IPSR_MSEL(IP8_11_8, MSIOF1_SCK_G, SEL_MSIOF1_6), + PINMUX_IPSR_MSEL(IP8_11_8, SIM0_CLK_A, SEL_SIMCARD_0), + + PINMUX_IPSR_GPSR(IP8_15_12, SD1_CMD), + PINMUX_IPSR_MSEL(IP8_15_12, MSIOF1_SYNC_G, SEL_MSIOF1_6), + PINMUX_IPSR_MSEL(IP8_15_12, NFCE_N_B, SEL_NDF_1), + PINMUX_IPSR_MSEL(IP8_15_12, SIM0_D_A, SEL_SIMCARD_0), + PINMUX_IPSR_MSEL(IP8_15_12, STP_IVCXO27_1_B, SEL_SSP1_1_1), + + PINMUX_IPSR_GPSR(IP8_19_16, SD1_DAT0), + PINMUX_IPSR_GPSR(IP8_19_16, SD2_DAT4), + PINMUX_IPSR_MSEL(IP8_19_16, MSIOF1_RXD_G, SEL_MSIOF1_6), + PINMUX_IPSR_MSEL(IP8_19_16, NFWP_N_B, SEL_NDF_1), + PINMUX_IPSR_MSEL(IP8_19_16, TS_SCK1_B, SEL_TSIF1_1), + PINMUX_IPSR_MSEL(IP8_19_16, STP_ISCLK_1_B, SEL_SSP1_1_1), + + PINMUX_IPSR_GPSR(IP8_23_20, SD1_DAT1), + PINMUX_IPSR_GPSR(IP8_23_20, SD2_DAT5), + PINMUX_IPSR_MSEL(IP8_23_20, MSIOF1_TXD_G, SEL_MSIOF1_6), + PINMUX_IPSR_MSEL(IP8_23_20, NFDATA14_B, SEL_NDF_1), + PINMUX_IPSR_MSEL(IP8_23_20, TS_SPSYNC1_B, SEL_TSIF1_1), + PINMUX_IPSR_MSEL(IP8_23_20, STP_ISSYNC_1_B, SEL_SSP1_1_1), + + PINMUX_IPSR_GPSR(IP8_27_24, SD1_DAT2), + PINMUX_IPSR_GPSR(IP8_27_24, SD2_DAT6), + PINMUX_IPSR_MSEL(IP8_27_24, MSIOF1_SS1_G, SEL_MSIOF1_6), + PINMUX_IPSR_MSEL(IP8_27_24, NFDATA15_B, SEL_NDF_1), + PINMUX_IPSR_MSEL(IP8_27_24, TS_SDAT1_B, SEL_TSIF1_1), + PINMUX_IPSR_MSEL(IP8_27_24, STP_ISD_1_B, SEL_SSP1_1_1), + + PINMUX_IPSR_GPSR(IP8_31_28, SD1_DAT3), + PINMUX_IPSR_GPSR(IP8_31_28, SD2_DAT7), + PINMUX_IPSR_MSEL(IP8_31_28, MSIOF1_SS2_G, SEL_MSIOF1_6), + PINMUX_IPSR_MSEL(IP8_31_28, NFRB_N_B, SEL_NDF_1), + PINMUX_IPSR_MSEL(IP8_31_28, TS_SDEN1_B, SEL_TSIF1_1), + PINMUX_IPSR_MSEL(IP8_31_28, STP_ISEN_1_B, SEL_SSP1_1_1), + + /* IPSR9 */ + PINMUX_IPSR_GPSR(IP9_3_0, SD2_CLK), + PINMUX_IPSR_GPSR(IP9_3_0, NFDATA8), + + PINMUX_IPSR_GPSR(IP9_7_4, SD2_CMD), + PINMUX_IPSR_GPSR(IP9_7_4, NFDATA9), + + PINMUX_IPSR_GPSR(IP9_11_8, SD2_DAT0), + PINMUX_IPSR_GPSR(IP9_11_8, NFDATA10), + + PINMUX_IPSR_GPSR(IP9_15_12, SD2_DAT1), + PINMUX_IPSR_GPSR(IP9_15_12, NFDATA11), + + PINMUX_IPSR_GPSR(IP9_19_16, SD2_DAT2), + PINMUX_IPSR_GPSR(IP9_19_16, NFDATA12), + + PINMUX_IPSR_GPSR(IP9_23_20, SD2_DAT3), + PINMUX_IPSR_GPSR(IP9_23_20, NFDATA13), + + PINMUX_IPSR_GPSR(IP9_27_24, SD2_DS), + PINMUX_IPSR_GPSR(IP9_27_24, NFALE), + + PINMUX_IPSR_GPSR(IP9_31_28, SD3_CLK), + PINMUX_IPSR_GPSR(IP9_31_28, NFWE_N), + + /* IPSR10 */ + PINMUX_IPSR_GPSR(IP10_3_0, SD3_CMD), + PINMUX_IPSR_GPSR(IP10_3_0, NFRE_N), + + PINMUX_IPSR_GPSR(IP10_7_4, SD3_DAT0), + PINMUX_IPSR_GPSR(IP10_7_4, NFDATA0), + + PINMUX_IPSR_GPSR(IP10_11_8, SD3_DAT1), + PINMUX_IPSR_GPSR(IP10_11_8, NFDATA1), + + PINMUX_IPSR_GPSR(IP10_15_12, SD3_DAT2), + PINMUX_IPSR_GPSR(IP10_15_12, NFDATA2), + + PINMUX_IPSR_GPSR(IP10_19_16, SD3_DAT3), + PINMUX_IPSR_GPSR(IP10_19_16, NFDATA3), + + PINMUX_IPSR_GPSR(IP10_23_20, SD3_DAT4), + PINMUX_IPSR_MSEL(IP10_23_20, SD2_CD_A, SEL_SDHI2_0), + PINMUX_IPSR_GPSR(IP10_23_20, NFDATA4), + + PINMUX_IPSR_GPSR(IP10_27_24, SD3_DAT5), + PINMUX_IPSR_MSEL(IP10_27_24, SD2_WP_A, SEL_SDHI2_0), + PINMUX_IPSR_GPSR(IP10_27_24, NFDATA5), + + PINMUX_IPSR_GPSR(IP10_31_28, SD3_DAT6), + PINMUX_IPSR_GPSR(IP10_31_28, SD3_CD), + PINMUX_IPSR_GPSR(IP10_31_28, NFDATA6), + + /* IPSR11 */ + PINMUX_IPSR_GPSR(IP11_3_0, SD3_DAT7), + PINMUX_IPSR_GPSR(IP11_3_0, SD3_WP), + PINMUX_IPSR_GPSR(IP11_3_0, NFDATA7), + + PINMUX_IPSR_GPSR(IP11_7_4, SD3_DS), + PINMUX_IPSR_GPSR(IP11_7_4, NFCLE), + + PINMUX_IPSR_GPSR(IP11_11_8, SD0_CD), + PINMUX_IPSR_MSEL(IP11_11_8, SCL2_B, SEL_I2C2_1), + PINMUX_IPSR_MSEL(IP11_11_8, SIM0_RST_A, SEL_SIMCARD_0), + + PINMUX_IPSR_GPSR(IP11_15_12, SD0_WP), + PINMUX_IPSR_MSEL(IP11_15_12, SDA2_B, SEL_I2C2_1), + + PINMUX_IPSR_GPSR(IP11_19_16, SD1_CD), + PINMUX_IPSR_MSEL(IP11_19_16, SIM0_CLK_B, SEL_SIMCARD_1), + + PINMUX_IPSR_GPSR(IP11_23_20, SD1_WP), + PINMUX_IPSR_MSEL(IP11_23_20, SIM0_D_B, SEL_SIMCARD_1), + + PINMUX_IPSR_GPSR(IP11_27_24, SCK0), + PINMUX_IPSR_MSEL(IP11_27_24, HSCK1_B, SEL_HSCIF1_1), + PINMUX_IPSR_MSEL(IP11_27_24, MSIOF1_SS2_B, SEL_MSIOF1_1), + PINMUX_IPSR_MSEL(IP11_27_24, AUDIO_CLKC_B, SEL_ADG_C_1), + PINMUX_IPSR_MSEL(IP11_27_24, SDA2_A, SEL_I2C2_0), + PINMUX_IPSR_MSEL(IP11_27_24, SIM0_RST_B, SEL_SIMCARD_1), + PINMUX_IPSR_MSEL(IP11_27_24, STP_OPWM_0_C, SEL_SSP1_0_2), + PINMUX_IPSR_MSEL(IP11_27_24, RIF0_CLK_B, SEL_DRIF0_1), + PINMUX_IPSR_GPSR(IP11_27_24, ADICHS2), + PINMUX_IPSR_MSEL(IP11_27_24, SCK5_B, SEL_SCIF5_1), + + PINMUX_IPSR_GPSR(IP11_31_28, RX0), + PINMUX_IPSR_MSEL(IP11_31_28, HRX1_B, SEL_HSCIF1_1), + PINMUX_IPSR_MSEL(IP11_31_28, TS_SCK0_C, SEL_TSIF0_2), + PINMUX_IPSR_MSEL(IP11_31_28, STP_ISCLK_0_C, SEL_SSP1_0_2), + PINMUX_IPSR_MSEL(IP11_31_28, RIF0_D0_B, SEL_DRIF0_1), + + /* IPSR12 */ + PINMUX_IPSR_GPSR(IP12_3_0, TX0), + PINMUX_IPSR_MSEL(IP12_3_0, HTX1_B, SEL_HSCIF1_1), + PINMUX_IPSR_MSEL(IP12_3_0, TS_SPSYNC0_C, SEL_TSIF0_2), + PINMUX_IPSR_MSEL(IP12_3_0, STP_ISSYNC_0_C, SEL_SSP1_0_2), + PINMUX_IPSR_MSEL(IP12_3_0, RIF0_D1_B, SEL_DRIF0_1), + + PINMUX_IPSR_GPSR(IP12_7_4, CTS0_N), + PINMUX_IPSR_MSEL(IP12_7_4, HCTS1_N_B, SEL_HSCIF1_1), + PINMUX_IPSR_MSEL(IP12_7_4, MSIOF1_SYNC_B, SEL_MSIOF1_1), + PINMUX_IPSR_MSEL(IP12_7_4, TS_SPSYNC1_C, SEL_TSIF1_2), + PINMUX_IPSR_MSEL(IP12_7_4, STP_ISSYNC_1_C, SEL_SSP1_1_2), + PINMUX_IPSR_MSEL(IP12_7_4, RIF1_SYNC_B, SEL_DRIF1_1), + PINMUX_IPSR_GPSR(IP12_7_4, AUDIO_CLKOUT_C), + PINMUX_IPSR_GPSR(IP12_7_4, ADICS_SAMP), + + PINMUX_IPSR_GPSR(IP12_11_8, RTS0_N_TANS), + PINMUX_IPSR_MSEL(IP12_11_8, HRTS1_N_B, SEL_HSCIF1_1), + PINMUX_IPSR_MSEL(IP12_11_8, MSIOF1_SS1_B, SEL_MSIOF1_1), + PINMUX_IPSR_MSEL(IP12_11_8, AUDIO_CLKA_B, SEL_ADG_A_1), + PINMUX_IPSR_MSEL(IP12_11_8, SCL2_A, SEL_I2C2_0), + PINMUX_IPSR_MSEL(IP12_11_8, STP_IVCXO27_1_C, SEL_SSP1_1_2), + PINMUX_IPSR_MSEL(IP12_11_8, RIF0_SYNC_B, SEL_DRIF0_1), + PINMUX_IPSR_MSEL(IP12_11_8, FSO_TOE_A, SEL_FSO_0), + PINMUX_IPSR_GPSR(IP12_11_8, ADICHS1), + + PINMUX_IPSR_MSEL(IP12_15_12, RX1_A, SEL_SCIF1_0), + PINMUX_IPSR_MSEL(IP12_15_12, HRX1_A, SEL_HSCIF1_0), + PINMUX_IPSR_MSEL(IP12_15_12, TS_SDAT0_C, SEL_TSIF0_2), + PINMUX_IPSR_MSEL(IP12_15_12, STP_ISD_0_C, SEL_SSP1_0_2), + PINMUX_IPSR_MSEL(IP12_15_12, RIF1_CLK_C, SEL_DRIF1_2), + + PINMUX_IPSR_MSEL(IP12_19_16, TX1_A, SEL_SCIF1_0), + PINMUX_IPSR_MSEL(IP12_19_16, HTX1_A, SEL_HSCIF1_0), + PINMUX_IPSR_MSEL(IP12_19_16, TS_SDEN0_C, SEL_TSIF0_2), + PINMUX_IPSR_MSEL(IP12_19_16, STP_ISEN_0_C, SEL_SSP1_0_2), + PINMUX_IPSR_MSEL(IP12_19_16, RIF1_D0_C, SEL_DRIF1_2), + + PINMUX_IPSR_GPSR(IP12_23_20, CTS1_N), + PINMUX_IPSR_MSEL(IP12_23_20, HCTS1_N_A, SEL_HSCIF1_0), + PINMUX_IPSR_MSEL(IP12_23_20, MSIOF1_RXD_B, SEL_MSIOF1_1), + PINMUX_IPSR_MSEL(IP12_23_20, TS_SDEN1_C, SEL_TSIF1_2), + PINMUX_IPSR_MSEL(IP12_23_20, STP_ISEN_1_C, SEL_SSP1_1_2), + PINMUX_IPSR_MSEL(IP12_23_20, RIF1_D0_B, SEL_DRIF1_1), + PINMUX_IPSR_GPSR(IP12_23_20, ADIDATA), + + PINMUX_IPSR_GPSR(IP12_27_24, RTS1_N_TANS), + PINMUX_IPSR_MSEL(IP12_27_24, HRTS1_N_A, SEL_HSCIF1_0), + PINMUX_IPSR_MSEL(IP12_27_24, MSIOF1_TXD_B, SEL_MSIOF1_1), + PINMUX_IPSR_MSEL(IP12_27_24, TS_SDAT1_C, SEL_TSIF1_2), + PINMUX_IPSR_MSEL(IP12_27_24, STP_ISD_1_C, SEL_SSP1_1_2), + PINMUX_IPSR_MSEL(IP12_27_24, RIF1_D1_B, SEL_DRIF1_1), + PINMUX_IPSR_GPSR(IP12_27_24, ADICHS0), + + PINMUX_IPSR_GPSR(IP12_31_28, SCK2), + PINMUX_IPSR_MSEL(IP12_31_28, SCIF_CLK_B, SEL_SCIF1_1), + PINMUX_IPSR_MSEL(IP12_31_28, MSIOF1_SCK_B, SEL_MSIOF1_1), + PINMUX_IPSR_MSEL(IP12_31_28, TS_SCK1_C, SEL_TSIF1_2), + PINMUX_IPSR_MSEL(IP12_31_28, STP_ISCLK_1_C, SEL_SSP1_1_2), + PINMUX_IPSR_MSEL(IP12_31_28, RIF1_CLK_B, SEL_DRIF1_1), + PINMUX_IPSR_GPSR(IP12_31_28, ADICLK), + + /* IPSR13 */ + PINMUX_IPSR_MSEL(IP13_3_0, TX2_A, SEL_SCIF2_0), + PINMUX_IPSR_MSEL(IP13_3_0, SD2_CD_B, SEL_SDHI2_1), + PINMUX_IPSR_MSEL(IP13_3_0, SCL1_A, SEL_I2C1_0), + PINMUX_IPSR_MSEL(IP13_3_0, FMCLK_A, SEL_FM_0), + PINMUX_IPSR_MSEL(IP13_3_0, RIF1_D1_C, SEL_DRIF1_2), + PINMUX_IPSR_MSEL(IP13_3_0, FSO_CFE_0_B, SEL_FSO_1), + + PINMUX_IPSR_MSEL(IP13_7_4, RX2_A, SEL_SCIF2_0), + PINMUX_IPSR_MSEL(IP13_7_4, SD2_WP_B, SEL_SDHI2_1), + PINMUX_IPSR_MSEL(IP13_7_4, SDA1_A, SEL_I2C1_0), + PINMUX_IPSR_MSEL(IP13_7_4, FMIN_A, SEL_FM_0), + PINMUX_IPSR_MSEL(IP13_7_4, RIF1_SYNC_C, SEL_DRIF1_2), + PINMUX_IPSR_MSEL(IP13_7_4, FSO_CFE_1_B, SEL_FSO_1), + + PINMUX_IPSR_GPSR(IP13_11_8, HSCK0), + PINMUX_IPSR_MSEL(IP13_11_8, MSIOF1_SCK_D, SEL_MSIOF1_3), + PINMUX_IPSR_MSEL(IP13_11_8, AUDIO_CLKB_A, SEL_ADG_B_0), + PINMUX_IPSR_MSEL(IP13_11_8, SSI_SDATA1_B, SEL_SSI_1), + PINMUX_IPSR_MSEL(IP13_11_8, TS_SCK0_D, SEL_TSIF0_3), + PINMUX_IPSR_MSEL(IP13_11_8, STP_ISCLK_0_D, SEL_SSP1_0_3), + PINMUX_IPSR_MSEL(IP13_11_8, RIF0_CLK_C, SEL_DRIF0_2), + PINMUX_IPSR_MSEL(IP13_11_8, RX5_B, SEL_SCIF5_1), + + PINMUX_IPSR_GPSR(IP13_15_12, HRX0), + PINMUX_IPSR_MSEL(IP13_15_12, MSIOF1_RXD_D, SEL_MSIOF1_3), + PINMUX_IPSR_MSEL(IP13_15_12, SSI_SDATA2_B, SEL_SSI_1), + PINMUX_IPSR_MSEL(IP13_15_12, TS_SDEN0_D, SEL_TSIF0_3), + PINMUX_IPSR_MSEL(IP13_15_12, STP_ISEN_0_D, SEL_SSP1_0_3), + PINMUX_IPSR_MSEL(IP13_15_12, RIF0_D0_C, SEL_DRIF0_2), + + PINMUX_IPSR_GPSR(IP13_19_16, HTX0), + PINMUX_IPSR_MSEL(IP13_19_16, MSIOF1_TXD_D, SEL_MSIOF1_3), + PINMUX_IPSR_MSEL(IP13_19_16, SSI_SDATA9_B, SEL_SSI_1), + PINMUX_IPSR_MSEL(IP13_19_16, TS_SDAT0_D, SEL_TSIF0_3), + PINMUX_IPSR_MSEL(IP13_19_16, STP_ISD_0_D, SEL_SSP1_0_3), + PINMUX_IPSR_MSEL(IP13_19_16, RIF0_D1_C, SEL_DRIF0_2), + + PINMUX_IPSR_GPSR(IP13_23_20, HCTS0_N), + PINMUX_IPSR_MSEL(IP13_23_20, RX2_B, SEL_SCIF2_1), + PINMUX_IPSR_MSEL(IP13_23_20, MSIOF1_SYNC_D, SEL_MSIOF1_3), + PINMUX_IPSR_MSEL(IP13_23_20, SSI_SCK9_A, SEL_SSI_0), + PINMUX_IPSR_MSEL(IP13_23_20, TS_SPSYNC0_D, SEL_TSIF0_3), + PINMUX_IPSR_MSEL(IP13_23_20, STP_ISSYNC_0_D, SEL_SSP1_0_3), + PINMUX_IPSR_MSEL(IP13_23_20, RIF0_SYNC_C, SEL_DRIF0_2), + PINMUX_IPSR_GPSR(IP13_23_20, AUDIO_CLKOUT1_A), + + PINMUX_IPSR_GPSR(IP13_27_24, HRTS0_N), + PINMUX_IPSR_MSEL(IP13_27_24, TX2_B, SEL_SCIF2_1), + PINMUX_IPSR_MSEL(IP13_27_24, MSIOF1_SS1_D, SEL_MSIOF1_3), + PINMUX_IPSR_MSEL(IP13_27_24, SSI_WS9_A, SEL_SSI_0), + PINMUX_IPSR_MSEL(IP13_27_24, STP_IVCXO27_0_D, SEL_SSP1_0_3), + PINMUX_IPSR_MSEL(IP13_27_24, BPFCLK_A, SEL_FM_0), + PINMUX_IPSR_GPSR(IP13_27_24, AUDIO_CLKOUT2_A), + + PINMUX_IPSR_GPSR(IP13_31_28, MSIOF0_SYNC), + PINMUX_IPSR_GPSR(IP13_31_28, AUDIO_CLKOUT_A), + PINMUX_IPSR_MSEL(IP13_31_28, TX5_B, SEL_SCIF5_1), + PINMUX_IPSR_MSEL(IP13_31_28, BPFCLK_D, SEL_FM_3), + + /* IPSR14 */ + PINMUX_IPSR_GPSR(IP14_3_0, MSIOF0_SS1), + PINMUX_IPSR_MSEL(IP14_3_0, RX5_A, SEL_SCIF5_0), + PINMUX_IPSR_MSEL(IP14_3_0, NFWP_N_A, SEL_NDF_0), + PINMUX_IPSR_MSEL(IP14_3_0, AUDIO_CLKA_C, SEL_ADG_A_2), + PINMUX_IPSR_MSEL(IP14_3_0, SSI_SCK2_A, SEL_SSI_0), + PINMUX_IPSR_MSEL(IP14_3_0, STP_IVCXO27_0_C, SEL_SSP1_0_2), + PINMUX_IPSR_GPSR(IP14_3_0, AUDIO_CLKOUT3_A), + PINMUX_IPSR_MSEL(IP14_3_0, TCLK1_B, SEL_TIMER_TMU_1), + + PINMUX_IPSR_GPSR(IP14_7_4, MSIOF0_SS2), + PINMUX_IPSR_MSEL(IP14_7_4, TX5_A, SEL_SCIF5_0), + PINMUX_IPSR_MSEL(IP14_7_4, MSIOF1_SS2_D, SEL_MSIOF1_3), + PINMUX_IPSR_MSEL(IP14_7_4, AUDIO_CLKC_A, SEL_ADG_C_0), + PINMUX_IPSR_MSEL(IP14_7_4, SSI_WS2_A, SEL_SSI_0), + PINMUX_IPSR_MSEL(IP14_7_4, STP_OPWM_0_D, SEL_SSP1_0_3), + PINMUX_IPSR_GPSR(IP14_7_4, AUDIO_CLKOUT_D), + PINMUX_IPSR_MSEL(IP14_7_4, SPEEDIN_B, SEL_SPEED_PULSE_1), + + PINMUX_IPSR_GPSR(IP14_11_8, MLB_CLK), + PINMUX_IPSR_MSEL(IP14_11_8, MSIOF1_SCK_F, SEL_MSIOF1_5), + PINMUX_IPSR_MSEL(IP14_11_8, SCL1_B, SEL_I2C1_1), + + PINMUX_IPSR_GPSR(IP14_15_12, MLB_SIG), + PINMUX_IPSR_MSEL(IP14_15_12, RX1_B, SEL_SCIF1_1), + PINMUX_IPSR_MSEL(IP14_15_12, MSIOF1_SYNC_F, SEL_MSIOF1_5), + PINMUX_IPSR_MSEL(IP14_15_12, SDA1_B, SEL_I2C1_1), + + PINMUX_IPSR_GPSR(IP14_19_16, MLB_DAT), + PINMUX_IPSR_MSEL(IP14_19_16, TX1_B, SEL_SCIF1_1), + PINMUX_IPSR_MSEL(IP14_19_16, MSIOF1_RXD_F, SEL_MSIOF1_5), + + PINMUX_IPSR_GPSR(IP14_23_20, SSI_SCK0129), + PINMUX_IPSR_MSEL(IP14_23_20, MSIOF1_TXD_F, SEL_MSIOF1_5), + + PINMUX_IPSR_GPSR(IP14_27_24, SSI_WS0129), + PINMUX_IPSR_MSEL(IP14_27_24, MSIOF1_SS1_F, SEL_MSIOF1_5), + + PINMUX_IPSR_GPSR(IP14_31_28, SSI_SDATA0), + PINMUX_IPSR_MSEL(IP14_31_28, MSIOF1_SS2_F, SEL_MSIOF1_5), + + /* IPSR15 */ + PINMUX_IPSR_MSEL(IP15_3_0, SSI_SDATA1_A, SEL_SSI_0), + + PINMUX_IPSR_MSEL(IP15_7_4, SSI_SDATA2_A, SEL_SSI_0), + PINMUX_IPSR_MSEL(IP15_7_4, SSI_SCK1_B, SEL_SSI_1), + + PINMUX_IPSR_GPSR(IP15_11_8, SSI_SCK34), + PINMUX_IPSR_MSEL(IP15_11_8, MSIOF1_SS1_A, SEL_MSIOF1_0), + PINMUX_IPSR_MSEL(IP15_11_8, STP_OPWM_0_A, SEL_SSP1_0_0), + + PINMUX_IPSR_GPSR(IP15_15_12, SSI_WS34), + PINMUX_IPSR_MSEL(IP15_15_12, HCTS2_N_A, SEL_HSCIF2_0), + PINMUX_IPSR_MSEL(IP15_15_12, MSIOF1_SS2_A, SEL_MSIOF1_0), + PINMUX_IPSR_MSEL(IP15_15_12, STP_IVCXO27_0_A, SEL_SSP1_0_0), + + PINMUX_IPSR_GPSR(IP15_19_16, SSI_SDATA3), + PINMUX_IPSR_MSEL(IP15_19_16, HRTS2_N_A, SEL_HSCIF2_0), + PINMUX_IPSR_MSEL(IP15_19_16, MSIOF1_TXD_A, SEL_MSIOF1_0), + PINMUX_IPSR_MSEL(IP15_19_16, TS_SCK0_A, SEL_TSIF0_0), + PINMUX_IPSR_MSEL(IP15_19_16, STP_ISCLK_0_A, SEL_SSP1_0_0), + PINMUX_IPSR_MSEL(IP15_19_16, RIF0_D1_A, SEL_DRIF0_0), + PINMUX_IPSR_MSEL(IP15_19_16, RIF2_D0_A, SEL_DRIF2_0), + + PINMUX_IPSR_GPSR(IP15_23_20, SSI_SCK4), + PINMUX_IPSR_MSEL(IP15_23_20, HRX2_A, SEL_HSCIF2_0), + PINMUX_IPSR_MSEL(IP15_23_20, MSIOF1_SCK_A, SEL_MSIOF1_0), + PINMUX_IPSR_MSEL(IP15_23_20, TS_SDAT0_A, SEL_TSIF0_0), + PINMUX_IPSR_MSEL(IP15_23_20, STP_ISD_0_A, SEL_SSP1_0_0), + PINMUX_IPSR_MSEL(IP15_23_20, RIF0_CLK_A, SEL_DRIF0_0), + PINMUX_IPSR_MSEL(IP15_23_20, RIF2_CLK_A, SEL_DRIF2_0), + + PINMUX_IPSR_GPSR(IP15_27_24, SSI_WS4), + PINMUX_IPSR_MSEL(IP15_27_24, HTX2_A, SEL_HSCIF2_0), + PINMUX_IPSR_MSEL(IP15_27_24, MSIOF1_SYNC_A, SEL_MSIOF1_0), + PINMUX_IPSR_MSEL(IP15_27_24, TS_SDEN0_A, SEL_TSIF0_0), + PINMUX_IPSR_MSEL(IP15_27_24, STP_ISEN_0_A, SEL_SSP1_0_0), + PINMUX_IPSR_MSEL(IP15_27_24, RIF0_SYNC_A, SEL_DRIF0_0), + PINMUX_IPSR_MSEL(IP15_27_24, RIF2_SYNC_A, SEL_DRIF2_0), + + PINMUX_IPSR_GPSR(IP15_31_28, SSI_SDATA4), + PINMUX_IPSR_MSEL(IP15_31_28, HSCK2_A, SEL_HSCIF2_0), + PINMUX_IPSR_MSEL(IP15_31_28, MSIOF1_RXD_A, SEL_MSIOF1_0), + PINMUX_IPSR_MSEL(IP15_31_28, TS_SPSYNC0_A, SEL_TSIF0_0), + PINMUX_IPSR_MSEL(IP15_31_28, STP_ISSYNC_0_A, SEL_SSP1_0_0), + PINMUX_IPSR_MSEL(IP15_31_28, RIF0_D0_A, SEL_DRIF0_0), + PINMUX_IPSR_MSEL(IP15_31_28, RIF2_D1_A, SEL_DRIF2_0), + + /* IPSR16 */ + PINMUX_IPSR_GPSR(IP16_3_0, SSI_SCK6), + PINMUX_IPSR_MSEL(IP16_3_0, SIM0_RST_D, SEL_SIMCARD_3), + + PINMUX_IPSR_GPSR(IP16_7_4, SSI_WS6), + PINMUX_IPSR_MSEL(IP16_7_4, SIM0_D_D, SEL_SIMCARD_3), + + PINMUX_IPSR_GPSR(IP16_11_8, SSI_SDATA6), + PINMUX_IPSR_MSEL(IP16_11_8, SIM0_CLK_D, SEL_SIMCARD_3), + + PINMUX_IPSR_GPSR(IP16_15_12, SSI_SCK78), + PINMUX_IPSR_MSEL(IP16_15_12, HRX2_B, SEL_HSCIF2_1), + PINMUX_IPSR_MSEL(IP16_15_12, MSIOF1_SCK_C, SEL_MSIOF1_2), + PINMUX_IPSR_MSEL(IP16_15_12, TS_SCK1_A, SEL_TSIF1_0), + PINMUX_IPSR_MSEL(IP16_15_12, STP_ISCLK_1_A, SEL_SSP1_1_0), + PINMUX_IPSR_MSEL(IP16_15_12, RIF1_CLK_A, SEL_DRIF1_0), + PINMUX_IPSR_MSEL(IP16_15_12, RIF3_CLK_A, SEL_DRIF3_0), + + PINMUX_IPSR_GPSR(IP16_19_16, SSI_WS78), + PINMUX_IPSR_MSEL(IP16_19_16, HTX2_B, SEL_HSCIF2_1), + PINMUX_IPSR_MSEL(IP16_19_16, MSIOF1_SYNC_C, SEL_MSIOF1_2), + PINMUX_IPSR_MSEL(IP16_19_16, TS_SDAT1_A, SEL_TSIF1_0), + PINMUX_IPSR_MSEL(IP16_19_16, STP_ISD_1_A, SEL_SSP1_1_0), + PINMUX_IPSR_MSEL(IP16_19_16, RIF1_SYNC_A, SEL_DRIF1_0), + PINMUX_IPSR_MSEL(IP16_19_16, RIF3_SYNC_A, SEL_DRIF3_0), + + PINMUX_IPSR_GPSR(IP16_23_20, SSI_SDATA7), + PINMUX_IPSR_MSEL(IP16_23_20, HCTS2_N_B, SEL_HSCIF2_1), + PINMUX_IPSR_MSEL(IP16_23_20, MSIOF1_RXD_C, SEL_MSIOF1_2), + PINMUX_IPSR_MSEL(IP16_23_20, TS_SDEN1_A, SEL_TSIF1_0), + PINMUX_IPSR_MSEL(IP16_23_20, STP_ISEN_1_A, SEL_SSP1_1_0), + PINMUX_IPSR_MSEL(IP16_23_20, RIF1_D0_A, SEL_DRIF1_0), + PINMUX_IPSR_MSEL(IP16_23_20, RIF3_D0_A, SEL_DRIF3_0), + PINMUX_IPSR_MSEL(IP16_23_20, TCLK2_A, SEL_TIMER_TMU_0), + + PINMUX_IPSR_GPSR(IP16_27_24, SSI_SDATA8), + PINMUX_IPSR_MSEL(IP16_27_24, HRTS2_N_B, SEL_HSCIF2_1), + PINMUX_IPSR_MSEL(IP16_27_24, MSIOF1_TXD_C, SEL_MSIOF1_2), + PINMUX_IPSR_MSEL(IP16_27_24, TS_SPSYNC1_A, SEL_TSIF1_0), + PINMUX_IPSR_MSEL(IP16_27_24, STP_ISSYNC_1_A, SEL_SSP1_1_0), + PINMUX_IPSR_MSEL(IP16_27_24, RIF1_D1_A, SEL_DRIF1_0), + PINMUX_IPSR_MSEL(IP16_27_24, RIF3_D1_A, SEL_DRIF3_0), + + PINMUX_IPSR_MSEL(IP16_31_28, SSI_SDATA9_A, SEL_SSI_0), + PINMUX_IPSR_MSEL(IP16_31_28, HSCK2_B, SEL_HSCIF2_1), + PINMUX_IPSR_MSEL(IP16_31_28, MSIOF1_SS1_C, SEL_MSIOF1_2), + PINMUX_IPSR_MSEL(IP16_31_28, HSCK1_A, SEL_HSCIF1_0), + PINMUX_IPSR_MSEL(IP16_31_28, SSI_WS1_B, SEL_SSI_1), + PINMUX_IPSR_GPSR(IP16_31_28, SCK1), + PINMUX_IPSR_MSEL(IP16_31_28, STP_IVCXO27_1_A, SEL_SSP1_1_0), + PINMUX_IPSR_GPSR(IP16_31_28, SCK5_A), + + /* IPSR17 */ + PINMUX_IPSR_MSEL(IP17_3_0, AUDIO_CLKA_A, SEL_ADG_A_0), + PINMUX_IPSR_GPSR(IP17_3_0, CC5_OSCOUT), + + PINMUX_IPSR_MSEL(IP17_7_4, AUDIO_CLKB_B, SEL_ADG_B_1), + PINMUX_IPSR_MSEL(IP17_7_4, SCIF_CLK_A, SEL_SCIF1_0), + PINMUX_IPSR_MSEL(IP17_7_4, STP_IVCXO27_1_D, SEL_SSP1_1_3), + PINMUX_IPSR_MSEL(IP17_7_4, REMOCON_A, SEL_REMOCON_0), + PINMUX_IPSR_MSEL(IP17_7_4, TCLK1_A, SEL_TIMER_TMU_0), + + PINMUX_IPSR_GPSR(IP17_11_8, USB0_PWEN), + PINMUX_IPSR_MSEL(IP17_11_8, SIM0_RST_C, SEL_SIMCARD_2), + PINMUX_IPSR_MSEL(IP17_11_8, TS_SCK1_D, SEL_TSIF1_3), + PINMUX_IPSR_MSEL(IP17_11_8, STP_ISCLK_1_D, SEL_SSP1_1_3), + PINMUX_IPSR_MSEL(IP17_11_8, BPFCLK_B, SEL_FM_1), + PINMUX_IPSR_MSEL(IP17_11_8, RIF3_CLK_B, SEL_DRIF3_1), + PINMUX_IPSR_MSEL(IP17_11_8, HSCK2_C, SEL_HSCIF2_2), + + PINMUX_IPSR_GPSR(IP17_15_12, USB0_OVC), + PINMUX_IPSR_MSEL(IP17_15_12, SIM0_D_C, SEL_SIMCARD_2), + PINMUX_IPSR_MSEL(IP17_15_12, TS_SDAT1_D, SEL_TSIF1_3), + PINMUX_IPSR_MSEL(IP17_15_12, STP_ISD_1_D, SEL_SSP1_1_3), + PINMUX_IPSR_MSEL(IP17_15_12, RIF3_SYNC_B, SEL_DRIF3_1), + PINMUX_IPSR_MSEL(IP17_15_12, HRX2_C, SEL_HSCIF2_2), + + PINMUX_IPSR_GPSR(IP17_19_16, USB1_PWEN), + PINMUX_IPSR_MSEL(IP17_19_16, SIM0_CLK_C, SEL_SIMCARD_2), + PINMUX_IPSR_MSEL(IP17_19_16, SSI_SCK1_A, SEL_SSI_0), + PINMUX_IPSR_MSEL(IP17_19_16, TS_SCK0_E, SEL_TSIF0_4), + PINMUX_IPSR_MSEL(IP17_19_16, STP_ISCLK_0_E, SEL_SSP1_0_4), + PINMUX_IPSR_MSEL(IP17_19_16, FMCLK_B, SEL_FM_1), + PINMUX_IPSR_MSEL(IP17_19_16, RIF2_CLK_B, SEL_DRIF2_1), + PINMUX_IPSR_MSEL(IP17_19_16, SPEEDIN_A, SEL_SPEED_PULSE_0), + PINMUX_IPSR_MSEL(IP17_19_16, HTX2_C, SEL_HSCIF2_2), + + PINMUX_IPSR_GPSR(IP17_23_20, USB1_OVC), + PINMUX_IPSR_MSEL(IP17_23_20, MSIOF1_SS2_C, SEL_MSIOF1_2), + PINMUX_IPSR_MSEL(IP17_23_20, SSI_WS1_A, SEL_SSI_0), + PINMUX_IPSR_MSEL(IP17_23_20, TS_SDAT0_E, SEL_TSIF0_4), + PINMUX_IPSR_MSEL(IP17_23_20, STP_ISD_0_E, SEL_SSP1_0_4), + PINMUX_IPSR_MSEL(IP17_23_20, FMIN_B, SEL_FM_1), + PINMUX_IPSR_MSEL(IP17_23_20, RIF2_SYNC_B, SEL_DRIF2_1), + PINMUX_IPSR_MSEL(IP17_23_20, REMOCON_B, SEL_REMOCON_1), + PINMUX_IPSR_MSEL(IP17_23_20, HCTS2_N_C, SEL_HSCIF2_2), + + PINMUX_IPSR_GPSR(IP17_27_24, USB30_PWEN), + PINMUX_IPSR_GPSR(IP17_27_24, AUDIO_CLKOUT_B), + PINMUX_IPSR_MSEL(IP17_27_24, SSI_SCK2_B, SEL_SSI_1), + PINMUX_IPSR_MSEL(IP17_27_24, TS_SDEN1_D, SEL_TSIF1_3), + PINMUX_IPSR_MSEL(IP17_27_24, STP_ISEN_1_D, SEL_SSP1_1_2), + PINMUX_IPSR_MSEL(IP17_27_24, STP_OPWM_0_E, SEL_SSP1_0_4), + PINMUX_IPSR_MSEL(IP17_27_24, RIF3_D0_B, SEL_DRIF3_1), + PINMUX_IPSR_MSEL(IP17_27_24, TCLK2_B, SEL_TIMER_TMU_1), + PINMUX_IPSR_GPSR(IP17_27_24, TPU0TO0), + PINMUX_IPSR_MSEL(IP17_27_24, BPFCLK_C, SEL_FM_2), + PINMUX_IPSR_MSEL(IP17_27_24, HRTS2_N_C, SEL_HSCIF2_2), + + PINMUX_IPSR_GPSR(IP17_31_28, USB30_OVC), + PINMUX_IPSR_GPSR(IP17_31_28, AUDIO_CLKOUT1_B), + PINMUX_IPSR_MSEL(IP17_31_28, SSI_WS2_B, SEL_SSI_1), + PINMUX_IPSR_MSEL(IP17_31_28, TS_SPSYNC1_D, SEL_TSIF1_3), + PINMUX_IPSR_MSEL(IP17_31_28, STP_ISSYNC_1_D, SEL_SSP1_1_3), + PINMUX_IPSR_MSEL(IP17_31_28, STP_IVCXO27_0_E, SEL_SSP1_0_4), + PINMUX_IPSR_MSEL(IP17_31_28, RIF3_D1_B, SEL_DRIF3_1), + PINMUX_IPSR_MSEL(IP17_31_28, FSO_TOE_B, SEL_FSO_1), + PINMUX_IPSR_GPSR(IP17_31_28, TPU0TO1), + + /* IPSR18 */ + PINMUX_IPSR_GPSR(IP18_3_0, GP6_30), + PINMUX_IPSR_GPSR(IP18_3_0, AUDIO_CLKOUT2_B), + PINMUX_IPSR_MSEL(IP18_3_0, SSI_SCK9_B, SEL_SSI_1), + PINMUX_IPSR_MSEL(IP18_3_0, TS_SDEN0_E, SEL_TSIF0_4), + PINMUX_IPSR_MSEL(IP18_3_0, STP_ISEN_0_E, SEL_SSP1_0_4), + PINMUX_IPSR_MSEL(IP18_3_0, RIF2_D0_B, SEL_DRIF2_1), + PINMUX_IPSR_GPSR(IP18_3_0, TPU0TO2), + PINMUX_IPSR_MSEL(IP18_3_0, FSO_CFE_0_A, SEL_FSO_0), + PINMUX_IPSR_MSEL(IP18_3_0, FMCLK_C, SEL_FM_2), + PINMUX_IPSR_MSEL(IP18_3_0, FMCLK_D, SEL_FM_3), + + PINMUX_IPSR_GPSR(IP18_7_4, GP6_31), + PINMUX_IPSR_GPSR(IP18_7_4, AUDIO_CLKOUT3_B), + PINMUX_IPSR_MSEL(IP18_7_4, SSI_WS9_B, SEL_SSI_1), + PINMUX_IPSR_MSEL(IP18_7_4, TS_SPSYNC0_E, SEL_TSIF0_4), + PINMUX_IPSR_MSEL(IP18_7_4, STP_ISSYNC_0_E, SEL_SSP1_0_4), + PINMUX_IPSR_MSEL(IP18_7_4, RIF2_D1_B, SEL_DRIF2_1), + PINMUX_IPSR_GPSR(IP18_7_4, TPU0TO3), + PINMUX_IPSR_MSEL(IP18_7_4, FSO_CFE_1_A, SEL_FSO_0), + PINMUX_IPSR_MSEL(IP18_7_4, FMIN_C, SEL_FM_2), + PINMUX_IPSR_MSEL(IP18_7_4, FMIN_D, SEL_FM_3), + + /* I2C */ + PINMUX_IPSR_NOGP(0, I2C_SEL_0_1), + PINMUX_IPSR_NOGP(0, I2C_SEL_3_1), + PINMUX_IPSR_NOGP(0, I2C_SEL_5_1), +}; + +static const struct sh_pfc_pin pinmux_pins[] = { + PINMUX_GPIO_GP_ALL(), +}; + +static const struct sh_pfc_pin_group pinmux_groups[] = { +}; + +static const struct sh_pfc_function pinmux_functions[] = { +}; + +static const struct pinmux_cfg_reg pinmux_config_regs[] = { +#define F_(x, y) FN_##y +#define FM(x) FN_##x + { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1) { + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + GP_0_15_FN, GPSR0_15, + GP_0_14_FN, GPSR0_14, + GP_0_13_FN, GPSR0_13, + GP_0_12_FN, GPSR0_12, + GP_0_11_FN, GPSR0_11, + GP_0_10_FN, GPSR0_10, + GP_0_9_FN, GPSR0_9, + GP_0_8_FN, GPSR0_8, + GP_0_7_FN, GPSR0_7, + GP_0_6_FN, GPSR0_6, + GP_0_5_FN, GPSR0_5, + GP_0_4_FN, GPSR0_4, + GP_0_3_FN, GPSR0_3, + GP_0_2_FN, GPSR0_2, + GP_0_1_FN, GPSR0_1, + GP_0_0_FN, GPSR0_0, } + }, + { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1) { + 0, 0, + 0, 0, + 0, 0, + GP_1_28_FN, GPSR1_28, + GP_1_27_FN, GPSR1_27, + GP_1_26_FN, GPSR1_26, + GP_1_25_FN, GPSR1_25, + GP_1_24_FN, GPSR1_24, + GP_1_23_FN, GPSR1_23, + GP_1_22_FN, GPSR1_22, + GP_1_21_FN, GPSR1_21, + GP_1_20_FN, GPSR1_20, + GP_1_19_FN, GPSR1_19, + GP_1_18_FN, GPSR1_18, + GP_1_17_FN, GPSR1_17, + GP_1_16_FN, GPSR1_16, + GP_1_15_FN, GPSR1_15, + GP_1_14_FN, GPSR1_14, + GP_1_13_FN, GPSR1_13, + GP_1_12_FN, GPSR1_12, + GP_1_11_FN, GPSR1_11, + GP_1_10_FN, GPSR1_10, + GP_1_9_FN, GPSR1_9, + GP_1_8_FN, GPSR1_8, + GP_1_7_FN, GPSR1_7, + GP_1_6_FN, GPSR1_6, + GP_1_5_FN, GPSR1_5, + GP_1_4_FN, GPSR1_4, + GP_1_3_FN, GPSR1_3, + GP_1_2_FN, GPSR1_2, + GP_1_1_FN, GPSR1_1, + GP_1_0_FN, GPSR1_0, } + }, + { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1) { + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + GP_2_14_FN, GPSR2_14, + GP_2_13_FN, GPSR2_13, + GP_2_12_FN, GPSR2_12, + GP_2_11_FN, GPSR2_11, + GP_2_10_FN, GPSR2_10, + GP_2_9_FN, GPSR2_9, + GP_2_8_FN, GPSR2_8, + GP_2_7_FN, GPSR2_7, + GP_2_6_FN, GPSR2_6, + GP_2_5_FN, GPSR2_5, + GP_2_4_FN, GPSR2_4, + GP_2_3_FN, GPSR2_3, + GP_2_2_FN, GPSR2_2, + GP_2_1_FN, GPSR2_1, + GP_2_0_FN, GPSR2_0, } + }, + { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1) { + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + GP_3_15_FN, GPSR3_15, + GP_3_14_FN, GPSR3_14, + GP_3_13_FN, GPSR3_13, + GP_3_12_FN, GPSR3_12, + GP_3_11_FN, GPSR3_11, + GP_3_10_FN, GPSR3_10, + GP_3_9_FN, GPSR3_9, + GP_3_8_FN, GPSR3_8, + GP_3_7_FN, GPSR3_7, + GP_3_6_FN, GPSR3_6, + GP_3_5_FN, GPSR3_5, + GP_3_4_FN, GPSR3_4, + GP_3_3_FN, GPSR3_3, + GP_3_2_FN, GPSR3_2, + GP_3_1_FN, GPSR3_1, + GP_3_0_FN, GPSR3_0, } + }, + { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1) { + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + GP_4_17_FN, GPSR4_17, + GP_4_16_FN, GPSR4_16, + GP_4_15_FN, GPSR4_15, + GP_4_14_FN, GPSR4_14, + GP_4_13_FN, GPSR4_13, + GP_4_12_FN, GPSR4_12, + GP_4_11_FN, GPSR4_11, + GP_4_10_FN, GPSR4_10, + GP_4_9_FN, GPSR4_9, + GP_4_8_FN, GPSR4_8, + GP_4_7_FN, GPSR4_7, + GP_4_6_FN, GPSR4_6, + GP_4_5_FN, GPSR4_5, + GP_4_4_FN, GPSR4_4, + GP_4_3_FN, GPSR4_3, + GP_4_2_FN, GPSR4_2, + GP_4_1_FN, GPSR4_1, + GP_4_0_FN, GPSR4_0, } + }, + { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1) { + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + GP_5_25_FN, GPSR5_25, + GP_5_24_FN, GPSR5_24, + GP_5_23_FN, GPSR5_23, + GP_5_22_FN, GPSR5_22, + GP_5_21_FN, GPSR5_21, + GP_5_20_FN, GPSR5_20, + GP_5_19_FN, GPSR5_19, + GP_5_18_FN, GPSR5_18, + GP_5_17_FN, GPSR5_17, + GP_5_16_FN, GPSR5_16, + GP_5_15_FN, GPSR5_15, + GP_5_14_FN, GPSR5_14, + GP_5_13_FN, GPSR5_13, + GP_5_12_FN, GPSR5_12, + GP_5_11_FN, GPSR5_11, + GP_5_10_FN, GPSR5_10, + GP_5_9_FN, GPSR5_9, + GP_5_8_FN, GPSR5_8, + GP_5_7_FN, GPSR5_7, + GP_5_6_FN, GPSR5_6, + GP_5_5_FN, GPSR5_5, + GP_5_4_FN, GPSR5_4, + GP_5_3_FN, GPSR5_3, + GP_5_2_FN, GPSR5_2, + GP_5_1_FN, GPSR5_1, + GP_5_0_FN, GPSR5_0, } + }, + { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1) { + GP_6_31_FN, GPSR6_31, + GP_6_30_FN, GPSR6_30, + GP_6_29_FN, GPSR6_29, + GP_6_28_FN, GPSR6_28, + GP_6_27_FN, GPSR6_27, + GP_6_26_FN, GPSR6_26, + GP_6_25_FN, GPSR6_25, + GP_6_24_FN, GPSR6_24, + GP_6_23_FN, GPSR6_23, + GP_6_22_FN, GPSR6_22, + GP_6_21_FN, GPSR6_21, + GP_6_20_FN, GPSR6_20, + GP_6_19_FN, GPSR6_19, + GP_6_18_FN, GPSR6_18, + GP_6_17_FN, GPSR6_17, + GP_6_16_FN, GPSR6_16, + GP_6_15_FN, GPSR6_15, + GP_6_14_FN, GPSR6_14, + GP_6_13_FN, GPSR6_13, + GP_6_12_FN, GPSR6_12, + GP_6_11_FN, GPSR6_11, + GP_6_10_FN, GPSR6_10, + GP_6_9_FN, GPSR6_9, + GP_6_8_FN, GPSR6_8, + GP_6_7_FN, GPSR6_7, + GP_6_6_FN, GPSR6_6, + GP_6_5_FN, GPSR6_5, + GP_6_4_FN, GPSR6_4, + GP_6_3_FN, GPSR6_3, + GP_6_2_FN, GPSR6_2, + GP_6_1_FN, GPSR6_1, + GP_6_0_FN, GPSR6_0, } + }, + { PINMUX_CFG_REG("GPSR7", 0xe606011c, 32, 1) { + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + GP_7_3_FN, GPSR7_3, + GP_7_2_FN, GPSR7_2, + GP_7_1_FN, GPSR7_1, + GP_7_0_FN, GPSR7_0, } + }, +#undef F_ +#undef FM + +#define F_(x, y) x, +#define FM(x) FN_##x, + { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4) { + IP0_31_28 + IP0_27_24 + IP0_23_20 + IP0_19_16 + IP0_15_12 + IP0_11_8 + IP0_7_4 + IP0_3_0 } + }, + { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4) { + IP1_31_28 + IP1_27_24 + IP1_23_20 + IP1_19_16 + IP1_15_12 + IP1_11_8 + IP1_7_4 + IP1_3_0 } + }, + { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4) { + IP2_31_28 + IP2_27_24 + IP2_23_20 + IP2_19_16 + IP2_15_12 + IP2_11_8 + IP2_7_4 + IP2_3_0 } + }, + { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4) { + IP3_31_28 + IP3_27_24 + IP3_23_20 + IP3_19_16 + IP3_15_12 + IP3_11_8 + IP3_7_4 + IP3_3_0 } + }, + { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4) { + IP4_31_28 + IP4_27_24 + IP4_23_20 + IP4_19_16 + IP4_15_12 + IP4_11_8 + IP4_7_4 + IP4_3_0 } + }, + { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4) { + IP5_31_28 + IP5_27_24 + IP5_23_20 + IP5_19_16 + IP5_15_12 + IP5_11_8 + IP5_7_4 + IP5_3_0 } + }, + { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4) { + IP6_31_28 + IP6_27_24 + IP6_23_20 + IP6_19_16 + IP6_15_12 + IP6_11_8 + IP6_7_4 + IP6_3_0 } + }, + { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4) { + IP7_31_28 + IP7_27_24 + IP7_23_20 + IP7_19_16 + IP7_15_12 + IP7_11_8 + IP7_7_4 + IP7_3_0 } + }, + { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4) { + IP8_31_28 + IP8_27_24 + IP8_23_20 + IP8_19_16 + IP8_15_12 + IP8_11_8 + IP8_7_4 + IP8_3_0 } + }, + { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4) { + IP9_31_28 + IP9_27_24 + IP9_23_20 + IP9_19_16 + IP9_15_12 + IP9_11_8 + IP9_7_4 + IP9_3_0 } + }, + { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4) { + IP10_31_28 + IP10_27_24 + IP10_23_20 + IP10_19_16 + IP10_15_12 + IP10_11_8 + IP10_7_4 + IP10_3_0 } + }, + { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4) { + IP11_31_28 + IP11_27_24 + IP11_23_20 + IP11_19_16 + IP11_15_12 + IP11_11_8 + IP11_7_4 + IP11_3_0 } + }, + { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4) { + IP12_31_28 + IP12_27_24 + IP12_23_20 + IP12_19_16 + IP12_15_12 + IP12_11_8 + IP12_7_4 + IP12_3_0 } + }, + { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4) { + IP13_31_28 + IP13_27_24 + IP13_23_20 + IP13_19_16 + IP13_15_12 + IP13_11_8 + IP13_7_4 + IP13_3_0 } + }, + { PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4) { + IP14_31_28 + IP14_27_24 + IP14_23_20 + IP14_19_16 + IP14_15_12 + IP14_11_8 + IP14_7_4 + IP14_3_0 } + }, + { PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4) { + IP15_31_28 + IP15_27_24 + IP15_23_20 + IP15_19_16 + IP15_15_12 + IP15_11_8 + IP15_7_4 + IP15_3_0 } + }, + { PINMUX_CFG_REG("IPSR16", 0xe6060240, 32, 4) { + IP16_31_28 + IP16_27_24 + IP16_23_20 + IP16_19_16 + IP16_15_12 + IP16_11_8 + IP16_7_4 + IP16_3_0 } + }, + { PINMUX_CFG_REG("IPSR17", 0xe6060244, 32, 4) { + IP17_31_28 + IP17_27_24 + IP17_23_20 + IP17_19_16 + IP17_15_12 + IP17_11_8 + IP17_7_4 + IP17_3_0 } + }, + { PINMUX_CFG_REG("IPSR18", 0xe6060248, 32, 4) { + /* IP18_31_28 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* IP18_27_24 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* IP18_23_20 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* IP18_19_16 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* IP18_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* IP18_11_8 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + IP18_7_4 + IP18_3_0 } + }, +#undef F_ +#undef FM + +#define F_(x, y) x, +#define FM(x) FN_##x, + { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32, + 3, 2, 3, 1, 1, 1, 1, 1, 2, 1, + 1, 2, 1, 1, 1, 2, 2, 1, 2, 3) { + MOD_SEL0_31_30_29 + MOD_SEL0_28_27 + MOD_SEL0_26_25_24 + MOD_SEL0_23 + MOD_SEL0_22 + MOD_SEL0_21 + MOD_SEL0_20 + MOD_SEL0_19 + MOD_SEL0_18_17 + MOD_SEL0_16 + MOD_SEL0_15 + MOD_SEL0_14_13 + MOD_SEL0_12 + MOD_SEL0_11 + MOD_SEL0_10 + MOD_SEL0_9_8 + MOD_SEL0_7_6 + MOD_SEL0_5 + MOD_SEL0_4_3 + /* RESERVED 2, 1, 0 */ + 0, 0, 0, 0, 0, 0, 0, 0 } + }, + { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32, + 2, 3, 1, 2, 3, 1, 1, 2, 1, + 2, 1, 1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1) { + MOD_SEL1_31_30 + MOD_SEL1_29_28_27 + MOD_SEL1_26 + MOD_SEL1_25_24 + MOD_SEL1_23_22_21 + MOD_SEL1_20 + MOD_SEL1_19 + MOD_SEL1_18_17 + MOD_SEL1_16 + MOD_SEL1_15_14 + MOD_SEL1_13 + MOD_SEL1_12 + MOD_SEL1_11 + MOD_SEL1_10 + MOD_SEL1_9 + 0, 0, 0, 0, /* RESERVED 8, 7 */ + MOD_SEL1_6 + MOD_SEL1_5 + MOD_SEL1_4 + MOD_SEL1_3 + MOD_SEL1_2 + MOD_SEL1_1 + MOD_SEL1_0 } + }, + { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32, + 1, 1, 1, 2, 1, 3, 1, 1, 1, 1, 1, 1, 1, + 4, 4, 4, 3, 1) { + MOD_SEL2_31 + MOD_SEL2_30 + MOD_SEL2_29 + MOD_SEL2_28_27 + MOD_SEL2_26 + MOD_SEL2_25_24_23 + MOD_SEL2_22 + MOD_SEL2_21 + MOD_SEL2_20 + MOD_SEL2_19 + MOD_SEL2_18 + MOD_SEL2_17 + /* RESERVED 16 */ + 0, 0, + /* RESERVED 15, 14, 13, 12 */ + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + /* RESERVED 11, 10, 9, 8 */ + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + /* RESERVED 7, 6, 5, 4 */ + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + /* RESERVED 3, 2, 1 */ + 0, 0, 0, 0, 0, 0, 0, 0, + MOD_SEL2_0 } + }, + { }, +}; + +const struct sh_pfc_soc_info r8a7796_pinmux_info = { + .name = "r8a77960_pfc", + .unlock_reg = 0xe6060000, /* PMMR */ + + .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, + + .pins = pinmux_pins, + .nr_pins = ARRAY_SIZE(pinmux_pins), + .groups = pinmux_groups, + .nr_groups = ARRAY_SIZE(pinmux_groups), + .functions = pinmux_functions, + .nr_functions = ARRAY_SIZE(pinmux_functions), + + .cfg_regs = pinmux_config_regs, + + .pinmux_data = pinmux_data, + .pinmux_data_size = ARRAY_SIZE(pinmux_data), +}; diff --git a/drivers/pinctrl/sh-pfc/sh_pfc.h b/drivers/pinctrl/sh-pfc/sh_pfc.h index ed12886d5bd5..c24067edcec4 100644 --- a/drivers/pinctrl/sh-pfc/sh_pfc.h +++ b/drivers/pinctrl/sh-pfc/sh_pfc.h @@ -261,6 +261,7 @@ extern const struct sh_pfc_soc_info r8a7792_pinmux_info; extern const struct sh_pfc_soc_info r8a7793_pinmux_info; extern const struct sh_pfc_soc_info r8a7794_pinmux_info; extern const struct sh_pfc_soc_info r8a7795_pinmux_info; +extern const struct sh_pfc_soc_info r8a7796_pinmux_info; extern const struct sh_pfc_soc_info sh7203_pinmux_info; extern const struct sh_pfc_soc_info sh7264_pinmux_info; extern const struct sh_pfc_soc_info sh7269_pinmux_info; -- cgit 1.4.1 From fc43d8b21754186dd1cd13d44f4721c2139e8068 Mon Sep 17 00:00:00 2001 From: Takeshi Kihara Date: Thu, 18 Aug 2016 15:12:33 +0200 Subject: pinctrl: sh-pfc: r8a7796: Add SCIF pins, groups and functions This patch adds SCIF{0,1,2,3,4,5} pins, groups and functions to R8A7796 SoC. Signed-off-by: Takeshi Kihara Signed-off-by: Geert Uytterhoeven --- drivers/pinctrl/sh-pfc/pfc-r8a7796.c | 300 +++++++++++++++++++++++++++++++++++ 1 file changed, 300 insertions(+) diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c index 0d14ca956859..090baff91560 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c @@ -1486,10 +1486,310 @@ static const struct sh_pfc_pin pinmux_pins[] = { PINMUX_GPIO_GP_ALL(), }; +/* - SCIF0 ------------------------------------------------------------------ */ +static const unsigned int scif0_data_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2), +}; +static const unsigned int scif0_data_mux[] = { + RX0_MARK, TX0_MARK, +}; +static const unsigned int scif0_clk_pins[] = { + /* SCK */ + RCAR_GP_PIN(5, 0), +}; +static const unsigned int scif0_clk_mux[] = { + SCK0_MARK, +}; +static const unsigned int scif0_ctrl_pins[] = { + /* RTS, CTS */ + RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3), +}; +static const unsigned int scif0_ctrl_mux[] = { + RTS0_N_TANS_MARK, CTS0_N_MARK, +}; +/* - SCIF1 ------------------------------------------------------------------ */ +static const unsigned int scif1_data_a_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6), +}; +static const unsigned int scif1_data_a_mux[] = { + RX1_A_MARK, TX1_A_MARK, +}; +static const unsigned int scif1_clk_pins[] = { + /* SCK */ + RCAR_GP_PIN(6, 21), +}; +static const unsigned int scif1_clk_mux[] = { + SCK1_MARK, +}; +static const unsigned int scif1_ctrl_pins[] = { + /* RTS, CTS */ + RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7), +}; +static const unsigned int scif1_ctrl_mux[] = { + RTS1_N_TANS_MARK, CTS1_N_MARK, +}; + +static const unsigned int scif1_data_b_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25), +}; +static const unsigned int scif1_data_b_mux[] = { + RX1_B_MARK, TX1_B_MARK, +}; +/* - SCIF2 ------------------------------------------------------------------ */ +static const unsigned int scif2_data_a_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10), +}; +static const unsigned int scif2_data_a_mux[] = { + RX2_A_MARK, TX2_A_MARK, +}; +static const unsigned int scif2_clk_pins[] = { + /* SCK */ + RCAR_GP_PIN(5, 9), +}; +static const unsigned int scif2_clk_mux[] = { + SCK2_MARK, +}; +static const unsigned int scif2_data_b_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16), +}; +static const unsigned int scif2_data_b_mux[] = { + RX2_B_MARK, TX2_B_MARK, +}; +/* - SCIF3 ------------------------------------------------------------------ */ +static const unsigned int scif3_data_a_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24), +}; +static const unsigned int scif3_data_a_mux[] = { + RX3_A_MARK, TX3_A_MARK, +}; +static const unsigned int scif3_clk_pins[] = { + /* SCK */ + RCAR_GP_PIN(1, 22), +}; +static const unsigned int scif3_clk_mux[] = { + SCK3_MARK, +}; +static const unsigned int scif3_ctrl_pins[] = { + /* RTS, CTS */ + RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25), +}; +static const unsigned int scif3_ctrl_mux[] = { + RTS3_N_TANS_MARK, CTS3_N_MARK, +}; +static const unsigned int scif3_data_b_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11), +}; +static const unsigned int scif3_data_b_mux[] = { + RX3_B_MARK, TX3_B_MARK, +}; +/* - SCIF4 ------------------------------------------------------------------ */ +static const unsigned int scif4_data_a_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12), +}; +static const unsigned int scif4_data_a_mux[] = { + RX4_A_MARK, TX4_A_MARK, +}; +static const unsigned int scif4_clk_a_pins[] = { + /* SCK */ + RCAR_GP_PIN(2, 10), +}; +static const unsigned int scif4_clk_a_mux[] = { + SCK4_A_MARK, +}; +static const unsigned int scif4_ctrl_a_pins[] = { + /* RTS, CTS */ + RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13), +}; +static const unsigned int scif4_ctrl_a_mux[] = { + RTS4_N_TANS_A_MARK, CTS4_N_A_MARK, +}; +static const unsigned int scif4_data_b_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), +}; +static const unsigned int scif4_data_b_mux[] = { + RX4_B_MARK, TX4_B_MARK, +}; +static const unsigned int scif4_clk_b_pins[] = { + /* SCK */ + RCAR_GP_PIN(1, 5), +}; +static const unsigned int scif4_clk_b_mux[] = { + SCK4_B_MARK, +}; +static const unsigned int scif4_ctrl_b_pins[] = { + /* RTS, CTS */ + RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9), +}; +static const unsigned int scif4_ctrl_b_mux[] = { + RTS4_N_TANS_B_MARK, CTS4_N_B_MARK, +}; +static const unsigned int scif4_data_c_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13), +}; +static const unsigned int scif4_data_c_mux[] = { + RX4_C_MARK, TX4_C_MARK, +}; +static const unsigned int scif4_clk_c_pins[] = { + /* SCK */ + RCAR_GP_PIN(0, 8), +}; +static const unsigned int scif4_clk_c_mux[] = { + SCK4_C_MARK, +}; +static const unsigned int scif4_ctrl_c_pins[] = { + /* RTS, CTS */ + RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10), +}; +static const unsigned int scif4_ctrl_c_mux[] = { + RTS4_N_TANS_C_MARK, CTS4_N_C_MARK, +}; +/* - SCIF5 ------------------------------------------------------------------ */ +static const unsigned int scif5_data_a_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21), +}; +static const unsigned int scif5_data_a_mux[] = { + RX5_A_MARK, TX5_A_MARK, +}; +static const unsigned int scif5_clk_a_pins[] = { + /* SCK */ + RCAR_GP_PIN(6, 21), +}; +static const unsigned int scif5_clk_a_mux[] = { + SCK5_A_MARK, +}; + +static const unsigned int scif5_data_b_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 18), +}; +static const unsigned int scif5_data_b_mux[] = { + RX5_B_MARK, TX5_B_MARK, +}; +static const unsigned int scif5_clk_b_pins[] = { + /* SCK */ + RCAR_GP_PIN(5, 0), +}; +static const unsigned int scif5_clk_b_mux[] = { + SCK5_B_MARK, +}; + +/* - SCIF Clock ------------------------------------------------------------- */ +static const unsigned int scif_clk_a_pins[] = { + /* SCIF_CLK */ + RCAR_GP_PIN(6, 23), +}; +static const unsigned int scif_clk_a_mux[] = { + SCIF_CLK_A_MARK, +}; +static const unsigned int scif_clk_b_pins[] = { + /* SCIF_CLK */ + RCAR_GP_PIN(5, 9), +}; +static const unsigned int scif_clk_b_mux[] = { + SCIF_CLK_B_MARK, +}; + static const struct sh_pfc_pin_group pinmux_groups[] = { + SH_PFC_PIN_GROUP(scif0_data), + SH_PFC_PIN_GROUP(scif0_clk), + SH_PFC_PIN_GROUP(scif0_ctrl), + SH_PFC_PIN_GROUP(scif1_data_a), + SH_PFC_PIN_GROUP(scif1_clk), + SH_PFC_PIN_GROUP(scif1_ctrl), + SH_PFC_PIN_GROUP(scif1_data_b), + SH_PFC_PIN_GROUP(scif2_data_a), + SH_PFC_PIN_GROUP(scif2_clk), + SH_PFC_PIN_GROUP(scif2_data_b), + SH_PFC_PIN_GROUP(scif3_data_a), + SH_PFC_PIN_GROUP(scif3_clk), + SH_PFC_PIN_GROUP(scif3_ctrl), + SH_PFC_PIN_GROUP(scif3_data_b), + SH_PFC_PIN_GROUP(scif4_data_a), + SH_PFC_PIN_GROUP(scif4_clk_a), + SH_PFC_PIN_GROUP(scif4_ctrl_a), + SH_PFC_PIN_GROUP(scif4_data_b), + SH_PFC_PIN_GROUP(scif4_clk_b), + SH_PFC_PIN_GROUP(scif4_ctrl_b), + SH_PFC_PIN_GROUP(scif4_data_c), + SH_PFC_PIN_GROUP(scif4_clk_c), + SH_PFC_PIN_GROUP(scif4_ctrl_c), + SH_PFC_PIN_GROUP(scif5_data_a), + SH_PFC_PIN_GROUP(scif5_clk_a), + SH_PFC_PIN_GROUP(scif5_data_b), + SH_PFC_PIN_GROUP(scif5_clk_b), + SH_PFC_PIN_GROUP(scif_clk_a), + SH_PFC_PIN_GROUP(scif_clk_b), +}; + +static const char * const scif0_groups[] = { + "scif0_data", + "scif0_clk", + "scif0_ctrl", +}; + +static const char * const scif1_groups[] = { + "scif1_data_a", + "scif1_clk", + "scif1_ctrl", + "scif1_data_b", +}; + +static const char * const scif2_groups[] = { + "scif2_data_a", + "scif2_clk", + "scif2_data_b", +}; + +static const char * const scif3_groups[] = { + "scif3_data_a", + "scif3_clk", + "scif3_ctrl", + "scif3_data_b", +}; + +static const char * const scif4_groups[] = { + "scif4_data_a", + "scif4_clk_a", + "scif4_ctrl_a", + "scif4_data_b", + "scif4_clk_b", + "scif4_ctrl_b", + "scif4_data_c", + "scif4_clk_c", + "scif4_ctrl_c", +}; + +static const char * const scif5_groups[] = { + "scif5_data_a", + "scif5_clk_a", + "scif5_data_b", + "scif5_clk_b", +}; + +static const char * const scif_clk_groups[] = { + "scif_clk_a", + "scif_clk_b", }; static const struct sh_pfc_function pinmux_functions[] = { + SH_PFC_FUNCTION(scif0), + SH_PFC_FUNCTION(scif1), + SH_PFC_FUNCTION(scif2), + SH_PFC_FUNCTION(scif3), + SH_PFC_FUNCTION(scif4), + SH_PFC_FUNCTION(scif5), + SH_PFC_FUNCTION(scif_clk), }; static const struct pinmux_cfg_reg pinmux_config_regs[] = { -- cgit 1.4.1 From 374cf6992de89fc38d4d923c89b40816d341d678 Mon Sep 17 00:00:00 2001 From: Takeshi Kihara Date: Wed, 17 Aug 2016 13:31:52 +0200 Subject: pinctrl: sh-pfc: r8a7796: Add SDHI pins, groups and functions This patch adds SDHI pins, groups and functions to R8A7796 SoC. Signed-off-by: Takeshi Kihara Signed-off-by: Simon Horman Signed-off-by: Geert Uytterhoeven --- drivers/pinctrl/sh-pfc/pfc-r8a7796.c | 275 +++++++++++++++++++++++++++++++++++ 1 file changed, 275 insertions(+) diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c index 090baff91560..f8ab74dd0506 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c @@ -1700,6 +1700,213 @@ static const unsigned int scif_clk_b_mux[] = { SCIF_CLK_B_MARK, }; +/* - SDHI0 ------------------------------------------------------------------ */ +static const unsigned int sdhi0_data1_pins[] = { + /* D0 */ + RCAR_GP_PIN(3, 2), +}; +static const unsigned int sdhi0_data1_mux[] = { + SD0_DAT0_MARK, +}; +static const unsigned int sdhi0_data4_pins[] = { + /* D[0:3] */ + RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), + RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5), +}; +static const unsigned int sdhi0_data4_mux[] = { + SD0_DAT0_MARK, SD0_DAT1_MARK, + SD0_DAT2_MARK, SD0_DAT3_MARK, +}; +static const unsigned int sdhi0_ctrl_pins[] = { + /* CLK, CMD */ + RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1), +}; +static const unsigned int sdhi0_ctrl_mux[] = { + SD0_CLK_MARK, SD0_CMD_MARK, +}; +static const unsigned int sdhi0_cd_pins[] = { + /* CD */ + RCAR_GP_PIN(3, 12), +}; +static const unsigned int sdhi0_cd_mux[] = { + SD0_CD_MARK, +}; +static const unsigned int sdhi0_wp_pins[] = { + /* WP */ + RCAR_GP_PIN(3, 13), +}; +static const unsigned int sdhi0_wp_mux[] = { + SD0_WP_MARK, +}; +/* - SDHI1 ------------------------------------------------------------------ */ +static const unsigned int sdhi1_data1_pins[] = { + /* D0 */ + RCAR_GP_PIN(3, 8), +}; +static const unsigned int sdhi1_data1_mux[] = { + SD1_DAT0_MARK, +}; +static const unsigned int sdhi1_data4_pins[] = { + /* D[0:3] */ + RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), + RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), +}; +static const unsigned int sdhi1_data4_mux[] = { + SD1_DAT0_MARK, SD1_DAT1_MARK, + SD1_DAT2_MARK, SD1_DAT3_MARK, +}; +static const unsigned int sdhi1_ctrl_pins[] = { + /* CLK, CMD */ + RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7), +}; +static const unsigned int sdhi1_ctrl_mux[] = { + SD1_CLK_MARK, SD1_CMD_MARK, +}; +static const unsigned int sdhi1_cd_pins[] = { + /* CD */ + RCAR_GP_PIN(3, 14), +}; +static const unsigned int sdhi1_cd_mux[] = { + SD1_CD_MARK, +}; +static const unsigned int sdhi1_wp_pins[] = { + /* WP */ + RCAR_GP_PIN(3, 15), +}; +static const unsigned int sdhi1_wp_mux[] = { + SD1_WP_MARK, +}; +/* - SDHI2 ------------------------------------------------------------------ */ +static const unsigned int sdhi2_data1_pins[] = { + /* D0 */ + RCAR_GP_PIN(4, 2), +}; +static const unsigned int sdhi2_data1_mux[] = { + SD2_DAT0_MARK, +}; +static const unsigned int sdhi2_data4_pins[] = { + /* D[0:3] */ + RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3), + RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5), +}; +static const unsigned int sdhi2_data4_mux[] = { + SD2_DAT0_MARK, SD2_DAT1_MARK, + SD2_DAT2_MARK, SD2_DAT3_MARK, +}; +static const unsigned int sdhi2_data8_pins[] = { + /* D[0:7] */ + RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3), + RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5), + RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), + RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), +}; +static const unsigned int sdhi2_data8_mux[] = { + SD2_DAT0_MARK, SD2_DAT1_MARK, + SD2_DAT2_MARK, SD2_DAT3_MARK, + SD2_DAT4_MARK, SD2_DAT5_MARK, + SD2_DAT6_MARK, SD2_DAT7_MARK, +}; +static const unsigned int sdhi2_ctrl_pins[] = { + /* CLK, CMD */ + RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1), +}; +static const unsigned int sdhi2_ctrl_mux[] = { + SD2_CLK_MARK, SD2_CMD_MARK, +}; +static const unsigned int sdhi2_cd_a_pins[] = { + /* CD */ + RCAR_GP_PIN(4, 13), +}; +static const unsigned int sdhi2_cd_a_mux[] = { + SD2_CD_A_MARK, +}; +static const unsigned int sdhi2_cd_b_pins[] = { + /* CD */ + RCAR_GP_PIN(5, 10), +}; +static const unsigned int sdhi2_cd_b_mux[] = { + SD2_CD_B_MARK, +}; +static const unsigned int sdhi2_wp_a_pins[] = { + /* WP */ + RCAR_GP_PIN(4, 14), +}; +static const unsigned int sdhi2_wp_a_mux[] = { + SD2_WP_A_MARK, +}; +static const unsigned int sdhi2_wp_b_pins[] = { + /* WP */ + RCAR_GP_PIN(5, 11), +}; +static const unsigned int sdhi2_wp_b_mux[] = { + SD2_WP_B_MARK, +}; +static const unsigned int sdhi2_ds_pins[] = { + /* DS */ + RCAR_GP_PIN(4, 6), +}; +static const unsigned int sdhi2_ds_mux[] = { + SD2_DS_MARK, +}; +/* - SDHI3 ------------------------------------------------------------------ */ +static const unsigned int sdhi3_data1_pins[] = { + /* D0 */ + RCAR_GP_PIN(4, 9), +}; +static const unsigned int sdhi3_data1_mux[] = { + SD3_DAT0_MARK, +}; +static const unsigned int sdhi3_data4_pins[] = { + /* D[0:3] */ + RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10), + RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12), +}; +static const unsigned int sdhi3_data4_mux[] = { + SD3_DAT0_MARK, SD3_DAT1_MARK, + SD3_DAT2_MARK, SD3_DAT3_MARK, +}; +static const unsigned int sdhi3_data8_pins[] = { + /* D[0:7] */ + RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10), + RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12), + RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14), + RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16), +}; +static const unsigned int sdhi3_data8_mux[] = { + SD3_DAT0_MARK, SD3_DAT1_MARK, + SD3_DAT2_MARK, SD3_DAT3_MARK, + SD3_DAT4_MARK, SD3_DAT5_MARK, + SD3_DAT6_MARK, SD3_DAT7_MARK, +}; +static const unsigned int sdhi3_ctrl_pins[] = { + /* CLK, CMD */ + RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8), +}; +static const unsigned int sdhi3_ctrl_mux[] = { + SD3_CLK_MARK, SD3_CMD_MARK, +}; +static const unsigned int sdhi3_cd_pins[] = { + /* CD */ + RCAR_GP_PIN(4, 15), +}; +static const unsigned int sdhi3_cd_mux[] = { + SD3_CD_MARK, +}; +static const unsigned int sdhi3_wp_pins[] = { + /* WP */ + RCAR_GP_PIN(4, 16), +}; +static const unsigned int sdhi3_wp_mux[] = { + SD3_WP_MARK, +}; +static const unsigned int sdhi3_ds_pins[] = { + /* DS */ + RCAR_GP_PIN(4, 17), +}; +static const unsigned int sdhi3_ds_mux[] = { + SD3_DS_MARK, +}; + static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(scif0_data), SH_PFC_PIN_GROUP(scif0_clk), @@ -1730,6 +1937,32 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(scif5_clk_b), SH_PFC_PIN_GROUP(scif_clk_a), SH_PFC_PIN_GROUP(scif_clk_b), + SH_PFC_PIN_GROUP(sdhi0_data1), + SH_PFC_PIN_GROUP(sdhi0_data4), + SH_PFC_PIN_GROUP(sdhi0_ctrl), + SH_PFC_PIN_GROUP(sdhi0_cd), + SH_PFC_PIN_GROUP(sdhi0_wp), + SH_PFC_PIN_GROUP(sdhi1_data1), + SH_PFC_PIN_GROUP(sdhi1_data4), + SH_PFC_PIN_GROUP(sdhi1_ctrl), + SH_PFC_PIN_GROUP(sdhi1_cd), + SH_PFC_PIN_GROUP(sdhi1_wp), + SH_PFC_PIN_GROUP(sdhi2_data1), + SH_PFC_PIN_GROUP(sdhi2_data4), + SH_PFC_PIN_GROUP(sdhi2_data8), + SH_PFC_PIN_GROUP(sdhi2_ctrl), + SH_PFC_PIN_GROUP(sdhi2_cd_a), + SH_PFC_PIN_GROUP(sdhi2_wp_a), + SH_PFC_PIN_GROUP(sdhi2_cd_b), + SH_PFC_PIN_GROUP(sdhi2_wp_b), + SH_PFC_PIN_GROUP(sdhi2_ds), + SH_PFC_PIN_GROUP(sdhi3_data1), + SH_PFC_PIN_GROUP(sdhi3_data4), + SH_PFC_PIN_GROUP(sdhi3_data8), + SH_PFC_PIN_GROUP(sdhi3_ctrl), + SH_PFC_PIN_GROUP(sdhi3_cd), + SH_PFC_PIN_GROUP(sdhi3_wp), + SH_PFC_PIN_GROUP(sdhi3_ds), }; static const char * const scif0_groups[] = { @@ -1782,6 +2015,44 @@ static const char * const scif_clk_groups[] = { "scif_clk_b", }; +static const char * const sdhi0_groups[] = { + "sdhi0_data1", + "sdhi0_data4", + "sdhi0_ctrl", + "sdhi0_cd", + "sdhi0_wp", +}; + +static const char * const sdhi1_groups[] = { + "sdhi1_data1", + "sdhi1_data4", + "sdhi1_ctrl", + "sdhi1_cd", + "sdhi1_wp", +}; + +static const char * const sdhi2_groups[] = { + "sdhi2_data1", + "sdhi2_data4", + "sdhi2_data8", + "sdhi2_ctrl", + "sdhi2_cd_a", + "sdhi2_wp_a", + "sdhi2_cd_b", + "sdhi2_wp_b", + "sdhi2_ds", +}; + +static const char * const sdhi3_groups[] = { + "sdhi3_data1", + "sdhi3_data4", + "sdhi3_data8", + "sdhi3_ctrl", + "sdhi3_cd", + "sdhi3_wp", + "sdhi3_ds", +}; + static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(scif0), SH_PFC_FUNCTION(scif1), @@ -1790,6 +2061,10 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(scif4), SH_PFC_FUNCTION(scif5), SH_PFC_FUNCTION(scif_clk), + SH_PFC_FUNCTION(sdhi0), + SH_PFC_FUNCTION(sdhi1), + SH_PFC_FUNCTION(sdhi2), + SH_PFC_FUNCTION(sdhi3), }; static const struct pinmux_cfg_reg pinmux_config_regs[] = { -- cgit 1.4.1 From db80f0e158e62164308a857bce442dfeddb5c29e Mon Sep 17 00:00:00 2001 From: Beniamino Galvani Date: Sat, 13 Aug 2016 19:41:18 +0200 Subject: pinctrl: meson: get rid of unneeded domain structures The driver originally supported more domains (register ranges) per pinctrl device, but since commit 9dab1868ec0d ("pinctrl: amlogic: Make driver independent from two-domain configuration") each device gets assigned a single domain and we instantiate multiple pinctrl devices in the DT. Therefore, now the 'meson_domain' and 'meson_domain_data' structures don't have any reason to exist and can be removed to make the model simpler to understand. This commit doesn't change behavior. Tested on a Odroid-C2. Signed-off-by: Beniamino Galvani Acked-by: Kevin Hilman Tested-by: Kevin Hilman Signed-off-by: Linus Walleij --- drivers/pinctrl/meson/pinctrl-meson-gxbb.c | 24 +--- drivers/pinctrl/meson/pinctrl-meson.c | 222 +++++++++++------------------ drivers/pinctrl/meson/pinctrl-meson.h | 52 ++----- drivers/pinctrl/meson/pinctrl-meson8.c | 24 +--- drivers/pinctrl/meson/pinctrl-meson8b.c | 24 +--- 5 files changed, 118 insertions(+), 228 deletions(-) diff --git a/drivers/pinctrl/meson/pinctrl-meson-gxbb.c b/drivers/pinctrl/meson/pinctrl-meson-gxbb.c index cb4d6ad30530..233c9c85bbd9 100644 --- a/drivers/pinctrl/meson/pinctrl-meson-gxbb.c +++ b/drivers/pinctrl/meson/pinctrl-meson-gxbb.c @@ -556,38 +556,28 @@ static struct meson_bank meson_gxbb_aobus_banks[] = { BANK("AO", PIN(GPIOAO_0, 0), PIN(GPIOAO_13, 0), 0, 0, 0, 16, 0, 0, 0, 16, 1, 0), }; -static struct meson_domain_data meson_gxbb_periphs_domain_data = { +struct meson_pinctrl_data meson_gxbb_periphs_pinctrl_data = { .name = "periphs-banks", - .banks = meson_gxbb_periphs_banks, - .num_banks = ARRAY_SIZE(meson_gxbb_periphs_banks), .pin_base = 14, - .num_pins = 120, -}; - -static struct meson_domain_data meson_gxbb_aobus_domain_data = { - .name = "aobus-banks", - .banks = meson_gxbb_aobus_banks, - .num_banks = ARRAY_SIZE(meson_gxbb_aobus_banks), - .pin_base = 0, - .num_pins = 14, -}; - -struct meson_pinctrl_data meson_gxbb_periphs_pinctrl_data = { .pins = meson_gxbb_periphs_pins, .groups = meson_gxbb_periphs_groups, .funcs = meson_gxbb_periphs_functions, - .domain_data = &meson_gxbb_periphs_domain_data, + .banks = meson_gxbb_periphs_banks, .num_pins = ARRAY_SIZE(meson_gxbb_periphs_pins), .num_groups = ARRAY_SIZE(meson_gxbb_periphs_groups), .num_funcs = ARRAY_SIZE(meson_gxbb_periphs_functions), + .num_banks = ARRAY_SIZE(meson_gxbb_periphs_banks), }; struct meson_pinctrl_data meson_gxbb_aobus_pinctrl_data = { + .name = "aobus-banks", + .pin_base = 0, .pins = meson_gxbb_aobus_pins, .groups = meson_gxbb_aobus_groups, .funcs = meson_gxbb_aobus_functions, - .domain_data = &meson_gxbb_aobus_domain_data, + .banks = meson_gxbb_aobus_banks, .num_pins = ARRAY_SIZE(meson_gxbb_aobus_pins), .num_groups = ARRAY_SIZE(meson_gxbb_aobus_groups), .num_funcs = ARRAY_SIZE(meson_gxbb_aobus_functions), + .num_banks = ARRAY_SIZE(meson_gxbb_aobus_banks), }; diff --git a/drivers/pinctrl/meson/pinctrl-meson.c b/drivers/pinctrl/meson/pinctrl-meson.c index 11623c6b0cb3..9678599cc774 100644 --- a/drivers/pinctrl/meson/pinctrl-meson.c +++ b/drivers/pinctrl/meson/pinctrl-meson.c @@ -21,9 +21,8 @@ * domain which can't be powered off; the bank also uses a set of * registers different from the other banks. * - * For each of the two power domains (regular and always-on) there are - * 4 different register ranges that control the following properties - * of the pins: + * For each pin controller there are 4 different register ranges that + * control the following properties of the pins: * 1) pin muxing * 2) pull enable/disable * 3) pull up/down @@ -33,8 +32,8 @@ * direction are the same and thus there are only 3 register ranges. * * Every pinmux group can be enabled by a specific bit in the first - * register range of the domain; when all groups for a given pin are - * disabled the pin acts as a GPIO. + * register range; when all groups for a given pin are disabled the + * pin acts as a GPIO. * * For the pull and GPIO configuration every bank uses a contiguous * set of bits in the register sets described above; the same register @@ -66,21 +65,21 @@ /** * meson_get_bank() - find the bank containing a given pin * - * @domain: the domain containing the pin + * @pc: the pinctrl instance * @pin: the pin number * @bank: the found bank * * Return: 0 on success, a negative value on error */ -static int meson_get_bank(struct meson_domain *domain, unsigned int pin, +static int meson_get_bank(struct meson_pinctrl *pc, unsigned int pin, struct meson_bank **bank) { int i; - for (i = 0; i < domain->data->num_banks; i++) { - if (pin >= domain->data->banks[i].first && - pin <= domain->data->banks[i].last) { - *bank = &domain->data->banks[i]; + for (i = 0; i < pc->data->num_banks; i++) { + if (pin >= pc->data->banks[i].first && + pin <= pc->data->banks[i].last) { + *bank = &pc->data->banks[i]; return 0; } } @@ -88,33 +87,6 @@ static int meson_get_bank(struct meson_domain *domain, unsigned int pin, return -EINVAL; } -/** - * meson_get_domain_and_bank() - find domain and bank containing a given pin - * - * @pc: Meson pin controller device - * @pin: the pin number - * @domain: the found domain - * @bank: the found bank - * - * Return: 0 on success, a negative value on error - */ -static int meson_get_domain_and_bank(struct meson_pinctrl *pc, unsigned int pin, - struct meson_domain **domain, - struct meson_bank **bank) -{ - struct meson_domain *d; - - d = pc->domain; - - if (pin >= d->data->pin_base && - pin < d->data->pin_base + d->data->num_pins) { - *domain = d; - return meson_get_bank(d, pin, bank); - } - - return -EINVAL; -} - /** * meson_calc_reg_and_bit() - calculate register and bit for a pin * @@ -190,7 +162,6 @@ static void meson_pmx_disable_other_groups(struct meson_pinctrl *pc, unsigned int pin, int sel_group) { struct meson_pmx_group *group; - struct meson_domain *domain; int i, j; for (i = 0; i < pc->data->num_groups; i++) { @@ -201,8 +172,7 @@ static void meson_pmx_disable_other_groups(struct meson_pinctrl *pc, for (j = 0; j < group->num_pins; j++) { if (group->pins[j] == pin) { /* We have found a group using the pin */ - domain = pc->domain; - regmap_update_bits(domain->reg_mux, + regmap_update_bits(pc->reg_mux, group->reg * 4, BIT(group->bit), 0); } @@ -216,7 +186,6 @@ static int meson_pmx_set_mux(struct pinctrl_dev *pcdev, unsigned func_num, struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev); struct meson_pmx_func *func = &pc->data->funcs[func_num]; struct meson_pmx_group *group = &pc->data->groups[group_num]; - struct meson_domain *domain = pc->domain; int i, ret = 0; dev_dbg(pc->dev, "enable function %s, group %s\n", func->name, @@ -231,7 +200,7 @@ static int meson_pmx_set_mux(struct pinctrl_dev *pcdev, unsigned func_num, /* Function 0 (GPIO) doesn't need any additional setting */ if (func_num) - ret = regmap_update_bits(domain->reg_mux, group->reg * 4, + ret = regmap_update_bits(pc->reg_mux, group->reg * 4, BIT(group->bit), BIT(group->bit)); return ret; @@ -287,14 +256,13 @@ static int meson_pinconf_set(struct pinctrl_dev *pcdev, unsigned int pin, unsigned long *configs, unsigned num_configs) { struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev); - struct meson_domain *domain; struct meson_bank *bank; enum pin_config_param param; unsigned int reg, bit; int i, ret; u16 arg; - ret = meson_get_domain_and_bank(pc, pin, &domain, &bank); + ret = meson_get_bank(pc, pin, &bank); if (ret) return ret; @@ -307,7 +275,7 @@ static int meson_pinconf_set(struct pinctrl_dev *pcdev, unsigned int pin, dev_dbg(pc->dev, "pin %u: disable bias\n", pin); meson_calc_reg_and_bit(bank, pin, REG_PULL, ®, &bit); - ret = regmap_update_bits(domain->reg_pull, reg, + ret = regmap_update_bits(pc->reg_pull, reg, BIT(bit), 0); if (ret) return ret; @@ -317,13 +285,13 @@ static int meson_pinconf_set(struct pinctrl_dev *pcdev, unsigned int pin, meson_calc_reg_and_bit(bank, pin, REG_PULLEN, ®, &bit); - ret = regmap_update_bits(domain->reg_pullen, reg, + ret = regmap_update_bits(pc->reg_pullen, reg, BIT(bit), BIT(bit)); if (ret) return ret; meson_calc_reg_and_bit(bank, pin, REG_PULL, ®, &bit); - ret = regmap_update_bits(domain->reg_pull, reg, + ret = regmap_update_bits(pc->reg_pull, reg, BIT(bit), BIT(bit)); if (ret) return ret; @@ -333,13 +301,13 @@ static int meson_pinconf_set(struct pinctrl_dev *pcdev, unsigned int pin, meson_calc_reg_and_bit(bank, pin, REG_PULLEN, ®, &bit); - ret = regmap_update_bits(domain->reg_pullen, reg, + ret = regmap_update_bits(pc->reg_pullen, reg, BIT(bit), BIT(bit)); if (ret) return ret; meson_calc_reg_and_bit(bank, pin, REG_PULL, ®, &bit); - ret = regmap_update_bits(domain->reg_pull, reg, + ret = regmap_update_bits(pc->reg_pull, reg, BIT(bit), 0); if (ret) return ret; @@ -354,18 +322,17 @@ static int meson_pinconf_set(struct pinctrl_dev *pcdev, unsigned int pin, static int meson_pinconf_get_pull(struct meson_pinctrl *pc, unsigned int pin) { - struct meson_domain *domain; struct meson_bank *bank; unsigned int reg, bit, val; int ret, conf; - ret = meson_get_domain_and_bank(pc, pin, &domain, &bank); + ret = meson_get_bank(pc, pin, &bank); if (ret) return ret; meson_calc_reg_and_bit(bank, pin, REG_PULLEN, ®, &bit); - ret = regmap_read(domain->reg_pullen, reg, &val); + ret = regmap_read(pc->reg_pullen, reg, &val); if (ret) return ret; @@ -374,7 +341,7 @@ static int meson_pinconf_get_pull(struct meson_pinctrl *pc, unsigned int pin) } else { meson_calc_reg_and_bit(bank, pin, REG_PULL, ®, &bit); - ret = regmap_read(domain->reg_pull, reg, &val); + ret = regmap_read(pc->reg_pull, reg, &val); if (ret) return ret; @@ -452,82 +419,82 @@ static int meson_gpio_request(struct gpio_chip *chip, unsigned gpio) static void meson_gpio_free(struct gpio_chip *chip, unsigned gpio) { - struct meson_domain *domain = gpiochip_get_data(chip); + struct meson_pinctrl *pc = gpiochip_get_data(chip); - pinctrl_free_gpio(domain->data->pin_base + gpio); + pinctrl_free_gpio(pc->data->pin_base + gpio); } static int meson_gpio_direction_input(struct gpio_chip *chip, unsigned gpio) { - struct meson_domain *domain = gpiochip_get_data(chip); + struct meson_pinctrl *pc = gpiochip_get_data(chip); unsigned int reg, bit, pin; struct meson_bank *bank; int ret; - pin = domain->data->pin_base + gpio; - ret = meson_get_bank(domain, pin, &bank); + pin = pc->data->pin_base + gpio; + ret = meson_get_bank(pc, pin, &bank); if (ret) return ret; meson_calc_reg_and_bit(bank, pin, REG_DIR, ®, &bit); - return regmap_update_bits(domain->reg_gpio, reg, BIT(bit), BIT(bit)); + return regmap_update_bits(pc->reg_gpio, reg, BIT(bit), BIT(bit)); } static int meson_gpio_direction_output(struct gpio_chip *chip, unsigned gpio, int value) { - struct meson_domain *domain = gpiochip_get_data(chip); + struct meson_pinctrl *pc = gpiochip_get_data(chip); unsigned int reg, bit, pin; struct meson_bank *bank; int ret; - pin = domain->data->pin_base + gpio; - ret = meson_get_bank(domain, pin, &bank); + pin = pc->data->pin_base + gpio; + ret = meson_get_bank(pc, pin, &bank); if (ret) return ret; meson_calc_reg_and_bit(bank, pin, REG_DIR, ®, &bit); - ret = regmap_update_bits(domain->reg_gpio, reg, BIT(bit), 0); + ret = regmap_update_bits(pc->reg_gpio, reg, BIT(bit), 0); if (ret) return ret; meson_calc_reg_and_bit(bank, pin, REG_OUT, ®, &bit); - return regmap_update_bits(domain->reg_gpio, reg, BIT(bit), + return regmap_update_bits(pc->reg_gpio, reg, BIT(bit), value ? BIT(bit) : 0); } static void meson_gpio_set(struct gpio_chip *chip, unsigned gpio, int value) { - struct meson_domain *domain = gpiochip_get_data(chip); + struct meson_pinctrl *pc = gpiochip_get_data(chip); unsigned int reg, bit, pin; struct meson_bank *bank; int ret; - pin = domain->data->pin_base + gpio; - ret = meson_get_bank(domain, pin, &bank); + pin = pc->data->pin_base + gpio; + ret = meson_get_bank(pc, pin, &bank); if (ret) return; meson_calc_reg_and_bit(bank, pin, REG_OUT, ®, &bit); - regmap_update_bits(domain->reg_gpio, reg, BIT(bit), + regmap_update_bits(pc->reg_gpio, reg, BIT(bit), value ? BIT(bit) : 0); } static int meson_gpio_get(struct gpio_chip *chip, unsigned gpio) { - struct meson_domain *domain = gpiochip_get_data(chip); + struct meson_pinctrl *pc = gpiochip_get_data(chip); unsigned int reg, bit, val, pin; struct meson_bank *bank; int ret; - pin = domain->data->pin_base + gpio; - ret = meson_get_bank(domain, pin, &bank); + pin = pc->data->pin_base + gpio; + ret = meson_get_bank(pc, pin, &bank); if (ret) return ret; meson_calc_reg_and_bit(bank, pin, REG_IN, ®, &bit); - regmap_read(domain->reg_gpio, reg, &val); + regmap_read(pc->reg_gpio, reg, &val); return !!(val & BIT(bit)); } @@ -562,35 +529,32 @@ static const struct of_device_id meson_pinctrl_dt_match[] = { static int meson_gpiolib_register(struct meson_pinctrl *pc) { - struct meson_domain *domain; int ret; - domain = pc->domain; - - domain->chip.label = domain->data->name; - domain->chip.parent = pc->dev; - domain->chip.request = meson_gpio_request; - domain->chip.free = meson_gpio_free; - domain->chip.direction_input = meson_gpio_direction_input; - domain->chip.direction_output = meson_gpio_direction_output; - domain->chip.get = meson_gpio_get; - domain->chip.set = meson_gpio_set; - domain->chip.base = domain->data->pin_base; - domain->chip.ngpio = domain->data->num_pins; - domain->chip.can_sleep = false; - domain->chip.of_node = domain->of_node; - domain->chip.of_gpio_n_cells = 2; - - ret = gpiochip_add_data(&domain->chip, domain); + pc->chip.label = pc->data->name; + pc->chip.parent = pc->dev; + pc->chip.request = meson_gpio_request; + pc->chip.free = meson_gpio_free; + pc->chip.direction_input = meson_gpio_direction_input; + pc->chip.direction_output = meson_gpio_direction_output; + pc->chip.get = meson_gpio_get; + pc->chip.set = meson_gpio_set; + pc->chip.base = pc->data->pin_base; + pc->chip.ngpio = pc->data->num_pins; + pc->chip.can_sleep = false; + pc->chip.of_node = pc->of_node; + pc->chip.of_gpio_n_cells = 2; + + ret = gpiochip_add_data(&pc->chip, pc); if (ret) { dev_err(pc->dev, "can't add gpio chip %s\n", - domain->data->name); + pc->data->name); goto fail; } - ret = gpiochip_add_pin_range(&domain->chip, dev_name(pc->dev), - 0, domain->data->pin_base, - domain->chip.ngpio); + ret = gpiochip_add_pin_range(&pc->chip, dev_name(pc->dev), + 0, pc->data->pin_base, + pc->chip.ngpio); if (ret) { dev_err(pc->dev, "can't add pin range\n"); goto fail; @@ -598,7 +562,7 @@ static int meson_gpiolib_register(struct meson_pinctrl *pc) return 0; fail: - gpiochip_remove(&pc->domain->chip); + gpiochip_remove(&pc->chip); return ret; } @@ -637,58 +601,46 @@ static struct regmap *meson_map_resource(struct meson_pinctrl *pc, static int meson_pinctrl_parse_dt(struct meson_pinctrl *pc, struct device_node *node) { - struct device_node *np; - struct meson_domain *domain; - int num_domains = 0; + struct device_node *np, *gpio_np = NULL; for_each_child_of_node(node, np) { if (!of_find_property(np, "gpio-controller", NULL)) continue; - num_domains++; + if (gpio_np) { + dev_err(pc->dev, "multiple gpio nodes\n"); + return -EINVAL; + } + gpio_np = np; } - if (num_domains != 1) { - dev_err(pc->dev, "wrong number of subnodes\n"); + if (!gpio_np) { + dev_err(pc->dev, "no gpio node found\n"); return -EINVAL; } - pc->domain = devm_kzalloc(pc->dev, sizeof(struct meson_domain), GFP_KERNEL); - if (!pc->domain) - return -ENOMEM; - - domain = pc->domain; - domain->data = pc->data->domain_data; - - for_each_child_of_node(node, np) { - if (!of_find_property(np, "gpio-controller", NULL)) - continue; - - domain->of_node = np; + pc->of_node = gpio_np; - domain->reg_mux = meson_map_resource(pc, np, "mux"); - if (IS_ERR(domain->reg_mux)) { - dev_err(pc->dev, "mux registers not found\n"); - return PTR_ERR(domain->reg_mux); - } - - domain->reg_pull = meson_map_resource(pc, np, "pull"); - if (IS_ERR(domain->reg_pull)) { - dev_err(pc->dev, "pull registers not found\n"); - return PTR_ERR(domain->reg_pull); - } + pc->reg_mux = meson_map_resource(pc, gpio_np, "mux"); + if (IS_ERR(pc->reg_mux)) { + dev_err(pc->dev, "mux registers not found\n"); + return PTR_ERR(pc->reg_mux); + } - domain->reg_pullen = meson_map_resource(pc, np, "pull-enable"); - /* Use pull region if pull-enable one is not present */ - if (IS_ERR(domain->reg_pullen)) - domain->reg_pullen = domain->reg_pull; + pc->reg_pull = meson_map_resource(pc, gpio_np, "pull"); + if (IS_ERR(pc->reg_pull)) { + dev_err(pc->dev, "pull registers not found\n"); + return PTR_ERR(pc->reg_pull); + } - domain->reg_gpio = meson_map_resource(pc, np, "gpio"); - if (IS_ERR(domain->reg_gpio)) { - dev_err(pc->dev, "gpio registers not found\n"); - return PTR_ERR(domain->reg_gpio); - } + pc->reg_pullen = meson_map_resource(pc, gpio_np, "pull-enable"); + /* Use pull region if pull-enable one is not present */ + if (IS_ERR(pc->reg_pullen)) + pc->reg_pullen = pc->reg_pull; - break; + pc->reg_gpio = meson_map_resource(pc, gpio_np, "gpio"); + if (IS_ERR(pc->reg_gpio)) { + dev_err(pc->dev, "gpio registers not found\n"); + return PTR_ERR(pc->reg_gpio); } return 0; diff --git a/drivers/pinctrl/meson/pinctrl-meson.h b/drivers/pinctrl/meson/pinctrl-meson.h index d89442ea4a4d..98b5080650c1 100644 --- a/drivers/pinctrl/meson/pinctrl-meson.h +++ b/drivers/pinctrl/meson/pinctrl-meson.h @@ -95,54 +95,17 @@ struct meson_bank { struct meson_reg_desc regs[NUM_REG]; }; -/** - * struct meson_domain_data - domain platform data - * - * @name: name of the domain - * @banks: set of banks belonging to the domain - * @num_banks: number of banks in the domain - */ -struct meson_domain_data { - const char *name; - struct meson_bank *banks; - unsigned int num_banks; - unsigned int pin_base; - unsigned int num_pins; -}; - -/** - * struct meson_domain - * - * @reg_mux: registers for mux settings - * @reg_pullen: registers for pull-enable settings - * @reg_pull: registers for pull settings - * @reg_gpio: registers for gpio settings - * @chip: gpio chip associated with the domain - * @data; platform data for the domain - * @node: device tree node for the domain - * - * A domain represents a set of banks controlled by the same set of - * registers. - */ -struct meson_domain { - struct regmap *reg_mux; - struct regmap *reg_pullen; - struct regmap *reg_pull; - struct regmap *reg_gpio; - - struct gpio_chip chip; - struct meson_domain_data *data; - struct device_node *of_node; -}; - struct meson_pinctrl_data { + const char *name; const struct pinctrl_pin_desc *pins; struct meson_pmx_group *groups; struct meson_pmx_func *funcs; - struct meson_domain_data *domain_data; + unsigned int pin_base; unsigned int num_pins; unsigned int num_groups; unsigned int num_funcs; + struct meson_bank *banks; + unsigned int num_banks; }; struct meson_pinctrl { @@ -150,7 +113,12 @@ struct meson_pinctrl { struct pinctrl_dev *pcdev; struct pinctrl_desc desc; struct meson_pinctrl_data *data; - struct meson_domain *domain; + struct regmap *reg_mux; + struct regmap *reg_pullen; + struct regmap *reg_pull; + struct regmap *reg_gpio; + struct gpio_chip chip; + struct device_node *of_node; }; #define PIN(x, b) (b + x) diff --git a/drivers/pinctrl/meson/pinctrl-meson8.c b/drivers/pinctrl/meson/pinctrl-meson8.c index 32de191e0807..07f1cb21c1b8 100644 --- a/drivers/pinctrl/meson/pinctrl-meson8.c +++ b/drivers/pinctrl/meson/pinctrl-meson8.c @@ -931,38 +931,28 @@ static struct meson_bank meson8_aobus_banks[] = { BANK("AO", PIN(GPIOAO_0, AO_OFF), PIN(GPIO_TEST_N, AO_OFF), 0, 0, 0, 16, 0, 0, 0, 16, 1, 0), }; -static struct meson_domain_data meson8_cbus_domain_data = { +struct meson_pinctrl_data meson8_cbus_pinctrl_data = { .name = "cbus-banks", - .banks = meson8_cbus_banks, - .num_banks = ARRAY_SIZE(meson8_cbus_banks), .pin_base = 0, - .num_pins = 120, -}; - -static struct meson_domain_data meson8_aobus_domain_data = { - .name = "ao-bank", - .banks = meson8_aobus_banks, - .num_banks = ARRAY_SIZE(meson8_aobus_banks), - .pin_base = 120, - .num_pins = 16, -}; - -struct meson_pinctrl_data meson8_cbus_pinctrl_data = { .pins = meson8_cbus_pins, .groups = meson8_cbus_groups, .funcs = meson8_cbus_functions, - .domain_data = &meson8_cbus_domain_data, + .banks = meson8_cbus_banks, .num_pins = ARRAY_SIZE(meson8_cbus_pins), .num_groups = ARRAY_SIZE(meson8_cbus_groups), .num_funcs = ARRAY_SIZE(meson8_cbus_functions), + .num_banks = ARRAY_SIZE(meson8_cbus_banks), }; struct meson_pinctrl_data meson8_aobus_pinctrl_data = { + .name = "ao-bank", + .pin_base = 120, .pins = meson8_aobus_pins, .groups = meson8_aobus_groups, .funcs = meson8_aobus_functions, - .domain_data = &meson8_aobus_domain_data, + .banks = meson8_aobus_banks, .num_pins = ARRAY_SIZE(meson8_aobus_pins), .num_groups = ARRAY_SIZE(meson8_aobus_groups), .num_funcs = ARRAY_SIZE(meson8_aobus_functions), + .num_banks = ARRAY_SIZE(meson8_aobus_banks), }; diff --git a/drivers/pinctrl/meson/pinctrl-meson8b.c b/drivers/pinctrl/meson/pinctrl-meson8b.c index 874f2edf8be3..76f077f18193 100644 --- a/drivers/pinctrl/meson/pinctrl-meson8b.c +++ b/drivers/pinctrl/meson/pinctrl-meson8b.c @@ -896,38 +896,28 @@ static struct meson_bank meson8b_aobus_banks[] = { BANK("AO", PIN(GPIOAO_0, AO_OFF), PIN(GPIO_TEST_N, AO_OFF), 0, 0, 0, 16, 0, 0, 0, 16, 1, 0), }; -static struct meson_domain_data meson8b_cbus_domain_data = { +struct meson_pinctrl_data meson8b_cbus_pinctrl_data = { .name = "cbus-banks", - .banks = meson8b_cbus_banks, - .num_banks = ARRAY_SIZE(meson8b_cbus_banks), .pin_base = 0, - .num_pins = 130, -}; - -static struct meson_domain_data meson8b_aobus_domain_data = { - .name = "aobus-banks", - .banks = meson8b_aobus_banks, - .num_banks = ARRAY_SIZE(meson8b_aobus_banks), - .pin_base = 130, - .num_pins = 16, -}; - -struct meson_pinctrl_data meson8b_cbus_pinctrl_data = { .pins = meson8b_cbus_pins, .groups = meson8b_cbus_groups, .funcs = meson8b_cbus_functions, - .domain_data = &meson8b_cbus_domain_data, + .banks = meson8b_cbus_banks, .num_pins = ARRAY_SIZE(meson8b_cbus_pins), .num_groups = ARRAY_SIZE(meson8b_cbus_groups), .num_funcs = ARRAY_SIZE(meson8b_cbus_functions), + .num_banks = ARRAY_SIZE(meson8b_cbus_banks), }; struct meson_pinctrl_data meson8b_aobus_pinctrl_data = { + .name = "aobus-banks", + .pin_base = 130, .pins = meson8b_aobus_pins, .groups = meson8b_aobus_groups, .funcs = meson8b_aobus_functions, - .domain_data = &meson8b_aobus_domain_data, + .banks = meson8b_aobus_banks, .num_pins = ARRAY_SIZE(meson8b_aobus_pins), .num_groups = ARRAY_SIZE(meson8b_aobus_groups), .num_funcs = ARRAY_SIZE(meson8b_aobus_functions), + .num_banks = ARRAY_SIZE(meson8b_aobus_banks), }; -- cgit 1.4.1 From 26fecf0b21d17d17ba98fd64e8ac5a5c87ffb0d5 Mon Sep 17 00:00:00 2001 From: perr perr Date: Tue, 16 Aug 2016 18:45:29 +0800 Subject: pinctrl: exynos: remove duplicate calls in irq handler Because chained_irq_enter() has already called chip->irq_mask() and chip->irq_ack(), also chained_irq_exit() will call chip->irq_unmask(), so it's not necessary to call chip->irq_*() here. Signed-off-by: Perr Zhang Acked-by: Tomasz Figa Reviewed-by: Krzysztof Kozlowski [Hand-edited from whitespace damaged patch] Signed-off-by: Linus Walleij --- drivers/pinctrl/samsung/pinctrl-exynos.c | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.c b/drivers/pinctrl/samsung/pinctrl-exynos.c index 051b5bf701a8..d32fa2b5ff82 100644 --- a/drivers/pinctrl/samsung/pinctrl-exynos.c +++ b/drivers/pinctrl/samsung/pinctrl-exynos.c @@ -428,14 +428,10 @@ static void exynos_irq_eint0_15(struct irq_desc *desc) int eint_irq; chained_irq_enter(chip, desc); - chip->irq_mask(&desc->irq_data); - - if (chip->irq_ack) - chip->irq_ack(&desc->irq_data); eint_irq = irq_linear_revmap(bank->irq_domain, eintd->irq); generic_handle_irq(eint_irq); - chip->irq_unmask(&desc->irq_data); + chained_irq_exit(chip, desc); } -- cgit 1.4.1 From a1edf87f217322d988a9c4aca5883b052f114c0d Mon Sep 17 00:00:00 2001 From: LABBE Corentin Date: Tue, 16 Aug 2016 10:36:53 +0200 Subject: pinctrl: palmas: fix a possible NULL dereference of_match_device could return NULL, and so cause a NULL pointer dereference later at line 1009: pinctrl_data = match->data; For fixing this problem, we use of_device_get_match_data(), this will simplify the code a little by using a standard function for getting the match data. Reported-by: coverity (CID 1324136) Signed-off-by: LABBE Corentin Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-palmas.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/pinctrl/pinctrl-palmas.c b/drivers/pinctrl/pinctrl-palmas.c index 8edb3f8c72c8..a30146da7ffd 100644 --- a/drivers/pinctrl/pinctrl-palmas.c +++ b/drivers/pinctrl/pinctrl-palmas.c @@ -1004,9 +1004,7 @@ static int palmas_pinctrl_probe(struct platform_device *pdev) bool enable_dvfs2 = false; if (pdev->dev.of_node) { - const struct of_device_id *match; - match = of_match_device(palmas_pinctrl_of_match, &pdev->dev); - pinctrl_data = match->data; + pinctrl_data = of_device_get_match_data(&pdev->dev); enable_dvfs1 = of_property_read_bool(pdev->dev.of_node, "ti,palmas-enable-dvfs1"); enable_dvfs2 = of_property_read_bool(pdev->dev.of_node, -- cgit 1.4.1 From 35398f7b38ab7e8a01fddd374b597c0c8d2d9d69 Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Sat, 20 Aug 2016 11:54:19 +0200 Subject: pinctrl: amlogic: gxbb: add the IR remote input pin This adds the IR remote receiver to the AO domain devices. Signed-off-by: Martin Blumenstingl Reviewed-by: Kevin Hilman Signed-off-by: Linus Walleij --- drivers/pinctrl/meson/pinctrl-meson-gxbb.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/pinctrl/meson/pinctrl-meson-gxbb.c b/drivers/pinctrl/meson/pinctrl-meson-gxbb.c index 233c9c85bbd9..7eeb0530aa5e 100644 --- a/drivers/pinctrl/meson/pinctrl-meson-gxbb.c +++ b/drivers/pinctrl/meson/pinctrl-meson-gxbb.c @@ -225,6 +225,8 @@ static const unsigned int i2c_sda_ao_pins[] = {PIN(GPIOAO_5, 0) }; static const unsigned int i2c_slave_sck_ao_pins[] = {PIN(GPIOAO_4, 0) }; static const unsigned int i2c_slave_sda_ao_pins[] = {PIN(GPIOAO_5, 0) }; +static const unsigned int remote_input_ao_pins[] = {PIN(GPIOAO_7, 0) }; + static struct meson_pmx_group meson_gxbb_periphs_groups[] = { GPIO_GROUP(GPIOZ_0, EE_OFF), GPIO_GROUP(GPIOZ_1, EE_OFF), @@ -432,6 +434,7 @@ static struct meson_pmx_group meson_gxbb_aobus_groups[] = { GROUP(i2c_sda_ao, 0, 5), GROUP(i2c_slave_sck_ao, 0, 2), GROUP(i2c_slave_sda_ao, 0, 1), + GROUP(remote_input_ao, 0, 0), }; static const char * const gpio_periphs_groups[] = { @@ -521,6 +524,10 @@ static const char * const i2c_slave_ao_groups[] = { "i2c_slave_sdk_ao", "i2c_slave_sda_ao", }; +static const char * const remote_input_ao_groups[] = { + "remote_input_ao", +}; + static struct meson_pmx_func meson_gxbb_periphs_functions[] = { FUNCTION(gpio_periphs), FUNCTION(emmc), @@ -537,6 +544,7 @@ static struct meson_pmx_func meson_gxbb_aobus_functions[] = { FUNCTION(uart_ao_b), FUNCTION(i2c_ao), FUNCTION(i2c_slave_ao), + FUNCTION(remote_input_ao), }; static struct meson_bank meson_gxbb_periphs_banks[] = { -- cgit 1.4.1 From a9a5a443d86a7795ad00f74e6715bfca156bbb2d Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Tue, 23 Aug 2016 13:25:07 +0200 Subject: pinctrl: meson-gxbb: add pins for PWM Add support for PWM pins, for EE and AO domains. Signed-off-by: Neil Armstrong Signed-off-by: Linus Walleij --- drivers/pinctrl/meson/pinctrl-meson-gxbb.c | 79 ++++++++++++++++++++++++++++++ 1 file changed, 79 insertions(+) diff --git a/drivers/pinctrl/meson/pinctrl-meson-gxbb.c b/drivers/pinctrl/meson/pinctrl-meson-gxbb.c index 7eeb0530aa5e..9ba9172dd84a 100644 --- a/drivers/pinctrl/meson/pinctrl-meson-gxbb.c +++ b/drivers/pinctrl/meson/pinctrl-meson-gxbb.c @@ -193,6 +193,14 @@ static const unsigned int eth_txd1_pins[] = { PIN(GPIOZ_11, EE_OFF) }; static const unsigned int eth_txd2_pins[] = { PIN(GPIOZ_12, EE_OFF) }; static const unsigned int eth_txd3_pins[] = { PIN(GPIOZ_13, EE_OFF) }; +static const unsigned int pwm_a_x_pins[] = { PIN(GPIOX_6, EE_OFF) }; +static const unsigned int pwm_a_y_pins[] = { PIN(GPIOY_16, EE_OFF) }; +static const unsigned int pwm_b_pins[] = { PIN(GPIODV_29, EE_OFF) }; +static const unsigned int pwm_d_pins[] = { PIN(GPIODV_28, EE_OFF) }; +static const unsigned int pwm_e_pins[] = { PIN(GPIOX_19, EE_OFF) }; +static const unsigned int pwm_f_x_pins[] = { PIN(GPIOX_7, EE_OFF) }; +static const unsigned int pwm_f_y_pins[] = { PIN(GPIOY_15, EE_OFF) }; + static const struct pinctrl_pin_desc meson_gxbb_aobus_pins[] = { MESON_PIN(GPIOAO_0, 0), MESON_PIN(GPIOAO_1, 0), @@ -227,6 +235,11 @@ static const unsigned int i2c_slave_sda_ao_pins[] = {PIN(GPIOAO_5, 0) }; static const unsigned int remote_input_ao_pins[] = {PIN(GPIOAO_7, 0) }; +static const unsigned int pwm_ao_a_3_pins[] = { PIN(GPIOAO_3, 0) }; +static const unsigned int pwm_ao_a_6_pins[] = { PIN(GPIOAO_6, 0) }; +static const unsigned int pwm_ao_a_12_pins[] = { PIN(GPIOAO_12, 0) }; +static const unsigned int pwm_ao_b_pins[] = { PIN(GPIOAO_13, 0) }; + static struct meson_pmx_group meson_gxbb_periphs_groups[] = { GPIO_GROUP(GPIOZ_0, EE_OFF), GPIO_GROUP(GPIOZ_1, EE_OFF), @@ -361,12 +374,17 @@ static struct meson_pmx_group meson_gxbb_periphs_groups[] = { GROUP(uart_rx_a, 4, 12), GROUP(uart_cts_a, 4, 11), GROUP(uart_rts_a, 4, 10), + GROUP(pwm_a_x, 3, 17), + GROUP(pwm_e, 2, 30), + GROUP(pwm_f_x, 3, 18), /* Bank Y */ GROUP(uart_cts_c, 1, 19), GROUP(uart_rts_c, 1, 18), GROUP(uart_tx_c, 1, 17), GROUP(uart_rx_c, 1, 16), + GROUP(pwm_a_y, 1, 21), + GROUP(pwm_f_y, 1, 20), /* Bank Z */ GROUP(eth_mdio, 6, 1), @@ -389,6 +407,8 @@ static struct meson_pmx_group meson_gxbb_periphs_groups[] = { GROUP(uart_rx_b, 2, 28), GROUP(uart_cts_b, 2, 27), GROUP(uart_rts_b, 2, 26), + GROUP(pwm_b, 3, 21), + GROUP(pwm_d, 3, 20), /* Bank BOOT */ GROUP(emmc_nand_d07, 4, 30), @@ -435,6 +455,10 @@ static struct meson_pmx_group meson_gxbb_aobus_groups[] = { GROUP(i2c_slave_sck_ao, 0, 2), GROUP(i2c_slave_sda_ao, 0, 1), GROUP(remote_input_ao, 0, 0), + GROUP(pwm_ao_a_3, 0, 22), + GROUP(pwm_ao_a_6, 0, 18), + GROUP(pwm_ao_a_12, 0, 17), + GROUP(pwm_ao_b, 0, 3), }; static const char * const gpio_periphs_groups[] = { @@ -502,6 +526,34 @@ static const char * const eth_groups[] = { "eth_txd0", "eth_txd1", "eth_txd2", "eth_txd3", }; +static const char * const pwm_a_x_groups[] = { + "pwm_a_x", +}; + +static const char * const pwm_a_y_groups[] = { + "pwm_a_y", +}; + +static const char * const pwm_b_groups[] = { + "pwm_b", +}; + +static const char * const pwm_d_groups[] = { + "pwm_d", +}; + +static const char * const pwm_e_groups[] = { + "pwm_e", +}; + +static const char * const pwm_f_x_groups[] = { + "pwm_f_x", +}; + +static const char * const pwm_f_y_groups[] = { + "pwm_f_y", +}; + static const char * const gpio_aobus_groups[] = { "GPIOAO_0", "GPIOAO_1", "GPIOAO_2", "GPIOAO_3", "GPIOAO_4", "GPIOAO_5", "GPIOAO_6", "GPIOAO_7", "GPIOAO_8", "GPIOAO_9", @@ -528,6 +580,22 @@ static const char * const remote_input_ao_groups[] = { "remote_input_ao", }; +static const char * const pwm_ao_a_3_groups[] = { + "pwm_ao_a_3", +}; + +static const char * const pwm_ao_a_6_groups[] = { + "pwm_ao_a_6", +}; + +static const char * const pwm_ao_a_12_groups[] = { + "pwm_ao_a_12", +}; + +static const char * const pwm_ao_b_groups[] = { + "pwm_ao_b", +}; + static struct meson_pmx_func meson_gxbb_periphs_functions[] = { FUNCTION(gpio_periphs), FUNCTION(emmc), @@ -536,6 +604,13 @@ static struct meson_pmx_func meson_gxbb_periphs_functions[] = { FUNCTION(uart_b), FUNCTION(uart_c), FUNCTION(eth), + FUNCTION(pwm_a_x), + FUNCTION(pwm_a_y), + FUNCTION(pwm_b), + FUNCTION(pwm_d), + FUNCTION(pwm_e), + FUNCTION(pwm_f_x), + FUNCTION(pwm_f_y), }; static struct meson_pmx_func meson_gxbb_aobus_functions[] = { @@ -545,6 +620,10 @@ static struct meson_pmx_func meson_gxbb_aobus_functions[] = { FUNCTION(i2c_ao), FUNCTION(i2c_slave_ao), FUNCTION(remote_input_ao), + FUNCTION(pwm_ao_a_3), + FUNCTION(pwm_ao_a_6), + FUNCTION(pwm_ao_a_12), + FUNCTION(pwm_ao_b), }; static struct meson_bank meson_gxbb_periphs_banks[] = { -- cgit 1.4.1 From 4394a639338bd5e0973d61294a69196cd580ab83 Mon Sep 17 00:00:00 2001 From: Paul Gortmaker Date: Tue, 23 Aug 2016 17:19:39 -0400 Subject: pinctrl: mediatek: make mtk-common explicitly non-modular The Makefile currently controlling compilation of this code is: drivers/pinctrl/mediatek/pinctrl-mtk-common.o ---> drivers/pinctrl/mediatek/Makefile:obj-y += pinctrl-mtk-common.o ...meaning that it currently is not being built as a module by anyone. Lets remove the couple traces of modular infrastructure use, so that when reading the driver there is no doubt it is builtin-only. We delete the MODULE_LICENSE tag etc. since all that information is already contained at the top of the file in the comments. We don't replace module.h with init.h since the file doesn't need that. Cc: Linus Walleij Cc: Hongzhou Yang Cc: linux-gpio@vger.kernel.org Signed-off-by: Paul Gortmaker Signed-off-by: Linus Walleij --- drivers/pinctrl/mediatek/pinctrl-mtk-common.c | 5 ----- 1 file changed, 5 deletions(-) diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c index ce554e0d6979..ba2b03dbfe3b 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c @@ -15,7 +15,6 @@ #include #include -#include #include #include #include @@ -1496,7 +1495,3 @@ chip_error: gpiochip_remove(pctl->chip); return ret; } - -MODULE_LICENSE("GPL"); -MODULE_DESCRIPTION("MediaTek Pinctrl Driver"); -MODULE_AUTHOR("Hongzhou Yang "); -- cgit 1.4.1 From 8b51fad0e975a913be6db1d3d06981232163d182 Mon Sep 17 00:00:00 2001 From: Paul Gortmaker Date: Tue, 23 Aug 2016 17:19:40 -0400 Subject: pinctrl: nomadik: make abx500 explicitly non-modular The Kconfig currently controlling compilation of this code is: config PINCTRL_ABX500 bool "ST-Ericsson ABx500 family Mixed Signal Circuit gpio functions" ...meaning that it currently is not being built as a module by anyone. Lets remove the couple traces of modular infrastructure use, so that when reading the driver there is no doubt it is builtin-only. Note that MODULE_ALIAS is a no-op for non-modular code. We also delete the MODULE_LICENSE tag etc. since all that information was (or is now) contained at the top of the file in the comments. Cc: Linus Walleij Cc: Alessandro Rubini Cc: Patrice Chotard Cc: linux-gpio@vger.kernel.org Signed-off-by: Paul Gortmaker Signed-off-by: Linus Walleij --- drivers/pinctrl/nomadik/pinctrl-abx500.c | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/drivers/pinctrl/nomadik/pinctrl-abx500.c b/drivers/pinctrl/nomadik/pinctrl-abx500.c index 7d343c22c90c..f95001bc1d58 100644 --- a/drivers/pinctrl/nomadik/pinctrl-abx500.c +++ b/drivers/pinctrl/nomadik/pinctrl-abx500.c @@ -4,6 +4,8 @@ * Author: Patrice Chotard * License terms: GNU General Public License (GPL) version 2 * + * Driver allows to use AxB5xx unused pins to be used as GPIO + * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. @@ -12,7 +14,6 @@ #include #include #include -#include #include #include #include @@ -1269,8 +1270,3 @@ static int __init abx500_gpio_init(void) return platform_driver_register(&abx500_gpio_driver); } core_initcall(abx500_gpio_init); - -MODULE_AUTHOR("Patrice Chotard "); -MODULE_DESCRIPTION("Driver allows to use AxB5xx unused pins to be used as GPIO"); -MODULE_ALIAS("platform:abx500-gpio"); -MODULE_LICENSE("GPL v2"); -- cgit 1.4.1 From 6d6cc0d89a0cf4d7310d1447db0e6ae2467925f4 Mon Sep 17 00:00:00 2001 From: Paul Gortmaker Date: Tue, 23 Aug 2016 17:19:41 -0400 Subject: pinctrl: nomadik: make core support explicitly non-modular The Kconfig currently controlling compilation of this code is: drivers/pinctrl/nomadik/Kconfig:config PINCTRL_NOMADIK drivers/pinctrl/nomadik/Kconfig: bool "Nomadik pin controller driver" ...meaning that it currently is not being built as a module by anyone. Lets remove the couple traces of modular infrastructure use, so that when reading the driver there is no doubt it is builtin-only. We delete the MODULE_LICENSE tag etc. since all that information is already contained at the top of the file in the comments. Cc: Linus Walleij Cc: Alessandro Rubini Cc: linux-gpio@vger.kernel.org Signed-off-by: Paul Gortmaker Signed-off-by: Linus Walleij --- drivers/pinctrl/nomadik/pinctrl-nomadik.c | 5 ----- 1 file changed, 5 deletions(-) diff --git a/drivers/pinctrl/nomadik/pinctrl-nomadik.c b/drivers/pinctrl/nomadik/pinctrl-nomadik.c index 6f2e1da11b1e..205fb399268a 100644 --- a/drivers/pinctrl/nomadik/pinctrl-nomadik.c +++ b/drivers/pinctrl/nomadik/pinctrl-nomadik.c @@ -11,7 +11,6 @@ * published by the Free Software Foundation. */ #include -#include #include #include #include @@ -1983,7 +1982,3 @@ static int __init nmk_pinctrl_init(void) return platform_driver_register(&nmk_pinctrl_driver); } core_initcall(nmk_pinctrl_init); - -MODULE_AUTHOR("Prafulla WADASKAR and Alessandro Rubini"); -MODULE_DESCRIPTION("Nomadik GPIO Driver"); -MODULE_LICENSE("GPL"); -- cgit 1.4.1 From 2f4362040be123eb09c26e273d2ac95d7ced7737 Mon Sep 17 00:00:00 2001 From: Paul Gortmaker Date: Tue, 23 Aug 2016 17:19:42 -0400 Subject: pinctrl: rockchip: make it explicitly non-modular The Kconfig currently controlling compilation of this code is: drivers/pinctrl/Kconfig:config PINCTRL_ROCKCHIP drivers/pinctrl/Kconfig: bool ...meaning that it currently is not being built as a module by anyone. Lets remove the couple traces of modular infrastructure use, so that when reading the driver there is no doubt it is builtin-only. Note that MODULE_DEVICE_TABLE is a no-op for non-modular code. We also delete the MODULE_LICENSE tag etc. since all that information is already contained at the top of the file in the comments. Cc: Linus Walleij Cc: Heiko Stuebner Cc: linux-gpio@vger.kernel.org Cc: linux-rockchip@lists.infradead.org Signed-off-by: Paul Gortmaker Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-rockchip.c | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c index 44902c63f507..49bf7dcb7ed8 100644 --- a/drivers/pinctrl/pinctrl-rockchip.c +++ b/drivers/pinctrl/pinctrl-rockchip.c @@ -23,7 +23,7 @@ * GNU General Public License for more details. */ -#include +#include #include #include #include @@ -2704,7 +2704,6 @@ static const struct of_device_id rockchip_pinctrl_dt_match[] = { .data = (void *)&rk3399_pin_ctrl }, {}, }; -MODULE_DEVICE_TABLE(of, rockchip_pinctrl_dt_match); static struct platform_driver rockchip_pinctrl_driver = { .probe = rockchip_pinctrl_probe, @@ -2720,7 +2719,3 @@ static int __init rockchip_pinctrl_drv_register(void) return platform_driver_register(&rockchip_pinctrl_driver); } postcore_initcall(rockchip_pinctrl_drv_register); - -MODULE_AUTHOR("Heiko Stuebner "); -MODULE_DESCRIPTION("Rockchip pinctrl driver"); -MODULE_LICENSE("GPL v2"); -- cgit 1.4.1 From 37e70b6a35e73d884096a2dbc976fae454829533 Mon Sep 17 00:00:00 2001 From: Paul Gortmaker Date: Tue, 23 Aug 2016 17:19:43 -0400 Subject: pinctrl: sirf: make atlas7 explicitly non-modular The Makefile currently controlling compilation of this code is: drivers/pinctrl/sirf/pinctrl-atlas7.o ---> drivers/pinctrl/sirf/Makefile:obj-y += pinctrl-atlas7.o ...meaning that it currently is not being built as a module by anyone. Lets remove the couple traces of modular infrastructure use, so that when reading the driver there is no doubt it is builtin-only. We delete the MODULE_LICENSE tag etc. since all that information is already contained at the top of the file in the comments. Cc: Linus Walleij Cc: Barry Song Cc: linux-gpio@vger.kernel.org Signed-off-by: Paul Gortmaker Signed-off-by: Linus Walleij --- drivers/pinctrl/sirf/pinctrl-atlas7.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/drivers/pinctrl/sirf/pinctrl-atlas7.c b/drivers/pinctrl/sirf/pinctrl-atlas7.c index 19952f73fa8c..7f3041697813 100644 --- a/drivers/pinctrl/sirf/pinctrl-atlas7.c +++ b/drivers/pinctrl/sirf/pinctrl-atlas7.c @@ -7,7 +7,7 @@ * Licensed under GPLv2 or later. */ -#include +#include #include #include #include @@ -6158,6 +6158,3 @@ static int __init atlas7_gpio_init(void) return platform_driver_register(&atlas7_gpio_driver); } subsys_initcall(atlas7_gpio_init); - -MODULE_DESCRIPTION("SIRFSOC Atlas7 pin control driver"); -MODULE_LICENSE("GPL"); -- cgit 1.4.1 From a9784e56aa106959ee695de8bf7c546b9bd6ad14 Mon Sep 17 00:00:00 2001 From: Paul Gortmaker Date: Tue, 23 Aug 2016 17:19:44 -0400 Subject: pinctrl: sirf: make core support explicitly non-modular The Makefile currently controlling compilation of this code is: drivers/pinctrl/sirf/pinctrl-sirf.o --> drivers/pinctrl/sirf/Makefile:obj-y += pinctrl-sirf.o ...meaning that it currently is not being built as a module by anyone. Lets remove the couple traces of modular infrastructure use, so that when reading the driver there is no doubt it is builtin-only. We also delete the MODULE_LICENSE tag etc. since all that information was (or is now) contained at the top of the file in the comments. Cc: Linus Walleij Cc: Rongjun Ying Cc: Yuping Luo Cc: Barry Song Cc: linux-gpio@vger.kernel.org Signed-off-by: Paul Gortmaker Signed-off-by: Linus Walleij --- drivers/pinctrl/sirf/pinctrl-sirf.c | 12 +++++------- 1 file changed, 5 insertions(+), 7 deletions(-) diff --git a/drivers/pinctrl/sirf/pinctrl-sirf.c b/drivers/pinctrl/sirf/pinctrl-sirf.c index 762c0c9c1278..0df72be60704 100644 --- a/drivers/pinctrl/sirf/pinctrl-sirf.c +++ b/drivers/pinctrl/sirf/pinctrl-sirf.c @@ -1,6 +1,11 @@ /* * pinmux driver for CSR SiRFprimaII * + * Authors: + * Rongjun Ying + * Yuping Luo + * Barry Song + * * Copyright (c) 2011 - 2014 Cambridge Silicon Radio Limited, a CSR plc group * company. * @@ -8,7 +13,6 @@ */ #include -#include #include #include #include @@ -884,9 +888,3 @@ static int __init sirfsoc_gpio_init(void) return sirfsoc_gpio_probe(np); } subsys_initcall(sirfsoc_gpio_init); - -MODULE_AUTHOR("Rongjun Ying "); -MODULE_AUTHOR("Yuping Luo "); -MODULE_AUTHOR("Barry Song "); -MODULE_DESCRIPTION("SIRFSOC pin control driver"); -MODULE_LICENSE("GPL"); -- cgit 1.4.1 From a2d16a21834848226919f3aca37307ce214f6073 Mon Sep 17 00:00:00 2001 From: Vladimir Zapolskiy Date: Sat, 20 Aug 2016 01:05:37 +0300 Subject: pinctrl: imx: output one pin/config pair per line in pinconf-groups cat /sys/kernel/debug/pinctrl/${pinctrl}/pinconf-groups output is hardly readable, if a pin group contains more than one pin the output is glued and looks like this: MX6Q_PAD_SD1_DAT0: 0x17071MX6Q_PAD_SD1_CMD: 0x17071MX6Q_PAD_SD1_CLK: 0x17071 Add two space indentation and a new line separator to improve readability of the output. Signed-off-by: Vladimir Zapolskiy Acked-by: Shawn Guo Signed-off-by: Linus Walleij --- drivers/pinctrl/freescale/pinctrl-imx.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/freescale/pinctrl-imx.c b/drivers/pinctrl/freescale/pinctrl-imx.c index 71391757938b..56fd88013850 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx.c +++ b/drivers/pinctrl/freescale/pinctrl-imx.c @@ -501,7 +501,7 @@ static void imx_pinconf_group_dbg_show(struct pinctrl_dev *pctldev, ret = imx_pinconf_get(pctldev, pin->pin, &config); if (ret) return; - seq_printf(s, "%s: 0x%lx", name, config); + seq_printf(s, " %s: 0x%lx\n", name, config); } } -- cgit 1.4.1 From b8d74b291ff01cfe3799c4118127d5e08763369d Mon Sep 17 00:00:00 2001 From: Daniel Glöckner Date: Thu, 25 Aug 2016 15:48:31 +0200 Subject: pinctrl: zynq: fix typo in sdio1_3_grp pin list MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit It contains pin 50 instead of pin 40. Signed-off-by: Daniel Glöckner Reviewed-by: Sören Brinkmann Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-zynq.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/pinctrl-zynq.c b/drivers/pinctrl/pinctrl-zynq.c index 7afdbede6823..e0ecffcbe11f 100644 --- a/drivers/pinctrl/pinctrl-zynq.c +++ b/drivers/pinctrl/pinctrl-zynq.c @@ -233,7 +233,7 @@ static const unsigned int sdio0_2_pins[] = {40, 41, 42, 43, 44, 45}; static const unsigned int sdio1_0_pins[] = {10, 11, 12, 13, 14, 15}; static const unsigned int sdio1_1_pins[] = {22, 23, 24, 25, 26, 27}; static const unsigned int sdio1_2_pins[] = {34, 35, 36, 37, 38, 39}; -static const unsigned int sdio1_3_pins[] = {46, 47, 48, 49, 40, 51}; +static const unsigned int sdio1_3_pins[] = {46, 47, 48, 49, 50, 51}; static const unsigned int sdio0_emio_wp_pins[] = {54}; static const unsigned int sdio0_emio_cd_pins[] = {55}; static const unsigned int sdio1_emio_wp_pins[] = {56}; -- cgit 1.4.1 From 29885a656511829d5e8f69b237de47a6c23f47fa Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Sun, 28 Aug 2016 18:47:24 +0200 Subject: pinctrl: meson-gxbb: add the pins for the SDIO/sd_emmc_a controller sd_emmc_a is used a controller for the SDIO modules. This adds the pin configuration for the SDIO controller. Signed-off-by: Martin Blumenstingl Signed-off-by: Linus Walleij --- drivers/pinctrl/meson/pinctrl-meson-gxbb.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/drivers/pinctrl/meson/pinctrl-meson-gxbb.c b/drivers/pinctrl/meson/pinctrl-meson-gxbb.c index 9ba9172dd84a..b4e2e9f15818 100644 --- a/drivers/pinctrl/meson/pinctrl-meson-gxbb.c +++ b/drivers/pinctrl/meson/pinctrl-meson-gxbb.c @@ -163,6 +163,13 @@ static const unsigned int sdcard_d3_pins[] = { PIN(CARD_4, EE_OFF) }; static const unsigned int sdcard_cmd_pins[] = { PIN(CARD_3, EE_OFF) }; static const unsigned int sdcard_clk_pins[] = { PIN(CARD_2, EE_OFF) }; +static const unsigned int sdio_d0_pins[] = { PIN(GPIOX_0, EE_OFF) }; +static const unsigned int sdio_d1_pins[] = { PIN(GPIOX_1, EE_OFF) }; +static const unsigned int sdio_d2_pins[] = { PIN(GPIOX_2, EE_OFF) }; +static const unsigned int sdio_d3_pins[] = { PIN(GPIOX_3, EE_OFF) }; +static const unsigned int sdio_cmd_pins[] = { PIN(GPIOX_4, EE_OFF) }; +static const unsigned int sdio_clk_pins[] = { PIN(GPIOX_5, EE_OFF) }; + static const unsigned int uart_tx_a_pins[] = { PIN(GPIOX_12, EE_OFF) }; static const unsigned int uart_rx_a_pins[] = { PIN(GPIOX_13, EE_OFF) }; static const unsigned int uart_cts_a_pins[] = { PIN(GPIOX_14, EE_OFF) }; @@ -370,6 +377,12 @@ static struct meson_pmx_group meson_gxbb_periphs_groups[] = { GPIO_GROUP(GPIO_TEST_N, EE_OFF), /* Bank X */ + GROUP(sdio_d0, 8, 5), + GROUP(sdio_d1, 8, 4), + GROUP(sdio_d2, 8, 3), + GROUP(sdio_d3, 8, 2), + GROUP(sdio_cmd, 8, 1), + GROUP(sdio_clk, 8, 0), GROUP(uart_tx_a, 4, 13), GROUP(uart_rx_a, 4, 12), GROUP(uart_cts_a, 4, 11), @@ -507,6 +520,11 @@ static const char * const sdcard_groups[] = { "sdcard_cmd", "sdcard_clk", }; +static const char * const sdio_groups[] = { + "sdio_d0", "sdio_d1", "sdio_d2", "sdio_d3", + "sdio_cmd", "sdio_clk", +}; + static const char * const uart_a_groups[] = { "uart_tx_a", "uart_rx_a", "uart_cts_a", "uart_rts_a", }; @@ -600,6 +618,7 @@ static struct meson_pmx_func meson_gxbb_periphs_functions[] = { FUNCTION(gpio_periphs), FUNCTION(emmc), FUNCTION(sdcard), + FUNCTION(sdio), FUNCTION(uart_a), FUNCTION(uart_b), FUNCTION(uart_c), -- cgit 1.4.1 From 5f714700b1892f8d67495567f16c63ad7b20d6b3 Mon Sep 17 00:00:00 2001 From: Andrew Jeffery Date: Tue, 30 Aug 2016 17:24:22 +0930 Subject: pinctrl: dt-bindings: Add documentation for Aspeed pin controllers Outline expectations on the pin controller's relationship with the System Control Unit (SCU) IP through syscon, and document the compatible strings for 4th and 5th generation Aspeed SoC pin controllers. Signed-off-by: Andrew Jeffery Acked-by: Rob Herring Acked-by: Joel Stanley Signed-off-by: Linus Walleij --- .../devicetree/bindings/pinctrl/pinctrl-aspeed.txt | 65 ++++++++++++++++++++++ 1 file changed, 65 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/pinctrl-aspeed.txt diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-aspeed.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-aspeed.txt new file mode 100644 index 000000000000..5e60ad18f147 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-aspeed.txt @@ -0,0 +1,65 @@ +Aspeed Pin Controllers +---------------------- + +The Aspeed SoCs vary in functionality inside a generation but have a common mux +device register layout. + +Required properties: +- compatible : Should be any one of the following: + "aspeed,ast2400-pinctrl" + "aspeed,g4-pinctrl" + "aspeed,ast2500-pinctrl" + "aspeed,g5-pinctrl" + +The pin controller node should be a child of a syscon node with the required +property: +- compatible: "syscon", "simple-mfd" + +Refer to the the bindings described in +Documentation/devicetree/bindings/mfd/syscon.txt + +Subnode Format +-------------- + +The required properties of child nodes are (as defined in pinctrl-bindings): +- function +- groups + +Each function has only one associated pin group. Each group is named by its +function. The following values for the function and groups properties are +supported: + +aspeed,ast2400-pinctrl, aspeed,g4-pinctrl: + +ACPI BMCINT DDCCLK DDCDAT FLACK FLBUSY FLWP GPID0 GPIE0 GPIE2 GPIE4 GPIE6 I2C10 +I2C11 I2C12 I2C13 I2C3 I2C4 I2C5 I2C6 I2C7 I2C8 I2C9 LPCPD LPCPME LPCSMI MDIO1 +MDIO2 NCTS1 NCTS3 NCTS4 NDCD1 NDCD3 NDCD4 NDSR1 NDSR3 NDTR1 NDTR3 NRI1 NRI3 +NRI4 NRTS1 NRTS3 PWM0 PWM1 PWM2 PWM3 PWM4 PWM5 PWM6 PWM7 RGMII1 RMII1 ROM16 +ROM8 ROMCS1 ROMCS2 ROMCS3 ROMCS4 RXD1 RXD3 RXD4 SD1 SGPMI SIOPBI SIOPBO TIMER3 +TIMER5 TIMER6 TIMER7 TIMER8 TXD1 TXD3 TXD4 UART6 VGAHS VGAVS VPI18 VPI24 VPI30 +VPO12 VPO24 + +aspeed,ast2500-pinctrl, aspeed,g5-pinctrl: + +GPID0 GPID2 GPIE0 I2C10 I2C11 I2C12 I2C13 I2C14 I2C3 I2C4 I2C5 I2C6 I2C7 I2C8 +I2C9 MAC1LINK MDIO1 MDIO2 OSCCLK PEWAKE PWM0 PWM1 PWM2 PWM3 PWM4 PWM5 PWM6 PWM7 +RGMII1 RGMII2 RMII1 RMII2 SD1 SPI1 TIMER4 TIMER5 TIMER6 TIMER7 TIMER8 + +Examples: + +syscon: scu@1e6e2000 { + compatible = "syscon", "simple-mfd"; + reg = <0x1e6e2000 0x1a8>; + + pinctrl: pinctrl { + compatible = "aspeed,g4-pinctrl"; + + pinctrl_i2c3_default: i2c3_default { + function = "I2C3"; + groups = "I2C3"; + }; + }; +}; + +Please refer to pinctrl-bindings.txt in this directory for details of the +common pinctrl bindings used by client devices. -- cgit 1.4.1 From 4d3d0e4272d8d660f5f14f5abcf96fb4df1aa94b Mon Sep 17 00:00:00 2001 From: Andrew Jeffery Date: Tue, 30 Aug 2016 17:24:24 +0930 Subject: pinctrl: Add core support for Aspeed SoCs The Aspeed SoCs typically provide more than 200 pins for GPIO and other functions. The signal enabled on a pin is determined on a priority basis, where a given pin can provide a number of different signal types. In addition to the priority levels, the Aspeed pin controllers describe the signal active on a pin by compound logical expressions involving multiple operators, registers and bits. Some difficulty arises as a pin's function bit masks for each priority level are frequently not the same (i.e. we cannot just flip a bit to change from a high to low priority signal), or even in the same register(s). Some configuration bits affect multiple pins, while in other cases the signals for a bus must each be enabled individually. Together, these features give rise to some complexity in the implementation. A more complete description of the complexities is provided in the associated header file. The patch doesn't implement pinctrl/pinmux/pinconf for any particular Aspeed SoC, rather it adds the framework for defining pinmux configurations. Signed-off-by: Andrew Jeffery Reviewed-by: Joel Stanley Signed-off-by: Linus Walleij --- drivers/pinctrl/Kconfig | 1 + drivers/pinctrl/Makefile | 1 + drivers/pinctrl/aspeed/Kconfig | 8 + drivers/pinctrl/aspeed/Makefile | 4 + drivers/pinctrl/aspeed/pinctrl-aspeed.c | 498 ++++++++++++++++++++++++++++ drivers/pinctrl/aspeed/pinctrl-aspeed.h | 569 ++++++++++++++++++++++++++++++++ 6 files changed, 1081 insertions(+) create mode 100644 drivers/pinctrl/aspeed/Kconfig create mode 100644 drivers/pinctrl/aspeed/Makefile create mode 100644 drivers/pinctrl/aspeed/pinctrl-aspeed.c create mode 100644 drivers/pinctrl/aspeed/pinctrl-aspeed.h diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index b3fe1d339632..0e75d94972ba 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -254,6 +254,7 @@ config PINCTRL_ZYNQ help This selects the pinctrl driver for Xilinx Zynq. +source "drivers/pinctrl/aspeed/Kconfig" source "drivers/pinctrl/bcm/Kconfig" source "drivers/pinctrl/berlin/Kconfig" source "drivers/pinctrl/freescale/Kconfig" diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index 8ebd7b8e1621..11bad373dfe0 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -37,6 +37,7 @@ obj-$(CONFIG_PINCTRL_TB10X) += pinctrl-tb10x.o obj-$(CONFIG_PINCTRL_ST) += pinctrl-st.o obj-$(CONFIG_PINCTRL_ZYNQ) += pinctrl-zynq.o +obj-$(CONFIG_ARCH_ASPEED) += aspeed/ obj-y += bcm/ obj-$(CONFIG_PINCTRL_BERLIN) += berlin/ obj-y += freescale/ diff --git a/drivers/pinctrl/aspeed/Kconfig b/drivers/pinctrl/aspeed/Kconfig new file mode 100644 index 000000000000..757002f9be30 --- /dev/null +++ b/drivers/pinctrl/aspeed/Kconfig @@ -0,0 +1,8 @@ +config PINCTRL_ASPEED + bool + depends on (ARCH_ASPEED || COMPILE_TEST) && OF + depends on MFD_SYSCON + select PINMUX + select PINCONF + select GENERIC_PINCONF + select REGMAP_MMIO diff --git a/drivers/pinctrl/aspeed/Makefile b/drivers/pinctrl/aspeed/Makefile new file mode 100644 index 000000000000..a0fc61d31ccf --- /dev/null +++ b/drivers/pinctrl/aspeed/Makefile @@ -0,0 +1,4 @@ +# Aspeed pinctrl support + +ccflags-y += -Woverride-init +obj-$(CONFIG_PINCTRL_ASPEED) += pinctrl-aspeed.o diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed.c b/drivers/pinctrl/aspeed/pinctrl-aspeed.c new file mode 100644 index 000000000000..7d461fc30d3c --- /dev/null +++ b/drivers/pinctrl/aspeed/pinctrl-aspeed.c @@ -0,0 +1,498 @@ +/* + * Copyright (C) 2016 IBM Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include +#include +#include +#include +#include "../core.h" +#include "pinctrl-aspeed.h" + +int aspeed_pinctrl_get_groups_count(struct pinctrl_dev *pctldev) +{ + struct aspeed_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev); + + return pdata->ngroups; +} + +const char *aspeed_pinctrl_get_group_name(struct pinctrl_dev *pctldev, + unsigned int group) +{ + struct aspeed_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev); + + return pdata->groups[group].name; +} + +int aspeed_pinctrl_get_group_pins(struct pinctrl_dev *pctldev, + unsigned int group, const unsigned int **pins, + unsigned int *npins) +{ + struct aspeed_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev); + + *pins = &pdata->groups[group].pins[0]; + *npins = pdata->groups[group].npins; + + return 0; +} + +void aspeed_pinctrl_pin_dbg_show(struct pinctrl_dev *pctldev, + struct seq_file *s, unsigned int offset) +{ + seq_printf(s, " %s", dev_name(pctldev->dev)); +} + +int aspeed_pinmux_get_fn_count(struct pinctrl_dev *pctldev) +{ + struct aspeed_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev); + + return pdata->nfunctions; +} + +const char *aspeed_pinmux_get_fn_name(struct pinctrl_dev *pctldev, + unsigned int function) +{ + struct aspeed_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev); + + return pdata->functions[function].name; +} + +int aspeed_pinmux_get_fn_groups(struct pinctrl_dev *pctldev, + unsigned int function, + const char * const **groups, + unsigned int * const num_groups) +{ + struct aspeed_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev); + + *groups = pdata->functions[function].groups; + *num_groups = pdata->functions[function].ngroups; + + return 0; +} + +static inline void aspeed_sig_desc_print_val( + const struct aspeed_sig_desc *desc, bool enable, u32 rv) +{ + pr_debug("SCU%x[0x%08x]=0x%x, got 0x%x from 0x%08x\n", desc->reg, + desc->mask, enable ? desc->enable : desc->disable, + (rv & desc->mask) >> __ffs(desc->mask), rv); +} + +/** + * Query the enabled or disabled state of a signal descriptor + * + * @desc: The signal descriptor of interest + * @enabled: True to query the enabled state, false to query disabled state + * @regmap: The SCU regmap instance + * + * @return True if the descriptor's bitfield is configured to the state + * selected by @enabled, false otherwise + * + * Evaluation of descriptor state is non-trivial in that it is not a binary + * outcome: The bitfields can be greater than one bit in size and thus can take + * a value that is neither the enabled nor disabled state recorded in the + * descriptor (typically this means a different function to the one of interest + * is enabled). Thus we must explicitly test for either condition as required. + */ +static bool aspeed_sig_desc_eval(const struct aspeed_sig_desc *desc, + bool enabled, struct regmap *map) +{ + unsigned int raw; + u32 want; + + if (regmap_read(map, desc->reg, &raw) < 0) + return false; + + aspeed_sig_desc_print_val(desc, enabled, raw); + want = enabled ? desc->enable : desc->disable; + + return ((raw & desc->mask) >> __ffs(desc->mask)) == want; +} + +/** + * Query the enabled or disabled state for a mux function's signal on a pin + * + * @expr: An expression controlling the signal for a mux function on a pin + * @enabled: True to query the enabled state, false to query disabled state + * @regmap: The SCU regmap instance + * + * @return True if the expression composed by @enabled evaluates true, false + * otherwise + * + * A mux function is enabled or disabled if the function's signal expression + * for each pin in the function's pin group evaluates true for the desired + * state. An signal expression evaluates true if all of its associated signal + * descriptors evaluate true for the desired state. + * + * If an expression's state is described by more than one bit, either through + * multi-bit bitfields in a single signal descriptor or through multiple signal + * descriptors of a single bit then it is possible for the expression to be in + * neither the enabled nor disabled state. Thus we must explicitly test for + * either condition as required. + */ +static bool aspeed_sig_expr_eval(const struct aspeed_sig_expr *expr, + bool enabled, struct regmap *map) +{ + int i; + + for (i = 0; i < expr->ndescs; i++) { + const struct aspeed_sig_desc *desc = &expr->descs[i]; + + if (!aspeed_sig_desc_eval(desc, enabled, map)) + return false; + } + + return true; +} + +/** + * Configure a pin's signal by applying an expression's descriptor state for + * all descriptors in the expression. + * + * @expr: The expression associated with the function whose signal is to be + * configured + * @enable: true to enable an function's signal through a pin's signal + * expression, false to disable the function's signal + * @map: The SCU's regmap instance for pinmux register access. + * + * @return true if the expression is configured as requested, false otherwise + */ +static bool aspeed_sig_expr_set(const struct aspeed_sig_expr *expr, + bool enable, struct regmap *map) +{ + int i; + bool ret; + + ret = aspeed_sig_expr_eval(expr, enable, map); + if (ret) + return ret; + + for (i = 0; i < expr->ndescs; i++) { + const struct aspeed_sig_desc *desc = &expr->descs[i]; + u32 pattern = enable ? desc->enable : desc->disable; + + /* + * Strap registers are configured in hardware or by early-boot + * firmware. Treat them as read-only despite that we can write + * them. This may mean that certain functions cannot be + * deconfigured and is the reason we re-evaluate after writing + * all descriptor bits. + */ + if (desc->reg == HW_STRAP1 || desc->reg == HW_STRAP2) + continue; + + ret = regmap_update_bits(map, desc->reg, desc->mask, + pattern << __ffs(desc->mask)); + + if (ret < 0) + return false; + } + + return aspeed_sig_expr_eval(expr, enable, map); +} + +static bool aspeed_sig_expr_enable(const struct aspeed_sig_expr *expr, + struct regmap *map) +{ + return aspeed_sig_expr_set(expr, true, map); +} + +static bool aspeed_sig_expr_disable(const struct aspeed_sig_expr *expr, + struct regmap *map) +{ + return aspeed_sig_expr_set(expr, false, map); +} + +/** + * Disable a signal on a pin by disabling all provided signal expressions. + * + * @exprs: The list of signal expressions (from a priority level on a pin) + * @map: The SCU's regmap instance for pinmux register access. + * + * @return true if all expressions in the list are successfully disabled, false + * otherwise + */ +static bool aspeed_disable_sig(const struct aspeed_sig_expr **exprs, + struct regmap *map) +{ + bool disabled = true; + + if (!exprs) + return true; + + while (*exprs) { + bool ret; + + ret = aspeed_sig_expr_disable(*exprs, map); + disabled = disabled && ret; + + exprs++; + } + + return disabled; +} + +/** + * Search for the signal expression needed to enable the pin's signal for the + * requested function. + * + * @exprs: List of signal expressions (haystack) + * @name: The name of the requested function (needle) + * + * @return A pointer to the signal expression whose function tag matches the + * provided name, otherwise NULL. + * + */ +static const struct aspeed_sig_expr *aspeed_find_expr_by_name( + const struct aspeed_sig_expr **exprs, const char *name) +{ + while (*exprs) { + if (strcmp((*exprs)->function, name) == 0) + return *exprs; + exprs++; + } + + return NULL; +} + +static char *get_defined_attribute(const struct aspeed_pin_desc *pdesc, + const char *(*get)( + const struct aspeed_sig_expr *)) +{ + char *found = NULL; + size_t len = 0; + const struct aspeed_sig_expr ***prios, **funcs, *expr; + + prios = pdesc->prios; + + while ((funcs = *prios)) { + while ((expr = *funcs)) { + const char *str = get(expr); + size_t delta = strlen(str) + 2; + char *expanded; + + expanded = krealloc(found, len + delta + 1, GFP_KERNEL); + if (!expanded) { + kfree(found); + return expanded; + } + + found = expanded; + found[len] = '\0'; + len += delta; + + strcat(found, str); + strcat(found, ", "); + + funcs++; + } + prios++; + } + + if (len < 2) { + kfree(found); + return NULL; + } + + found[len - 2] = '\0'; + + return found; +} + +static const char *aspeed_sig_expr_function(const struct aspeed_sig_expr *expr) +{ + return expr->function; +} + +static char *get_defined_functions(const struct aspeed_pin_desc *pdesc) +{ + return get_defined_attribute(pdesc, aspeed_sig_expr_function); +} + +static const char *aspeed_sig_expr_signal(const struct aspeed_sig_expr *expr) +{ + return expr->signal; +} + +static char *get_defined_signals(const struct aspeed_pin_desc *pdesc) +{ + return get_defined_attribute(pdesc, aspeed_sig_expr_signal); +} + +int aspeed_pinmux_set_mux(struct pinctrl_dev *pctldev, unsigned int function, + unsigned int group) +{ + int i; + const struct aspeed_pinctrl_data *pdata = + pinctrl_dev_get_drvdata(pctldev); + const struct aspeed_pin_group *pgroup = &pdata->groups[group]; + const struct aspeed_pin_function *pfunc = + &pdata->functions[function]; + + for (i = 0; i < pgroup->npins; i++) { + int pin = pgroup->pins[i]; + const struct aspeed_pin_desc *pdesc = pdata->pins[pin].drv_data; + const struct aspeed_sig_expr *expr = NULL; + const struct aspeed_sig_expr **funcs; + const struct aspeed_sig_expr ***prios; + + if (!pdesc) + return -EINVAL; + + prios = pdesc->prios; + + if (!prios) + continue; + + /* Disable functions at a higher priority than that requested */ + while ((funcs = *prios)) { + expr = aspeed_find_expr_by_name(funcs, pfunc->name); + + if (expr) + break; + + if (!aspeed_disable_sig(funcs, pdata->map)) + return -EPERM; + + prios++; + } + + if (!expr) { + char *functions = get_defined_functions(pdesc); + char *signals = get_defined_signals(pdesc); + + pr_warn("No function %s found on pin %s (%d). Found signal(s) %s for function(s) %s\n", + pfunc->name, pdesc->name, pin, signals, + functions); + kfree(signals); + kfree(functions); + + return -ENXIO; + } + + if (!aspeed_sig_expr_enable(expr, pdata->map)) + return -EPERM; + } + + return 0; +} + +static bool aspeed_expr_is_gpio(const struct aspeed_sig_expr *expr) +{ + /* + * The signal type is GPIO if the signal name has "GPIO" as a prefix. + * strncmp (rather than strcmp) is used to implement the prefix + * requirement. + * + * expr->signal might look like "GPIOT3" in the GPIO case. + */ + return strncmp(expr->signal, "GPIO", 4) == 0; +} + +static bool aspeed_gpio_in_exprs(const struct aspeed_sig_expr **exprs) +{ + if (!exprs) + return false; + + while (*exprs) { + if (aspeed_expr_is_gpio(*exprs)) + return true; + exprs++; + } + + return false; +} + +int aspeed_gpio_request_enable(struct pinctrl_dev *pctldev, + struct pinctrl_gpio_range *range, + unsigned int offset) +{ + const struct aspeed_pinctrl_data *pdata = + pinctrl_dev_get_drvdata(pctldev); + const struct aspeed_pin_desc *pdesc = pdata->pins[offset].drv_data; + const struct aspeed_sig_expr ***prios, **funcs, *expr; + + if (!pdesc) + return -EINVAL; + + prios = pdesc->prios; + + if (!prios) + return -ENXIO; + + /* Disable any functions of higher priority than GPIO */ + while ((funcs = *prios)) { + if (aspeed_gpio_in_exprs(funcs)) + break; + + if (!aspeed_disable_sig(funcs, pdata->map)) + return -EPERM; + + prios++; + } + + if (!funcs) { + char *signals = get_defined_signals(pdesc); + + pr_warn("No GPIO signal type found on pin %s (%d). Found: %s\n", + pdesc->name, offset, signals); + kfree(signals); + + return -ENXIO; + } + + expr = *funcs; + + /* + * Disabling all higher-priority expressions is enough to enable the + * lowest-priority signal type. As such it has no associated + * expression. + */ + if (!expr) + return 0; + + /* + * If GPIO is not the lowest priority signal type, assume there is only + * one expression defined to enable the GPIO function + */ + if (!aspeed_sig_expr_enable(expr, pdata->map)) + return -EPERM; + + return 0; +} + +int aspeed_pinctrl_probe(struct platform_device *pdev, + struct pinctrl_desc *pdesc, + struct aspeed_pinctrl_data *pdata) +{ + struct device *parent; + struct pinctrl_dev *pctl; + + parent = pdev->dev.parent; + if (!parent) { + dev_err(&pdev->dev, "No parent for syscon pincontroller\n"); + return -ENODEV; + } + + pdata->map = syscon_node_to_regmap(parent->of_node); + if (IS_ERR(pdata->map)) { + dev_err(&pdev->dev, "No regmap for syscon pincontroller parent\n"); + return PTR_ERR(pdata->map); + } + + pctl = pinctrl_register(pdesc, &pdev->dev, pdata); + + if (IS_ERR(pctl)) { + dev_err(&pdev->dev, "Failed to register pinctrl\n"); + return PTR_ERR(pctl); + } + + platform_set_drvdata(pdev, pdata); + + return 0; +} diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed.h b/drivers/pinctrl/aspeed/pinctrl-aspeed.h new file mode 100644 index 000000000000..3e72ef8c54bf --- /dev/null +++ b/drivers/pinctrl/aspeed/pinctrl-aspeed.h @@ -0,0 +1,569 @@ +/* + * Copyright (C) 2016 IBM Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef PINCTRL_ASPEED +#define PINCTRL_ASPEED + +#include +#include +#include +#include +#include + +/* + * The ASPEED SoCs provide typically more than 200 pins for GPIO and other + * functions. The SoC function enabled on a pin is determined on a priority + * basis where a given pin can provide a number of different signal types. + * + * The signal active on a pin is described by both a priority level and + * compound logical expressions involving multiple operators, registers and + * bits. Some difficulty arises as the pin's function bit masks for each + * priority level are frequently not the same (i.e. cannot just flip a bit to + * change from a high to low priority signal), or even in the same register. + * Further, not all signals can be unmuxed, as some expressions depend on + * values in the hardware strapping register (which is treated as read-only). + * + * SoC Multi-function Pin Expression Examples + * ------------------------------------------ + * + * Here are some sample mux configurations from the AST2400 and AST2500 + * datasheets to illustrate the corner cases, roughly in order of least to most + * corner. The signal priorities are in decending order from P0 (highest). + * + * D6 is a pin with a single function (beside GPIO); a high priority signal + * that participates in one function: + * + * Ball | Default | P0 Signal | P0 Expression | P1 Signal | P1 Expression | Other + * -----+---------+-----------+-----------------------------+-----------+---------------+---------- + * D6 GPIOA0 MAC1LINK SCU80[0]=1 GPIOA0 + * -----+---------+-----------+-----------------------------+-----------+---------------+---------- + * + * C5 is a multi-signal pin (high and low priority signals). Here we touch + * different registers for the different functions that enable each signal: + * + * -----+---------+-----------+-----------------------------+-----------+---------------+---------- + * C5 GPIOA4 SCL9 SCU90[22]=1 TIMER5 SCU80[4]=1 GPIOA4 + * -----+---------+-----------+-----------------------------+-----------+---------------+---------- + * + * E19 is a single-signal pin with two functions that influence the active + * signal. In this case both bits have the same meaning - enable a dedicated + * LPC reset pin. However it's not always the case that the bits in the + * OR-relationship have the same meaning. + * + * -----+---------+-----------+-----------------------------+-----------+---------------+---------- + * E19 GPIOB4 LPCRST# SCU80[12]=1 | Strap[14]=1 GPIOB4 + * -----+---------+-----------+-----------------------------+-----------+---------------+---------- + * + * For example, pin B19 has a low-priority signal that's enabled by two + * distinct SoC functions: A specific SIOPBI bit in register SCUA4, and an ACPI + * bit in the STRAP register. The ACPI bit configures signals on pins in + * addition to B19. Both of the low priority functions as well as the high + * priority function must be disabled for GPIOF1 to be used. + * + * Ball | Default | P0 Signal | P0 Expression | P1 Signal | P1 Expression | Other + * -----+---------+-----------+-----------------------------------------+-----------+----------------------------------------+---------- + * B19 GPIOF1 NDCD4 SCU80[25]=1 SIOPBI# SCUA4[12]=1 | Strap[19]=0 GPIOF1 + * -----+---------+-----------+-----------------------------------------+-----------+----------------------------------------+---------- + * + * For pin E18, the SoC ANDs the expected state of three bits to determine the + * pin's active signal: + * + * * SCU3C[3]: Enable external SOC reset function + * * SCU80[15]: Enable SPICS1# or EXTRST# function pin + * * SCU90[31]: Select SPI interface CS# output + * + * -----+---------+-----------+-----------------------------------------+-----------+----------------------------------------+---------- + * E18 GPIOB7 EXTRST# SCU3C[3]=1 & SCU80[15]=1 & SCU90[31]=0 SPICS1# SCU3C[3]=1 & SCU80[15]=1 & SCU90[31]=1 GPIOB7 + * -----+---------+-----------+-----------------------------------------+-----------+----------------------------------------+---------- + * + * (Bits SCU3C[3] and SCU80[15] appear to only be used in the expressions for + * selecting the signals on pin E18) + * + * Pin T5 is a multi-signal pin with a more complex configuration: + * + * Ball | Default | P0 Signal | P0 Expression | P1 Signal | P1 Expression | Other + * -----+---------+-----------+------------------------------+-----------+---------------+---------- + * T5 GPIOL1 VPIDE SCU90[5:4]!=0 & SCU84[17]=1 NDCD1 SCU84[17]=1 GPIOL1 + * -----+---------+-----------+------------------------------+-----------+---------------+---------- + * + * The high priority signal configuration is best thought of in terms of its + * exploded form, with reference to the SCU90[5:4] bits: + * + * * SCU90[5:4]=00: disable + * * SCU90[5:4]=01: 18 bits (R6/G6/B6) video mode. + * * SCU90[5:4]=10: 24 bits (R8/G8/B8) video mode. + * * SCU90[5:4]=11: 30 bits (R10/G10/B10) video mode. + * + * Re-writing: + * + * -----+---------+-----------+------------------------------+-----------+---------------+---------- + * T5 GPIOL1 VPIDE (SCU90[5:4]=1 & SCU84[17]=1) NDCD1 SCU84[17]=1 GPIOL1 + * | (SCU90[5:4]=2 & SCU84[17]=1) + * | (SCU90[5:4]=3 & SCU84[17]=1) + * -----+---------+-----------+------------------------------+-----------+---------------+---------- + * + * For reference the SCU84[17] bit configure the "UART1 NDCD1 or Video VPIDE + * function pin", where the signal itself is determined by whether SCU94[5:4] + * is disabled or in one of the 18, 24 or 30bit video modes. + * + * Other video-input-related pins require an explicit state in SCU90[5:4], e.g. + * W1 and U5: + * + * -----+---------+-----------+------------------------------+-----------+---------------+---------- + * W1 GPIOL6 VPIB0 SCU90[5:4]=3 & SCU84[22]=1 TXD1 SCU84[22]=1 GPIOL6 + * U5 GPIOL7 VPIB1 SCU90[5:4]=3 & SCU84[23]=1 RXD1 SCU84[23]=1 GPIOL7 + * -----+---------+-----------+------------------------------+-----------+---------------+---------- + * + * The examples of T5 and W1 are particularly fertile, as they also demonstrate + * that despite operating as part of the video input bus each signal needs to + * be enabled individually via it's own SCU84 (in the cases of T5 and W1) + * register bit. This is a little crazy if the bus doesn't have optional + * signals, but is used to decent effect with some of the UARTs where not all + * signals are required. However, this isn't done consistently - UART1 is + * enabled on a per-pin basis, and by contrast, all signals for UART6 are + * enabled by a single bit. + * + * Further, the high and low priority signals listed in the table above share + * a configuration bit. The VPI signals should operate in concert in a single + * function, but the UART signals should retain the ability to be configured + * independently. This pushes the implementation down the path of tagging a + * signal's expressions with the function they participate in, rather than + * defining masks affecting multiple signals per function. The latter approach + * fails in this instance where applying the configuration for the UART pin of + * interest will stomp on the state of other UART signals when disabling the + * VPI functions on the current pin. + * + * Ball | Default | P0 Signal | P0 Expression | P1 Signal | P1 Expression | Other + * -----+------------+-----------+---------------------------+-----------+---------------+------------ + * A12 RGMII1TXCK GPIOT0 SCUA0[0]=1 RMII1TXEN Strap[6]=0 RGMII1TXCK + * B12 RGMII1TXCTL GPIOT1 SCUA0[1]=1 – Strap[6]=0 RGMII1TXCTL + * -----+------------+-----------+---------------------------+-----------+---------------+------------ + * + * A12 demonstrates that the "Other" signal isn't always GPIO - in this case + * GPIOT0 is a high-priority signal and RGMII1TXCK is Other. Thus, GPIO + * should be treated like any other signal type with full function expression + * requirements, and not assumed to be the default case. Separately, GPIOT0 and + * GPIOT1's signal descriptor bits are distinct, therefore we must iterate all + * pins in the function's group to disable the higher-priority signals such + * that the signal for the function of interest is correctly enabled. + * + * Finally, three priority levels aren't always enough; the AST2500 brings with + * it 18 pins of five priority levels, however the 18 pins only use three of + * the five priority levels. + * + * Ultimately the requirement to control pins in the examples above drive the + * design: + * + * * Pins provide signals according to functions activated in the mux + * configuration + * + * * Pins provide up to five signal types in a priority order + * + * * For priorities levels defined on a pin, each priority provides one signal + * + * * Enabling lower priority signals requires higher priority signals be + * disabled + * + * * A function represents a set of signals; functions are distinct if their + * sets of signals are not equal + * + * * Signals participate in one or more functions + * + * * A function is described by an expression of one or more signal + * descriptors, which compare bit values in a register + * + * * A signal expression is the smallest set of signal descriptors whose + * comparisons must evaluate 'true' for a signal to be enabled on a pin. + * + * * A function's signal is active on a pin if evaluating all signal + * descriptors in the pin's signal expression for the function yields a 'true' + * result + * + * * A signal at a given priority on a given pin is active if any of the + * functions in which the signal participates are active, and no higher + * priority signal on the pin is active + * + * * GPIO is configured per-pin + * + * And so: + * + * * To disable a signal, any function(s) activating the signal must be + * disabled + * + * * Each pin must know the signal expressions of functions in which it + * participates, for the purpose of enabling the Other function. This is done + * by deactivating all functions that activate higher priority signals on the + * pin. + * + * As a concrete example: + * + * * T5 provides three signals types: VPIDE, NDCD1 and GPIO + * + * * The VPIDE signal participates in 3 functions: VPI18, VPI24 and VPI30 + * + * * The NDCD1 signal participates in just its own NDCD1 function + * + * * VPIDE is high priority, NDCD1 is low priority, and GPIOL1 is the least + * prioritised + * + * * The prerequisit for activating the NDCD1 signal is that the VPI18, VPI24 + * and VPI30 functions all be disabled + * + * * Similarly, all of VPI18, VPI24, VPI30 and NDCD1 functions must be disabled + * to provide GPIOL6 + * + * Considerations + * -------------- + * + * If pinctrl allows us to allocate a pin we can configure a function without + * concern for the function of already allocated pins, if pin groups are + * created with respect to the SoC functions in which they participate. This is + * intuitive, but it did not feel obvious from the bit/pin relationships. + * + * Conversely, failing to allocate all pins in a group indicates some bits (as + * well as pins) required for the group's configuration will already be in use, + * likely in a way that's inconsistent with the requirements of the failed + * group. + */ + +/* + * The "Multi-function Pins Mapping and Control" table in the SoC datasheet + * references registers by the device/offset mnemonic. The register macros + * below are named the same way to ease transcription and verification (as + * opposed to naming them e.g. PINMUX_CTRL_[0-9]). Further, signal expressions + * reference registers beyond those dedicated to pinmux, such as the system + * reset control and MAC clock configuration registers. The AST2500 goes a step + * further and references registers in the graphics IP block, but that isn't + * handled yet. + */ +#define SCU2C 0x2C /* Misc. Control Register */ +#define SCU3C 0x3C /* System Reset Control/Status Register */ +#define SCU48 0x48 /* MAC Interface Clock Delay Setting */ +#define HW_STRAP1 0x70 /* AST2400 strapping is 33 bits, is split */ +#define SCU80 0x80 /* Multi-function Pin Control #1 */ +#define SCU84 0x84 /* Multi-function Pin Control #2 */ +#define SCU88 0x88 /* Multi-function Pin Control #3 */ +#define SCU8C 0x8C /* Multi-function Pin Control #4 */ +#define SCU90 0x90 /* Multi-function Pin Control #5 */ +#define SCU94 0x94 /* Multi-function Pin Control #6 */ +#define SCUA0 0xA0 /* Multi-function Pin Control #7 */ +#define SCUA4 0xA4 /* Multi-function Pin Control #8 */ +#define SCUA8 0xA8 /* Multi-function Pin Control #9 */ +#define HW_STRAP2 0xD0 /* Strapping */ + + /** + * A signal descriptor, which describes the register, bits and the + * enable/disable values that should be compared or written. + * + * @reg: The register offset from base in bytes + * @mask: The mask to apply to the register. The lowest set bit of the mask is + * used to derive the shift value. + * @enable: The value that enables the function. Value should be in the LSBs, + * not at the position of the mask. + * @disable: The value that disables the function. Value should be in the + * LSBs, not at the position of the mask. + */ +struct aspeed_sig_desc { + unsigned int reg; + u32 mask; + u32 enable; + u32 disable; +}; + +/** + * Describes a signal expression. The expression is evaluated by ANDing the + * evaluation of the descriptors. + * + * @signal: The signal name for the priority level on the pin. If the signal + * type is GPIO, then the signal name must begin with the string + * "GPIO", e.g. GPIOA0, GPIOT4 etc. + * @function: The name of the function the signal participates in for the + * associated expression + * @ndescs: The number of signal descriptors in the expression + * @descs: Pointer to an array of signal descriptors that comprise the + * function expression + */ +struct aspeed_sig_expr { + const char *signal; + const char *function; + int ndescs; + const struct aspeed_sig_desc *descs; +}; + +/** + * A struct capturing the list of expressions enabling signals at each priority + * for a given pin. The signal configuration for a priority level is evaluated + * by ORing the evaluation of the signal expressions in the respective + * priority's list. + * + * @name: A name for the pin + * @prios: A pointer to an array of expression list pointers + * + */ +struct aspeed_pin_desc { + const char *name; + const struct aspeed_sig_expr ***prios; +}; + +/* Macro hell */ + +/** + * Short-hand macro for describing a configuration enabled by the state of one + * bit. The disable value is derived. + * + * @reg: The signal's associated register, offset from base + * @idx: The signal's bit index in the register + * @val: The value (0 or 1) that enables the function + */ +#define SIG_DESC_BIT(reg, idx, val) \ + { reg, BIT_MASK(idx), val, (((val) + 1) & 1) } + +/** + * A further short-hand macro describing a configuration enabled with a set bit. + * + * @reg: The configuration's associated register, offset from base + * @idx: The configuration's bit index in the register + */ +#define SIG_DESC_SET(reg, idx) SIG_DESC_BIT(reg, idx, 1) + +#define SIG_DESC_LIST_SYM(sig, func) sig_descs_ ## sig ## _ ## func +#define SIG_DESC_LIST_DECL(sig, func, ...) \ + static const struct aspeed_sig_desc SIG_DESC_LIST_SYM(sig, func)[] = \ + { __VA_ARGS__ } + +#define SIG_EXPR_SYM(sig, func) sig_expr_ ## sig ## _ ## func +#define SIG_EXPR_DECL_(sig, func) \ + static const struct aspeed_sig_expr SIG_EXPR_SYM(sig, func) = \ + { \ + .signal = #sig, \ + .function = #func, \ + .ndescs = ARRAY_SIZE(SIG_DESC_LIST_SYM(sig, func)), \ + .descs = &(SIG_DESC_LIST_SYM(sig, func))[0], \ + } + +/** + * Declare a signal expression. + * + * @sig: A macro symbol name for the signal (is subjected to stringification + * and token pasting) + * @func: The function in which the signal is participating + * @...: Signal descriptors that define the signal expression + * + * For example, the following declares the ROMD8 signal for the ROM16 function: + * + * SIG_EXPR_DECL(ROMD8, ROM16, SIG_DESC_SET(SCU90, 6)); + * + * And with multiple signal descriptors: + * + * SIG_EXPR_DECL(ROMD8, ROM16S, SIG_DESC_SET(HW_STRAP1, 4), + * { HW_STRAP1, GENMASK(1, 0), 0, 0 }); + */ +#define SIG_EXPR_DECL(sig, func, ...) \ + SIG_DESC_LIST_DECL(sig, func, __VA_ARGS__); \ + SIG_EXPR_DECL_(sig, func) + +/** + * Declare a pointer to a signal expression + * + * @sig: The macro symbol name for the signal (subjected to token pasting) + * @func: The macro symbol name for the function (subjected to token pasting) + */ +#define SIG_EXPR_PTR(sig, func) (&SIG_EXPR_SYM(sig, func)) + +#define SIG_EXPR_LIST_SYM(sig) sig_exprs_ ## sig + +/** + * Declare a signal expression list for reference in a struct aspeed_pin_prio. + * + * @sig: A macro symbol name for the signal (is subjected to token pasting) + * @...: Signal expression structure pointers (use SIG_EXPR_PTR()) + * + * For example, the 16-bit ROM bus can be enabled by one of two possible signal + * expressions: + * + * SIG_EXPR_DECL(ROMD8, ROM16, SIG_DESC_SET(SCU90, 6)); + * SIG_EXPR_DECL(ROMD8, ROM16S, SIG_DESC_SET(HW_STRAP1, 4), + * { HW_STRAP1, GENMASK(1, 0), 0, 0 }); + * SIG_EXPR_LIST_DECL(ROMD8, SIG_EXPR_PTR(ROMD8, ROM16), + * SIG_EXPR_PTR(ROMD8, ROM16S)); + */ +#define SIG_EXPR_LIST_DECL(sig, ...) \ + static const struct aspeed_sig_expr *SIG_EXPR_LIST_SYM(sig)[] = \ + { __VA_ARGS__, NULL } + +/** + * A short-hand macro for declaring a function expression and an expression + * list with a single function. + * + * @func: A macro symbol name for the function (is subjected to token pasting) + * @...: Function descriptors that define the function expression + * + * For example, signal NCTS6 participates in its own function with one group: + * + * SIG_EXPR_LIST_DECL_SINGLE(NCTS6, NCTS6, SIG_DESC_SET(SCU90, 7)); + */ +#define SIG_EXPR_LIST_DECL_SINGLE(sig, func, ...) \ + SIG_DESC_LIST_DECL(sig, func, __VA_ARGS__); \ + SIG_EXPR_DECL_(sig, func); \ + SIG_EXPR_LIST_DECL(sig, SIG_EXPR_PTR(sig, func)) + +#define SIG_EXPR_LIST_DECL_DUAL(sig, f0, f1) \ + SIG_EXPR_LIST_DECL(sig, SIG_EXPR_PTR(sig, f0), SIG_EXPR_PTR(sig, f1)) + +#define SIG_EXPR_LIST_PTR(sig) (&SIG_EXPR_LIST_SYM(sig)[0]) + +#define PIN_EXPRS_SYM(pin) pin_exprs_ ## pin +#define PIN_EXPRS_PTR(pin) (&PIN_EXPRS_SYM(pin)[0]) +#define PIN_SYM(pin) pin_ ## pin + +#define MS_PIN_DECL_(pin, ...) \ + static const struct aspeed_sig_expr **PIN_EXPRS_SYM(pin)[] = \ + { __VA_ARGS__, NULL }; \ + static const struct aspeed_pin_desc PIN_SYM(pin) = \ + { #pin, PIN_EXPRS_PTR(pin) } + +/** + * Declare a multi-signal pin + * + * @pin: The pin number + * @other: Macro name for "other" functionality (subjected to stringification) + * @high: Macro name for the highest priority signal functions + * @low: Macro name for the low signal functions + * + * For example: + * + * #define A8 56 + * SIG_EXPR_DECL(ROMD8, ROM16, SIG_DESC_SET(SCU90, 6)); + * SIG_EXPR_DECL(ROMD8, ROM16S, SIG_DESC_SET(HW_STRAP1, 4), + * { HW_STRAP1, GENMASK(1, 0), 0, 0 }); + * SIG_EXPR_LIST_DECL(ROMD8, SIG_EXPR_PTR(ROMD8, ROM16), + * SIG_EXPR_PTR(ROMD8, ROM16S)); + * SIG_EXPR_LIST_DECL_SINGLE(NCTS6, NCTS6, SIG_DESC_SET(SCU90, 7)); + * MS_PIN_DECL(A8, GPIOH0, ROMD8, NCTS6); + */ +#define MS_PIN_DECL(pin, other, high, low) \ + SIG_EXPR_LIST_DECL_SINGLE(other, other); \ + MS_PIN_DECL_(pin, \ + SIG_EXPR_LIST_PTR(high), \ + SIG_EXPR_LIST_PTR(low), \ + SIG_EXPR_LIST_PTR(other)) + +#define PIN_GROUP_SYM(func) pins_ ## func +#define FUNC_GROUP_SYM(func) groups_ ## func +#define FUNC_GROUP_DECL(func, ...) \ + static const int PIN_GROUP_SYM(func)[] = { __VA_ARGS__ }; \ + static const char *FUNC_GROUP_SYM(func)[] = { #func } + +/** + * Declare a single signal pin + * + * @pin: The pin number + * @other: Macro name for "other" functionality (subjected to stringification) + * @sig: Macro name for the signal (subjected to stringification) + * + * For example: + * + * #define E3 80 + * SIG_EXPR_LIST_DECL_SINGLE(SCL5, I2C5, I2C5_DESC); + * SS_PIN_DECL(E3, GPIOK0, SCL5); + */ +#define SS_PIN_DECL(pin, other, sig) \ + SIG_EXPR_LIST_DECL_SINGLE(other, other); \ + MS_PIN_DECL_(pin, SIG_EXPR_LIST_PTR(sig), SIG_EXPR_LIST_PTR(other)) + +/** + * Single signal, single function pin declaration + * + * @pin: The pin number + * @other: Macro name for "other" functionality (subjected to stringification) + * @sig: Macro name for the signal (subjected to stringification) + * @...: Signal descriptors that define the function expression + * + * For example: + * + * SSSF_PIN_DECL(A4, GPIOA2, TIMER3, SIG_DESC_SET(SCU80, 2)); + */ +#define SSSF_PIN_DECL(pin, other, sig, ...) \ + SIG_EXPR_LIST_DECL_SINGLE(sig, sig, __VA_ARGS__); \ + SIG_EXPR_LIST_DECL_SINGLE(other, other); \ + MS_PIN_DECL_(pin, SIG_EXPR_LIST_PTR(sig), SIG_EXPR_LIST_PTR(other)); \ + FUNC_GROUP_DECL(sig, pin) + +#define GPIO_PIN_DECL(pin, gpio) \ + SIG_EXPR_LIST_DECL_SINGLE(gpio, gpio); \ + MS_PIN_DECL_(pin, SIG_EXPR_LIST_PTR(gpio)) + +struct aspeed_pinctrl_data { + struct regmap *map; + + const struct pinctrl_pin_desc *pins; + const unsigned int npins; + + const struct aspeed_pin_group *groups; + const unsigned int ngroups; + + const struct aspeed_pin_function *functions; + const unsigned int nfunctions; +}; + +#define ASPEED_PINCTRL_PIN(name_) \ + [name_] = { \ + .number = name_, \ + .name = #name_, \ + .drv_data = (void *) &(PIN_SYM(name_)) \ + } + +struct aspeed_pin_group { + const char *name; + const unsigned int *pins; + const unsigned int npins; +}; + +#define ASPEED_PINCTRL_GROUP(name_) { \ + .name = #name_, \ + .pins = &(PIN_GROUP_SYM(name_))[0], \ + .npins = ARRAY_SIZE(PIN_GROUP_SYM(name_)), \ +} + +struct aspeed_pin_function { + const char *name; + const char *const *groups; + unsigned int ngroups; +}; + +#define ASPEED_PINCTRL_FUNC(name_, ...) { \ + .name = #name_, \ + .groups = &FUNC_GROUP_SYM(name_)[0], \ + .ngroups = ARRAY_SIZE(FUNC_GROUP_SYM(name_)), \ +} + +int aspeed_pinctrl_get_groups_count(struct pinctrl_dev *pctldev); +const char *aspeed_pinctrl_get_group_name(struct pinctrl_dev *pctldev, + unsigned int group); +int aspeed_pinctrl_get_group_pins(struct pinctrl_dev *pctldev, + unsigned int group, const unsigned int **pins, + unsigned int *npins); +void aspeed_pinctrl_pin_dbg_show(struct pinctrl_dev *pctldev, + struct seq_file *s, unsigned int offset); +int aspeed_pinmux_get_fn_count(struct pinctrl_dev *pctldev); +const char *aspeed_pinmux_get_fn_name(struct pinctrl_dev *pctldev, + unsigned int function); +int aspeed_pinmux_get_fn_groups(struct pinctrl_dev *pctldev, + unsigned int function, const char * const **groups, + unsigned int * const num_groups); +int aspeed_pinmux_set_mux(struct pinctrl_dev *pctldev, unsigned int function, + unsigned int group); +int aspeed_gpio_request_enable(struct pinctrl_dev *pctldev, + struct pinctrl_gpio_range *range, + unsigned int offset); +int aspeed_pinctrl_probe(struct platform_device *pdev, + struct pinctrl_desc *pdesc, + struct aspeed_pinctrl_data *pdata); + +#endif /* PINCTRL_ASPEED */ -- cgit 1.4.1 From 524594d40153befc7b0c4600550a5eb312c6918c Mon Sep 17 00:00:00 2001 From: Andrew Jeffery Date: Tue, 30 Aug 2016 17:24:25 +0930 Subject: pinctrl: Add pinctrl-aspeed-g4 driver A subset of the pins and functions are exposed. The selection of functions and pins is driven by the development of OpenBMC[1] on the AST2400 SoC, particularly around booting the OpenPOWER Palmetto development machine. [1] https://github.com/openbmc/docs Signed-off-by: Andrew Jeffery Reviewed-by: Joel Stanley Signed-off-by: Linus Walleij --- drivers/pinctrl/aspeed/Kconfig | 8 + drivers/pinctrl/aspeed/Makefile | 1 + drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c | 1231 ++++++++++++++++++++++++++++ 3 files changed, 1240 insertions(+) create mode 100644 drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c diff --git a/drivers/pinctrl/aspeed/Kconfig b/drivers/pinctrl/aspeed/Kconfig index 757002f9be30..1f3d74549381 100644 --- a/drivers/pinctrl/aspeed/Kconfig +++ b/drivers/pinctrl/aspeed/Kconfig @@ -6,3 +6,11 @@ config PINCTRL_ASPEED select PINCONF select GENERIC_PINCONF select REGMAP_MMIO + +config PINCTRL_ASPEED_G4 + bool "Aspeed G4 SoC pin control" + depends on (MACH_ASPEED_G4 || COMPILE_TEST) && OF + select PINCTRL_ASPEED + help + Say Y here to enable pin controller support for Aspeed's 4th + generation SoCs. GPIO is provided by a separate GPIO driver. diff --git a/drivers/pinctrl/aspeed/Makefile b/drivers/pinctrl/aspeed/Makefile index a0fc61d31ccf..8675d6fd82df 100644 --- a/drivers/pinctrl/aspeed/Makefile +++ b/drivers/pinctrl/aspeed/Makefile @@ -2,3 +2,4 @@ ccflags-y += -Woverride-init obj-$(CONFIG_PINCTRL_ASPEED) += pinctrl-aspeed.o +obj-$(CONFIG_PINCTRL_ASPEED_G4) += pinctrl-aspeed-g4.o diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c b/drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c new file mode 100644 index 000000000000..a21b071ff290 --- /dev/null +++ b/drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c @@ -0,0 +1,1231 @@ +/* + * Copyright (C) 2016 IBM Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "../core.h" +#include "../pinctrl-utils.h" +#include "pinctrl-aspeed.h" + +/* + * Uses undefined macros for symbol naming and references, eg GPIOA0, MAC1LINK, + * TIMER3 etc. + * + * Pins are defined in GPIO bank order: + * + * GPIOA0: 0 + * ... + * GPIOA7: 7 + * GPIOB0: 8 + * ... + * GPIOZ7: 207 + * GPIOAA0: 208 + * ... + * GPIOAB3: 219 + * + * Not all pins have their signals defined (yet). + */ + +#define A4 2 +SSSF_PIN_DECL(A4, GPIOA2, TIMER3, SIG_DESC_SET(SCU80, 2)); + +#define I2C9_DESC SIG_DESC_SET(SCU90, 22) + +#define C5 4 +SIG_EXPR_LIST_DECL_SINGLE(SCL9, I2C9, I2C9_DESC); +SIG_EXPR_LIST_DECL_SINGLE(TIMER5, TIMER5, SIG_DESC_SET(SCU80, 4)); +MS_PIN_DECL(C5, GPIOA4, SCL9, TIMER5); + +FUNC_GROUP_DECL(TIMER5, C5); + +#define B4 5 +SIG_EXPR_LIST_DECL_SINGLE(SDA9, I2C9, I2C9_DESC); +SIG_EXPR_LIST_DECL_SINGLE(TIMER6, TIMER6, SIG_DESC_SET(SCU80, 5)); +MS_PIN_DECL(B4, GPIOA5, SDA9, TIMER6); + +FUNC_GROUP_DECL(TIMER6, B4); +FUNC_GROUP_DECL(I2C9, C5, B4); + +#define MDIO2_DESC SIG_DESC_SET(SCU90, 2) + +#define A3 6 +SIG_EXPR_LIST_DECL_SINGLE(MDC2, MDIO2, MDIO2_DESC); +SIG_EXPR_LIST_DECL_SINGLE(TIMER7, TIMER7, SIG_DESC_SET(SCU80, 6)); +MS_PIN_DECL(A3, GPIOA6, MDC2, TIMER7); + +FUNC_GROUP_DECL(TIMER7, A3); + +#define D5 7 +SIG_EXPR_LIST_DECL_SINGLE(MDIO2, MDIO2, MDIO2_DESC); +SIG_EXPR_LIST_DECL_SINGLE(TIMER8, TIMER8, SIG_DESC_SET(SCU80, 7)); +MS_PIN_DECL(D5, GPIOA7, MDIO2, TIMER8); + +FUNC_GROUP_DECL(TIMER8, D5); +FUNC_GROUP_DECL(MDIO2, A3, D5); + +#define H19 13 +#define H19_DESC SIG_DESC_SET(SCU80, 13) +SIG_EXPR_LIST_DECL_SINGLE(LPCPD, LPCPD, H19_DESC); +SIG_EXPR_LIST_DECL_SINGLE(LPCSMI, LPCSMI, H19_DESC); +MS_PIN_DECL(H19, GPIOB5, LPCPD, LPCSMI); + +FUNC_GROUP_DECL(LPCPD, H19); +FUNC_GROUP_DECL(LPCSMI, H19); + +#define H20 14 +SSSF_PIN_DECL(H20, GPIOB6, LPCPME, SIG_DESC_SET(SCU80, 14)); + +#define SD1_DESC SIG_DESC_SET(SCU90, 0) +#define I2C10_DESC SIG_DESC_SET(SCU90, 23) + +#define C4 16 +SIG_EXPR_LIST_DECL_SINGLE(SD1CLK, SD1, SD1_DESC); +SIG_EXPR_LIST_DECL_SINGLE(SCL10, I2C10, I2C10_DESC); +MS_PIN_DECL(C4, GPIOC0, SD1CLK, SCL10); + +#define B3 17 +SIG_EXPR_LIST_DECL_SINGLE(SD1CMD, SD1, SD1_DESC); +SIG_EXPR_LIST_DECL_SINGLE(SDA10, I2C10, I2C10_DESC); +MS_PIN_DECL(B3, GPIOC1, SD1CMD, SDA10); + +FUNC_GROUP_DECL(I2C10, C4, B3); + +#define I2C11_DESC SIG_DESC_SET(SCU90, 24) + +#define A2 18 +SIG_EXPR_LIST_DECL_SINGLE(SD1DAT0, SD1, SD1_DESC); +SIG_EXPR_LIST_DECL_SINGLE(SCL11, I2C11, I2C11_DESC); +MS_PIN_DECL(A2, GPIOC2, SD1DAT0, SCL11); + +#define E5 19 +SIG_EXPR_LIST_DECL_SINGLE(SD1DAT1, SD1, SD1_DESC); +SIG_EXPR_LIST_DECL_SINGLE(SDA11, I2C11, I2C11_DESC); +MS_PIN_DECL(E5, GPIOC3, SD1DAT1, SDA11); + +FUNC_GROUP_DECL(I2C11, A2, E5); + +#define I2C12_DESC SIG_DESC_SET(SCU90, 25) + +#define D4 20 +SIG_EXPR_LIST_DECL_SINGLE(SD1DAT2, SD1, SD1_DESC); +SIG_EXPR_LIST_DECL_SINGLE(SCL12, I2C12, I2C12_DESC); +MS_PIN_DECL(D4, GPIOC4, SD1DAT2, SCL12); + +#define C3 21 +SIG_EXPR_LIST_DECL_SINGLE(SD1DAT3, SD1, SD1_DESC); +SIG_EXPR_LIST_DECL_SINGLE(SDA12, I2C12, I2C12_DESC); +MS_PIN_DECL(C3, GPIOC5, SD1DAT3, SDA12); + +FUNC_GROUP_DECL(I2C12, D4, C3); + +#define I2C13_DESC SIG_DESC_SET(SCU90, 26) + +#define B2 22 +SIG_EXPR_LIST_DECL_SINGLE(SD1CD, SD1, SD1_DESC); +SIG_EXPR_LIST_DECL_SINGLE(SCL13, I2C13, I2C13_DESC); +MS_PIN_DECL(B2, GPIOC6, SD1CD, SCL13); + +#define A1 23 +SIG_EXPR_LIST_DECL_SINGLE(SD1WP, SD1, SD1_DESC); +SIG_EXPR_LIST_DECL_SINGLE(SDA13, I2C13, I2C13_DESC); +MS_PIN_DECL(A1, GPIOC7, SD1WP, SDA13); + +FUNC_GROUP_DECL(I2C13, B2, A1); +FUNC_GROUP_DECL(SD1, C4, B3, A2, E5, D4, C3, B2, A1); + +#define SD2_DESC SIG_DESC_SET(SCU90, 1) +#define GPID_DESC SIG_DESC_SET(HW_STRAP1, 21) +#define GPID0_DESC SIG_DESC_SET(SCU8C, 8) + +#define A18 24 +SIG_EXPR_LIST_DECL_SINGLE(SD2CLK, SD2, SD2_DESC); +SIG_EXPR_DECL(GPID0IN, GPID0, GPID0_DESC); +SIG_EXPR_DECL(GPID0IN, GPID, GPID_DESC); +SIG_EXPR_LIST_DECL_DUAL(GPID0IN, GPID0, GPID); +MS_PIN_DECL(A18, GPIOD0, SD2CLK, GPID0IN); + +#define D16 25 +SIG_EXPR_LIST_DECL_SINGLE(SD2CMD, SD2, SD2_DESC); +SIG_EXPR_DECL(GPID0OUT, GPID0, GPID0_DESC); +SIG_EXPR_DECL(GPID0OUT, GPID, GPID_DESC); +SIG_EXPR_LIST_DECL_DUAL(GPID0OUT, GPID0, GPID); +MS_PIN_DECL(D16, GPIOD1, SD2CMD, GPID0OUT); + +FUNC_GROUP_DECL(GPID0, A18, D16); + +#define GPIE_DESC SIG_DESC_SET(HW_STRAP1, 22) +#define GPIE0_DESC SIG_DESC_SET(SCU8C, 12) +#define GPIE2_DESC SIG_DESC_SET(SCU8C, 13) +#define GPIE4_DESC SIG_DESC_SET(SCU8C, 14) +#define GPIE6_DESC SIG_DESC_SET(SCU8C, 15) + +#define D15 32 +SIG_EXPR_LIST_DECL_SINGLE(NCTS3, NCTS3, SIG_DESC_SET(SCU80, 16)); +SIG_EXPR_DECL(GPIE0IN, GPIE0, GPIE0_DESC); +SIG_EXPR_DECL(GPIE0IN, GPIE, GPIE_DESC); +SIG_EXPR_LIST_DECL_DUAL(GPIE0IN, GPIE0, GPIE); +MS_PIN_DECL(D15, GPIOE0, NCTS3, GPIE0IN); + +FUNC_GROUP_DECL(NCTS3, D15); + +#define C15 33 +SIG_EXPR_LIST_DECL_SINGLE(NDCD3, NDCD3, SIG_DESC_SET(SCU80, 17)); +SIG_EXPR_DECL(GPIE0OUT, GPIE0, GPIE0_DESC); +SIG_EXPR_DECL(GPIE0OUT, GPIE, GPIE_DESC); +SIG_EXPR_LIST_DECL_DUAL(GPIE0OUT, GPIE0, GPIE); +MS_PIN_DECL(C15, GPIOE1, NDCD3, GPIE0OUT); + +FUNC_GROUP_DECL(NDCD3, C15); +FUNC_GROUP_DECL(GPIE0, D15, C15); + +#define B15 34 +SIG_EXPR_LIST_DECL_SINGLE(NDSR3, NDSR3, SIG_DESC_SET(SCU80, 18)); +SIG_EXPR_DECL(GPIE2IN, GPIE2, GPIE2_DESC); +SIG_EXPR_DECL(GPIE2IN, GPIE, GPIE_DESC); +SIG_EXPR_LIST_DECL_DUAL(GPIE2IN, GPIE2, GPIE); +MS_PIN_DECL(B15, GPIOE2, NDSR3, GPIE2IN); + +FUNC_GROUP_DECL(NDSR3, B15); + +#define A15 35 +SIG_EXPR_LIST_DECL_SINGLE(NRI3, NRI3, SIG_DESC_SET(SCU80, 19)); +SIG_EXPR_DECL(GPIE2OUT, GPIE2, GPIE2_DESC); +SIG_EXPR_DECL(GPIE2OUT, GPIE, GPIE_DESC); +SIG_EXPR_LIST_DECL_DUAL(GPIE2OUT, GPIE2, GPIE); +MS_PIN_DECL(A15, GPIOE3, NRI3, GPIE2OUT); + +FUNC_GROUP_DECL(NRI3, A15); +FUNC_GROUP_DECL(GPIE2, B15, A15); + +#define E14 36 +SIG_EXPR_LIST_DECL_SINGLE(NDTR3, NDTR3, SIG_DESC_SET(SCU80, 20)); +SIG_EXPR_DECL(GPIE4IN, GPIE4, GPIE4_DESC); +SIG_EXPR_DECL(GPIE4IN, GPIE, GPIE_DESC); +SIG_EXPR_LIST_DECL_DUAL(GPIE4IN, GPIE4, GPIE); +MS_PIN_DECL(E14, GPIOE4, NDTR3, GPIE4IN); + +FUNC_GROUP_DECL(NDTR3, E14); + +#define D14 37 +SIG_EXPR_LIST_DECL_SINGLE(NRTS3, NRTS3, SIG_DESC_SET(SCU80, 21)); +SIG_EXPR_DECL(GPIE4OUT, GPIE4, GPIE4_DESC); +SIG_EXPR_DECL(GPIE4OUT, GPIE, GPIE_DESC); +SIG_EXPR_LIST_DECL_DUAL(GPIE4OUT, GPIE4, GPIE); +MS_PIN_DECL(D14, GPIOE5, NRTS3, GPIE4OUT); + +FUNC_GROUP_DECL(NRTS3, D14); +FUNC_GROUP_DECL(GPIE4, E14, D14); + +#define C14 38 +SIG_EXPR_LIST_DECL_SINGLE(TXD3, TXD3, SIG_DESC_SET(SCU80, 22)); +SIG_EXPR_DECL(GPIE6IN, GPIE6, GPIE6_DESC); +SIG_EXPR_DECL(GPIE6IN, GPIE, GPIE_DESC); +SIG_EXPR_LIST_DECL_DUAL(GPIE6IN, GPIE6, GPIE); +MS_PIN_DECL(C14, GPIOE6, TXD3, GPIE6IN); + +FUNC_GROUP_DECL(TXD3, C14); + +#define B14 39 +SIG_EXPR_LIST_DECL_SINGLE(RXD3, RXD3, SIG_DESC_SET(SCU80, 23)); +SIG_EXPR_DECL(GPIE6OUT, GPIE6, GPIE6_DESC); +SIG_EXPR_DECL(GPIE6OUT, GPIE, GPIE_DESC); +SIG_EXPR_LIST_DECL_DUAL(GPIE6OUT, GPIE6, GPIE); +MS_PIN_DECL(B14, GPIOE7, RXD3, GPIE6OUT); + +FUNC_GROUP_DECL(RXD3, B14); +FUNC_GROUP_DECL(GPIE6, C14, B14); + +#define D18 40 +SSSF_PIN_DECL(D18, GPIOF0, NCTS4, SIG_DESC_SET(SCU80, 24)); + +#define ACPI_DESC SIG_DESC_BIT(HW_STRAP1, 19, 0) + +#define B19 41 +SIG_EXPR_LIST_DECL_SINGLE(NDCD4, NDCD4, SIG_DESC_SET(SCU80, 25)); +SIG_EXPR_DECL(SIOPBI, SIOPBI, SIG_DESC_SET(SCUA4, 12)); +SIG_EXPR_DECL(SIOPBI, ACPI, ACPI_DESC); +SIG_EXPR_LIST_DECL_DUAL(SIOPBI, SIOPBI, ACPI); +MS_PIN_DECL(B19, GPIOF1, NDCD4, SIOPBI); +FUNC_GROUP_DECL(NDCD4, B19); +FUNC_GROUP_DECL(SIOPBI, B19); + +#define D17 43 +SIG_EXPR_LIST_DECL_SINGLE(NRI4, NRI4, SIG_DESC_SET(SCU80, 27)); +SIG_EXPR_DECL(SIOPBO, SIOPBO, SIG_DESC_SET(SCUA4, 14)); +SIG_EXPR_DECL(SIOPBO, ACPI, ACPI_DESC); +SIG_EXPR_LIST_DECL_DUAL(SIOPBO, SIOPBO, ACPI); +MS_PIN_DECL(D17, GPIOF3, NRI4, SIOPBO); +FUNC_GROUP_DECL(NRI4, D17); +FUNC_GROUP_DECL(SIOPBO, D17); + +FUNC_GROUP_DECL(ACPI, B19, D17); + +#define E16 46 +SSSF_PIN_DECL(E16, GPIOF6, TXD4, SIG_DESC_SET(SCU80, 30)); + +#define C17 47 +SSSF_PIN_DECL(C17, GPIOF7, RXD4, SIG_DESC_SET(SCU80, 31)); + +#define AA22 54 +SSSF_PIN_DECL(AA22, GPIOG6, FLBUSY, SIG_DESC_SET(SCU84, 6)); + +#define U18 55 +SSSF_PIN_DECL(U18, GPIOG7, FLWP, SIG_DESC_SET(SCU84, 7)); + +#define UART6_DESC SIG_DESC_SET(SCU90, 7) +#define ROM16_DESC SIG_DESC_SET(SCU90, 6) +#define FLASH_WIDE SIG_DESC_SET(HW_STRAP1, 4) +#define BOOT_SRC_NOR { HW_STRAP1, GENMASK(1, 0), 0, 0 } + +#define A8 56 +SIG_EXPR_DECL(ROMD8, ROM16, ROM16_DESC); +SIG_EXPR_DECL(ROMD8, ROM16S, FLASH_WIDE, BOOT_SRC_NOR); +SIG_EXPR_LIST_DECL_DUAL(ROMD8, ROM16, ROM16S); +SIG_EXPR_LIST_DECL_SINGLE(NCTS6, NCTS6, UART6_DESC); +MS_PIN_DECL(A8, GPIOH0, ROMD8, NCTS6); + +#define C7 57 +SIG_EXPR_DECL(ROMD9, ROM16, ROM16_DESC); +SIG_EXPR_DECL(ROMD9, ROM16S, FLASH_WIDE, BOOT_SRC_NOR); +SIG_EXPR_LIST_DECL_DUAL(ROMD9, ROM16, ROM16S); +SIG_EXPR_LIST_DECL_SINGLE(NDCD6, NDCD6, UART6_DESC); +MS_PIN_DECL(C7, GPIOH1, ROMD9, NDCD6); + +#define B7 58 +SIG_EXPR_DECL(ROMD10, ROM16, ROM16_DESC); +SIG_EXPR_DECL(ROMD10, ROM16S, FLASH_WIDE, BOOT_SRC_NOR); +SIG_EXPR_LIST_DECL_DUAL(ROMD10, ROM16, ROM16S); +SIG_EXPR_LIST_DECL_SINGLE(NDSR6, NDSR6, UART6_DESC); +MS_PIN_DECL(B7, GPIOH2, ROMD10, NDSR6); + +#define A7 59 +SIG_EXPR_DECL(ROMD11, ROM16, ROM16_DESC); +SIG_EXPR_DECL(ROMD11, ROM16S, FLASH_WIDE, BOOT_SRC_NOR); +SIG_EXPR_LIST_DECL_DUAL(ROMD11, ROM16, ROM16S); +SIG_EXPR_LIST_DECL_SINGLE(NRI6, NRI6, UART6_DESC); +MS_PIN_DECL(A7, GPIOH3, ROMD11, NRI6); + +#define D7 60 +SIG_EXPR_DECL(ROMD12, ROM16, ROM16_DESC); +SIG_EXPR_DECL(ROMD12, ROM16S, FLASH_WIDE, BOOT_SRC_NOR); +SIG_EXPR_LIST_DECL_DUAL(ROMD12, ROM16, ROM16S); +SIG_EXPR_LIST_DECL_SINGLE(NDTR6, NDTR6, UART6_DESC); +MS_PIN_DECL(D7, GPIOH4, ROMD12, NDTR6); + +#define B6 61 +SIG_EXPR_DECL(ROMD13, ROM16, ROM16_DESC); +SIG_EXPR_DECL(ROMD13, ROM16S, FLASH_WIDE, BOOT_SRC_NOR); +SIG_EXPR_LIST_DECL_DUAL(ROMD13, ROM16, ROM16S); +SIG_EXPR_LIST_DECL_SINGLE(NRTS6, NRTS6, UART6_DESC); +MS_PIN_DECL(B6, GPIOH5, ROMD13, NRTS6); + +#define A6 62 +SIG_EXPR_DECL(ROMD14, ROM16, ROM16_DESC); +SIG_EXPR_DECL(ROMD14, ROM16S, FLASH_WIDE, BOOT_SRC_NOR); +SIG_EXPR_LIST_DECL_DUAL(ROMD14, ROM16, ROM16S); +SIG_EXPR_LIST_DECL_SINGLE(TXD6, TXD6, UART6_DESC); +MS_PIN_DECL(A6, GPIOH6, ROMD14, TXD6); + +#define E7 63 +SIG_EXPR_DECL(ROMD15, ROM16, ROM16_DESC); +SIG_EXPR_DECL(ROMD15, ROM16S, FLASH_WIDE, BOOT_SRC_NOR); +SIG_EXPR_LIST_DECL_DUAL(ROMD15, ROM16, ROM16S); +SIG_EXPR_LIST_DECL_SINGLE(RXD6, RXD6, UART6_DESC); +MS_PIN_DECL(E7, GPIOH7, ROMD15, RXD6); + +FUNC_GROUP_DECL(UART6, A8, C7, B7, A7, D7, B6, A6, E7); + +#define J3 75 +SSSF_PIN_DECL(J3, GPIOJ3, SGPMI, SIG_DESC_SET(SCU84, 11)); + +#define T4 76 +SSSF_PIN_DECL(T4, GPIOJ4, VGAHS, SIG_DESC_SET(SCU84, 12)); + +#define U2 77 +SSSF_PIN_DECL(U2, GPIOJ5, VGAVS, SIG_DESC_SET(SCU84, 13)); + +#define T2 78 +SSSF_PIN_DECL(T2, GPIOJ6, DDCCLK, SIG_DESC_SET(SCU84, 14)); + +#define T1 79 +SSSF_PIN_DECL(T1, GPIOJ7, DDCDAT, SIG_DESC_SET(SCU84, 15)); + +#define I2C5_DESC SIG_DESC_SET(SCU90, 18) + +#define E3 80 +SIG_EXPR_LIST_DECL_SINGLE(SCL5, I2C5, I2C5_DESC); +SS_PIN_DECL(E3, GPIOK0, SCL5); + +#define D2 81 +SIG_EXPR_LIST_DECL_SINGLE(SDA5, I2C5, I2C5_DESC); +SS_PIN_DECL(D2, GPIOK1, SDA5); + +FUNC_GROUP_DECL(I2C5, E3, D2); + +#define I2C6_DESC SIG_DESC_SET(SCU90, 19) + +#define C1 82 +SIG_EXPR_LIST_DECL_SINGLE(SCL6, I2C6, I2C6_DESC); +SS_PIN_DECL(C1, GPIOK2, SCL6); + +#define F4 83 +SIG_EXPR_LIST_DECL_SINGLE(SDA6, I2C6, I2C6_DESC); +SS_PIN_DECL(F4, GPIOK3, SDA6); + +FUNC_GROUP_DECL(I2C6, C1, F4); + +#define I2C7_DESC SIG_DESC_SET(SCU90, 20) + +#define E2 84 +SIG_EXPR_LIST_DECL_SINGLE(SCL7, I2C7, I2C7_DESC); +SS_PIN_DECL(E2, GPIOK4, SCL7); + +#define D1 85 +SIG_EXPR_LIST_DECL_SINGLE(SDA7, I2C7, I2C7_DESC); +SS_PIN_DECL(D1, GPIOK5, SDA7); + +FUNC_GROUP_DECL(I2C7, E2, D1); + +#define I2C8_DESC SIG_DESC_SET(SCU90, 21) + +#define G5 86 +SIG_EXPR_LIST_DECL_SINGLE(SCL8, I2C8, I2C8_DESC); +SS_PIN_DECL(G5, GPIOK6, SCL8); + +#define F3 87 +SIG_EXPR_LIST_DECL_SINGLE(SDA8, I2C8, I2C8_DESC); +SS_PIN_DECL(F3, GPIOK7, SDA8); + +FUNC_GROUP_DECL(I2C8, G5, F3); + +#define U1 88 +SSSF_PIN_DECL(U1, GPIOL0, NCTS1, SIG_DESC_SET(SCU84, 16)); + +#define VPI18_DESC { SCU90, GENMASK(5, 4), 1, 0 } +#define VPI24_DESC { SCU90, GENMASK(5, 4), 2, 0 } +#define VPI30_DESC { SCU90, GENMASK(5, 4), 3, 0 } + +#define T5 89 +#define T5_DESC SIG_DESC_SET(SCU84, 17) +SIG_EXPR_DECL(VPIDE, VPI18, VPI18_DESC, T5_DESC); +SIG_EXPR_DECL(VPIDE, VPI24, VPI24_DESC, T5_DESC); +SIG_EXPR_DECL(VPIDE, VPI30, VPI30_DESC, T5_DESC); +SIG_EXPR_LIST_DECL(VPIDE, SIG_EXPR_PTR(VPIDE, VPI18), + SIG_EXPR_PTR(VPIDE, VPI24), + SIG_EXPR_PTR(VPIDE, VPI30)); +SIG_EXPR_LIST_DECL_SINGLE(NDCD1, NDCD1, T5_DESC); +MS_PIN_DECL(T5, GPIOL1, VPIDE, NDCD1); +FUNC_GROUP_DECL(NDCD1, T5); + +#define U3 90 +#define U3_DESC SIG_DESC_SET(SCU84, 18) +SIG_EXPR_DECL(VPIODD, VPI18, VPI18_DESC, U3_DESC); +SIG_EXPR_DECL(VPIODD, VPI24, VPI24_DESC, U3_DESC); +SIG_EXPR_DECL(VPIODD, VPI30, VPI30_DESC, U3_DESC); +SIG_EXPR_LIST_DECL(VPIODD, SIG_EXPR_PTR(VPIODD, VPI18), + SIG_EXPR_PTR(VPIODD, VPI24), + SIG_EXPR_PTR(VPIODD, VPI30)); +SIG_EXPR_LIST_DECL_SINGLE(NDSR1, NDSR1, U3_DESC); +MS_PIN_DECL(U3, GPIOL2, VPIODD, NDSR1); +FUNC_GROUP_DECL(NDSR1, U3); + +#define V1 91 +#define V1_DESC SIG_DESC_SET(SCU84, 19) +SIG_EXPR_DECL(VPIHS, VPI18, VPI18_DESC, V1_DESC); +SIG_EXPR_DECL(VPIHS, VPI24, VPI24_DESC, V1_DESC); +SIG_EXPR_DECL(VPIHS, VPI30, VPI30_DESC, V1_DESC); +SIG_EXPR_LIST_DECL(VPIHS, SIG_EXPR_PTR(VPIHS, VPI18), + SIG_EXPR_PTR(VPIHS, VPI24), + SIG_EXPR_PTR(VPIHS, VPI30)); +SIG_EXPR_LIST_DECL_SINGLE(NRI1, NRI1, V1_DESC); +MS_PIN_DECL(V1, GPIOL3, VPIHS, NRI1); +FUNC_GROUP_DECL(NRI1, V1); + +#define U4 92 +#define U4_DESC SIG_DESC_SET(SCU84, 20) +SIG_EXPR_DECL(VPIVS, VPI18, VPI18_DESC, U4_DESC); +SIG_EXPR_DECL(VPIVS, VPI24, VPI24_DESC, U4_DESC); +SIG_EXPR_DECL(VPIVS, VPI30, VPI30_DESC, U4_DESC); +SIG_EXPR_LIST_DECL(VPIVS, SIG_EXPR_PTR(VPIVS, VPI18), + SIG_EXPR_PTR(VPIVS, VPI24), + SIG_EXPR_PTR(VPIVS, VPI30)); +SIG_EXPR_LIST_DECL_SINGLE(NDTR1, NDTR1, U4_DESC); +MS_PIN_DECL(U4, GPIOL4, VPIVS, NDTR1); +FUNC_GROUP_DECL(NDTR1, U4); + +#define V2 93 +#define V2_DESC SIG_DESC_SET(SCU84, 21) +SIG_EXPR_DECL(VPICLK, VPI18, VPI18_DESC, V2_DESC); +SIG_EXPR_DECL(VPICLK, VPI24, VPI24_DESC, V2_DESC); +SIG_EXPR_DECL(VPICLK, VPI30, VPI30_DESC, V2_DESC); +SIG_EXPR_LIST_DECL(VPICLK, SIG_EXPR_PTR(VPICLK, VPI18), + SIG_EXPR_PTR(VPICLK, VPI24), + SIG_EXPR_PTR(VPICLK, VPI30)); +SIG_EXPR_LIST_DECL_SINGLE(NRTS1, NRTS1, V2_DESC); +MS_PIN_DECL(V2, GPIOL5, VPICLK, NRTS1); +FUNC_GROUP_DECL(NRTS1, V2); + +#define W1 94 +#define W1_DESC SIG_DESC_SET(SCU84, 22) +SIG_EXPR_LIST_DECL_SINGLE(VPIB0, VPI30, VPI30_DESC, W1_DESC); +SIG_EXPR_LIST_DECL_SINGLE(TXD1, TXD1, W1_DESC); +MS_PIN_DECL(W1, GPIOL6, VPIB0, TXD1); +FUNC_GROUP_DECL(TXD1, W1); + +#define U5 95 +#define U5_DESC SIG_DESC_SET(SCU84, 23) +SIG_EXPR_LIST_DECL_SINGLE(VPIB1, VPI30, VPI30_DESC, U5_DESC); +SIG_EXPR_LIST_DECL_SINGLE(RXD1, RXD1, U5_DESC); +MS_PIN_DECL(U5, GPIOL7, VPIB1, RXD1); +FUNC_GROUP_DECL(RXD1, U5); + +#define W4 104 +#define W4_DESC SIG_DESC_SET(SCU88, 0) +SIG_EXPR_LIST_DECL_SINGLE(VPIG0, VPI30, VPI30_DESC, W4_DESC); +SIG_EXPR_LIST_DECL_SINGLE(PWM0, PWM0, W4_DESC); +MS_PIN_DECL(W4, GPION0, VPIG0, PWM0); +FUNC_GROUP_DECL(PWM0, W4); + +#define Y3 105 +#define Y3_DESC SIG_DESC_SET(SCU88, 1) +SIG_EXPR_LIST_DECL_SINGLE(VPIG1, VPI30, VPI30_DESC, Y3_DESC); +SIG_EXPR_LIST_DECL_SINGLE(PWM1, PWM1, Y3_DESC); +MS_PIN_DECL(Y3, GPION1, VPIG1, PWM1); +FUNC_GROUP_DECL(PWM1, Y3); + +#define AA2 106 +#define AA2_DESC SIG_DESC_SET(SCU88, 2) +SIG_EXPR_DECL(VPIG2, VPI18, VPI18_DESC, AA2_DESC); +SIG_EXPR_DECL(VPIG2, VPI24, VPI24_DESC, AA2_DESC); +SIG_EXPR_DECL(VPIG2, VPI30, VPI30_DESC, AA2_DESC); +SIG_EXPR_LIST_DECL(VPIG2, SIG_EXPR_PTR(VPIG2, VPI18), + SIG_EXPR_PTR(VPIG2, VPI24), + SIG_EXPR_PTR(VPIG2, VPI30)); +SIG_EXPR_LIST_DECL_SINGLE(PWM2, PWM2, AA2_DESC); +MS_PIN_DECL(AA2, GPION2, VPIG2, PWM2); +FUNC_GROUP_DECL(PWM2, AA2); + +#define AB1 107 +#define AB1_DESC SIG_DESC_SET(SCU88, 3) +SIG_EXPR_DECL(VPIG3, VPI18, VPI18_DESC, AB1_DESC); +SIG_EXPR_DECL(VPIG3, VPI24, VPI24_DESC, AB1_DESC); +SIG_EXPR_DECL(VPIG3, VPI30, VPI30_DESC, AB1_DESC); +SIG_EXPR_LIST_DECL(VPIG3, SIG_EXPR_PTR(VPIG3, VPI18), + SIG_EXPR_PTR(VPIG2, VPI24), + SIG_EXPR_PTR(VPIG2, VPI30)); +SIG_EXPR_LIST_DECL_SINGLE(PWM3, PWM3, AB1_DESC); +MS_PIN_DECL(AB1, GPION3, VPIG3, PWM3); +FUNC_GROUP_DECL(PWM3, AB1); + +#define W5 108 +#define W5_DESC SIG_DESC_SET(SCU88, 4) +SIG_EXPR_DECL(VPIG4, VPI18, VPI18_DESC, W5_DESC); +SIG_EXPR_DECL(VPIG4, VPI24, VPI24_DESC, W5_DESC); +SIG_EXPR_DECL(VPIG4, VPI30, VPI30_DESC, W5_DESC); +SIG_EXPR_LIST_DECL(VPIG4, SIG_EXPR_PTR(VPIG4, VPI18), + SIG_EXPR_PTR(VPIG2, VPI24), + SIG_EXPR_PTR(VPIG2, VPI30)); +SIG_EXPR_LIST_DECL_SINGLE(PWM4, PWM4, W5_DESC); +MS_PIN_DECL(W5, GPION4, VPIG4, PWM4); +FUNC_GROUP_DECL(PWM4, W5); + +#define Y4 109 +#define Y4_DESC SIG_DESC_SET(SCU88, 5) +SIG_EXPR_DECL(VPIG5, VPI18, VPI18_DESC, Y4_DESC); +SIG_EXPR_DECL(VPIG5, VPI24, VPI24_DESC, Y4_DESC); +SIG_EXPR_DECL(VPIG5, VPI30, VPI30_DESC, Y4_DESC); +SIG_EXPR_LIST_DECL(VPIG5, SIG_EXPR_PTR(VPIG5, VPI18), + SIG_EXPR_PTR(VPIG2, VPI24), + SIG_EXPR_PTR(VPIG2, VPI30)); +SIG_EXPR_LIST_DECL_SINGLE(PWM5, PWM5, Y4_DESC); +MS_PIN_DECL(Y4, GPION5, VPIG5, PWM5); +FUNC_GROUP_DECL(PWM5, Y4); + +#define AA3 110 +#define AA3_DESC SIG_DESC_SET(SCU88, 6) +SIG_EXPR_LIST_DECL_SINGLE(VPIG6, VPI30, VPI30_DESC, AA3_DESC); +SIG_EXPR_LIST_DECL_SINGLE(PWM6, PWM6, AA3_DESC); +MS_PIN_DECL(AA3, GPION6, VPIG6, PWM6); +FUNC_GROUP_DECL(PWM6, AA3); + +#define AB2 111 +#define AB2_DESC SIG_DESC_SET(SCU88, 7) +SIG_EXPR_LIST_DECL_SINGLE(VPIG7, VPI30, VPI30_DESC, AB2_DESC); +SIG_EXPR_LIST_DECL_SINGLE(PWM7, PWM7, AB2_DESC); +MS_PIN_DECL(AB2, GPION7, VPIG7, PWM7); +FUNC_GROUP_DECL(PWM7, AB2); + +#define V6 112 +SIG_EXPR_LIST_DECL_SINGLE(VPIG8, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 8)); +SS_PIN_DECL(V6, GPIOO0, VPIG8); + +#define Y5 113 +SIG_EXPR_LIST_DECL_SINGLE(VPIG9, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 9)); +SS_PIN_DECL(Y5, GPIOO1, VPIG9); + +FUNC_GROUP_DECL(VPI18, T5, U3, V1, U4, V2, AA22, W5, Y4, AA3, AB2); +FUNC_GROUP_DECL(VPI24, T5, U3, V1, U4, V2, AA22, W5, Y4, AA3, AB2, V6, Y5); +FUNC_GROUP_DECL(VPI30, T5, U3, V1, U4, V2, W1, U5, W4, Y3, AA22, W5, Y4, AA3, + AB2); + +#define Y7 125 +SIG_EXPR_LIST_DECL_SINGLE(GPIOP5, GPIOP5); +MS_PIN_DECL_(Y7, SIG_EXPR_LIST_PTR(GPIOP5)); + +#define AA7 126 +SSSF_PIN_DECL(AA7, GPIOP6, BMCINT, SIG_DESC_SET(SCU88, 22)); + +#define AB7 127 +SSSF_PIN_DECL(AB7, GPIOP7, FLACK, SIG_DESC_SET(SCU88, 23)); + +#define I2C3_DESC SIG_DESC_SET(SCU90, 16) + +#define D3 128 +SIG_EXPR_LIST_DECL_SINGLE(SCL3, I2C3, I2C3_DESC); +SS_PIN_DECL(D3, GPIOQ0, SCL3); + +#define C2 129 +SIG_EXPR_LIST_DECL_SINGLE(SDA3, I2C3, I2C3_DESC); +SS_PIN_DECL(C2, GPIOQ1, SDA3); + +FUNC_GROUP_DECL(I2C3, D3, C2); + +#define I2C4_DESC SIG_DESC_SET(SCU90, 17) + +#define B1 130 +SIG_EXPR_LIST_DECL_SINGLE(SCL4, I2C4, I2C4_DESC); +SS_PIN_DECL(B1, GPIOQ2, SCL4); + +#define F5 131 +SIG_EXPR_LIST_DECL_SINGLE(SDA4, I2C4, I2C4_DESC); +SS_PIN_DECL(F5, GPIOQ3, SDA4); + +FUNC_GROUP_DECL(I2C4, B1, F5); + +#define DASH9028_DESC SIG_DESC_SET(SCU90, 28) + +#define H2 134 +SIG_EXPR_LIST_DECL_SINGLE(DASHH2, DASHH2, DASH9028_DESC); +SS_PIN_DECL(H2, GPIOQ6, DASHH2); + +#define H1 135 +SIG_EXPR_LIST_DECL_SINGLE(DASHH1, DASHH1, DASH9028_DESC); +SS_PIN_DECL(H1, GPIOQ7, DASHH1); + +#define V20 136 +SSSF_PIN_DECL(V20, GPIOR0, ROMCS1, SIG_DESC_SET(SCU88, 24)); + +#define W21 137 +SSSF_PIN_DECL(W21, GPIOR1, ROMCS2, SIG_DESC_SET(SCU88, 25)); + +#define Y22 138 +SSSF_PIN_DECL(Y22, GPIOR2, ROMCS3, SIG_DESC_SET(SCU88, 26)); + +#define U19 139 +SSSF_PIN_DECL(U19, GPIOR3, ROMCS4, SIG_DESC_SET(SCU88, 27)); + +#define VPOOFF0_DESC { SCU94, GENMASK(1, 0), 0, 0 } +#define VPO12_DESC { SCU94, GENMASK(1, 0), 1, 0 } +#define VPO24_DESC { SCU94, GENMASK(1, 0), 2, 0 } +#define VPOOFF1_DESC { SCU94, GENMASK(1, 0), 3, 0 } +#define VPO_OFF_12 { SCU94, 0x2, 0, 0 } +#define VPO_24_OFF SIG_DESC_SET(SCU94, 1) + +#define V21 140 +#define V21_DESC SIG_DESC_SET(SCU88, 28) +SIG_EXPR_DECL(ROMA24, ROM8, V21_DESC, VPO_OFF_12); +SIG_EXPR_DECL(ROMA24, ROM16, V21_DESC, VPO_OFF_12); +SIG_EXPR_DECL(ROMA24, ROM16S, V21_DESC, VPO_OFF_12); +SIG_EXPR_LIST_DECL(ROMA24, SIG_EXPR_PTR(ROMA24, ROM8), + SIG_EXPR_PTR(ROMA24, ROM16), + SIG_EXPR_PTR(ROMA24, ROM16S)); +SIG_EXPR_LIST_DECL_SINGLE(VPOR6, VPO24, V21_DESC, VPO_24_OFF); +MS_PIN_DECL(V21, GPIOR4, ROMA24, VPOR6); + +#define W22 141 +#define W22_DESC SIG_DESC_SET(SCU88, 29) +SIG_EXPR_DECL(ROMA25, ROM8, W22_DESC, VPO_OFF_12); +SIG_EXPR_DECL(ROMA25, ROM16, W22_DESC, VPO_OFF_12); +SIG_EXPR_DECL(ROMA25, ROM16S, W22_DESC, VPO_OFF_12); +SIG_EXPR_LIST_DECL(ROMA25, SIG_EXPR_PTR(ROMA25, ROM8), + SIG_EXPR_PTR(ROMA25, ROM16), + SIG_EXPR_PTR(ROMA25, ROM16S)); +SIG_EXPR_LIST_DECL_SINGLE(VPOR7, VPO24, W22_DESC, VPO_24_OFF); +MS_PIN_DECL(W22, GPIOR5, ROMA25, VPOR7); + +#define C6 142 +SIG_EXPR_LIST_DECL_SINGLE(MDC1, MDIO1, SIG_DESC_SET(SCU88, 30)); +SS_PIN_DECL(C6, GPIOR6, MDC1); + +#define A5 143 +SIG_EXPR_LIST_DECL_SINGLE(MDIO1, MDIO1, SIG_DESC_SET(SCU88, 31)); +SS_PIN_DECL(A5, GPIOR7, MDIO1); + +FUNC_GROUP_DECL(MDIO1, C6, A5); + +#define U21 144 +#define U21_DESC SIG_DESC_SET(SCU8C, 0) +SIG_EXPR_DECL(ROMD4, ROM8, U21_DESC, VPOOFF0_DESC); +SIG_EXPR_DECL(ROMD4, ROM16, U21_DESC, VPOOFF0_DESC); +SIG_EXPR_DECL(ROMD4, ROM16S, U21_DESC, VPOOFF0_DESC); +SIG_EXPR_LIST_DECL(ROMD4, SIG_EXPR_PTR(ROMD4, ROM8), + SIG_EXPR_PTR(ROMD4, ROM16), + SIG_EXPR_PTR(ROMD4, ROM16S)); +SIG_EXPR_DECL(VPODE, VPO12, U21_DESC, VPO12_DESC); +SIG_EXPR_DECL(VPODE, VPO24, U21_DESC, VPO12_DESC); +SIG_EXPR_LIST_DECL_DUAL(VPODE, VPO12, VPO24); +MS_PIN_DECL(U21, GPIOS0, ROMD4, VPODE); + +#define T19 145 +#define T19_DESC SIG_DESC_SET(SCU8C, 1) +SIG_EXPR_DECL(ROMD5, ROM8, T19_DESC, VPOOFF0_DESC); +SIG_EXPR_DECL(ROMD5, ROM16, T19_DESC, VPOOFF0_DESC); +SIG_EXPR_DECL(ROMD5, ROM16S, T19_DESC, VPOOFF0_DESC); +SIG_EXPR_LIST_DECL(ROMD5, SIG_EXPR_PTR(ROMD5, ROM8), + SIG_EXPR_PTR(ROMD5, ROM16), + SIG_EXPR_PTR(ROMD5, ROM16S)); +SIG_EXPR_DECL(VPOHS, VPO12, T19_DESC, VPO12_DESC); +SIG_EXPR_DECL(VPOHS, VPO24, T19_DESC, VPO24_DESC); +SIG_EXPR_LIST_DECL_DUAL(VPOHS, VPO12, VPO24); +MS_PIN_DECL(T19, GPIOS1, ROMD5, VPOHS); + +#define V22 146 +#define V22_DESC SIG_DESC_SET(SCU8C, 2) +SIG_EXPR_DECL(ROMD6, ROM8, V22_DESC, VPOOFF0_DESC); +SIG_EXPR_DECL(ROMD6, ROM16, V22_DESC, VPOOFF0_DESC); +SIG_EXPR_DECL(ROMD6, ROM16S, V22_DESC, VPOOFF0_DESC); +SIG_EXPR_LIST_DECL(ROMD6, SIG_EXPR_PTR(ROMD6, ROM8), + SIG_EXPR_PTR(ROMD6, ROM16), + SIG_EXPR_PTR(ROMD6, ROM16S)); +SIG_EXPR_DECL(VPOVS, VPO12, V22_DESC, VPO12_DESC); +SIG_EXPR_DECL(VPOVS, VPO24, V22_DESC, VPO24_DESC); +SIG_EXPR_LIST_DECL_DUAL(VPOVS, VPO12, VPO24); +MS_PIN_DECL(V22, GPIOS2, ROMD6, VPOVS); + +#define U20 147 +#define U20_DESC SIG_DESC_SET(SCU8C, 3) +SIG_EXPR_DECL(ROMD7, ROM8, U20_DESC, VPOOFF0_DESC); +SIG_EXPR_DECL(ROMD7, ROM16, U20_DESC, VPOOFF0_DESC); +SIG_EXPR_DECL(ROMD7, ROM16S, U20_DESC, VPOOFF0_DESC); +SIG_EXPR_LIST_DECL(ROMD7, SIG_EXPR_PTR(ROMD7, ROM8), + SIG_EXPR_PTR(ROMD7, ROM16), + SIG_EXPR_PTR(ROMD7, ROM16S)); +SIG_EXPR_DECL(VPOCLK, VPO12, U20_DESC, VPO12_DESC); +SIG_EXPR_DECL(VPOCLK, VPO24, U20_DESC, VPO24_DESC); +SIG_EXPR_LIST_DECL_DUAL(VPOCLK, VPO12, VPO24); +MS_PIN_DECL(U20, GPIOS3, ROMD7, VPOCLK); + +#define R18 148 +#define ROMOE_DESC SIG_DESC_SET(SCU8C, 4) +SIG_EXPR_LIST_DECL_SINGLE(GPIOS4, GPIOS4); +SIG_EXPR_DECL(ROMOE, ROM8, ROMOE_DESC); +SIG_EXPR_DECL(ROMOE, ROM16, ROMOE_DESC); +SIG_EXPR_DECL(ROMOE, ROM16S, ROMOE_DESC); +SIG_EXPR_LIST_DECL(ROMOE, SIG_EXPR_PTR(ROMOE, ROM8), + SIG_EXPR_PTR(ROMOE, ROM16), + SIG_EXPR_PTR(ROMOE, ROM16S)); +MS_PIN_DECL_(R18, SIG_EXPR_LIST_PTR(ROMOE), SIG_EXPR_LIST_PTR(GPIOS4)); + +#define N21 149 +#define ROMWE_DESC SIG_DESC_SET(SCU8C, 5) +SIG_EXPR_LIST_DECL_SINGLE(GPIOS5, GPIOS5); +SIG_EXPR_DECL(ROMWE, ROM8, ROMWE_DESC); +SIG_EXPR_DECL(ROMWE, ROM16, ROMWE_DESC); +SIG_EXPR_DECL(ROMWE, ROM16S, ROMWE_DESC); +SIG_EXPR_LIST_DECL(ROMWE, SIG_EXPR_PTR(ROMWE, ROM8), + SIG_EXPR_PTR(ROMWE, ROM16), + SIG_EXPR_PTR(ROMWE, ROM16S)); +MS_PIN_DECL_(N21, SIG_EXPR_LIST_PTR(ROMWE), SIG_EXPR_LIST_PTR(GPIOS5)); + +#define L22 150 +#define L22_DESC SIG_DESC_SET(SCU8C, 6) +SIG_EXPR_DECL(ROMA22, ROM8, L22_DESC, VPO_OFF_12); +SIG_EXPR_DECL(ROMA22, ROM16, L22_DESC, VPO_OFF_12); +SIG_EXPR_DECL(ROMA22, ROM16S, L22_DESC, VPO_OFF_12); +SIG_EXPR_LIST_DECL(ROMA22, SIG_EXPR_PTR(ROMA22, ROM8), + SIG_EXPR_PTR(ROMA22, ROM16), + SIG_EXPR_PTR(ROMA22, ROM16S)); +SIG_EXPR_LIST_DECL_SINGLE(VPOR4, VPO24, L22_DESC, VPO_24_OFF); +MS_PIN_DECL(L22, GPIOS6, ROMA22, VPOR4); + +#define K18 151 +#define K18_DESC SIG_DESC_SET(SCU8C, 7) +SIG_EXPR_DECL(ROMA23, ROM8, K18_DESC, VPO_OFF_12); +SIG_EXPR_DECL(ROMA23, ROM16, K18_DESC, VPO_OFF_12); +SIG_EXPR_DECL(ROMA23, ROM16S, K18_DESC, VPO_OFF_12); +SIG_EXPR_LIST_DECL(ROMA23, SIG_EXPR_PTR(ROMA23, ROM8), + SIG_EXPR_PTR(ROMA23, ROM16), + SIG_EXPR_PTR(ROMA23, ROM16S)); +SIG_EXPR_LIST_DECL_SINGLE(VPOR5, VPO24, K18_DESC, VPO_24_OFF); +MS_PIN_DECL(K18, GPIOS7, ROMA23, VPOR5); + +FUNC_GROUP_DECL(ROM8, V20, U21, T19, V22, U20, R18, N21, L22, K18, W21, Y22, + U19); +FUNC_GROUP_DECL(ROM16, V20, U21, T19, V22, U20, R18, N21, L22, K18, + A8, C7, B7, A7, D7, B6, A6, E7, W21, Y22, U19); +FUNC_GROUP_DECL(VPO12, U21, T19, V22, U20); +FUNC_GROUP_DECL(VPO24, U21, T19, V22, U20, L22, K18, V21, W22); + +#define RMII1_DESC SIG_DESC_BIT(HW_STRAP1, 6, 0) + +#define A12 152 +SIG_EXPR_LIST_DECL_SINGLE(GPIOT0, GPIOT0, SIG_DESC_SET(SCUA0, 0)); +SIG_EXPR_LIST_DECL_SINGLE(RMII1TXEN, RMII1, RMII1_DESC); +SIG_EXPR_LIST_DECL_SINGLE(RGMII1TXCK, RGMII1); +MS_PIN_DECL_(A12, SIG_EXPR_LIST_PTR(GPIOT0), SIG_EXPR_LIST_PTR(RMII1TXEN), + SIG_EXPR_LIST_PTR(RGMII1TXCK)); + +#define B12 153 +SIG_EXPR_LIST_DECL_SINGLE(GPIOT1, GPIOT1, SIG_DESC_SET(SCUA0, 1)); +SIG_EXPR_LIST_DECL_SINGLE(DASHB12, RMII1, RMII1_DESC); +SIG_EXPR_LIST_DECL_SINGLE(RGMII1TXCTL, RGMII1); +MS_PIN_DECL_(B12, SIG_EXPR_LIST_PTR(GPIOT1), SIG_EXPR_LIST_PTR(DASHB12), + SIG_EXPR_LIST_PTR(RGMII1TXCTL)); + +#define C12 154 +SIG_EXPR_LIST_DECL_SINGLE(GPIOT2, GPIOT2, SIG_DESC_SET(SCUA0, 2)); +SIG_EXPR_LIST_DECL_SINGLE(RMII1TXD0, RMII1, RMII1_DESC); +SIG_EXPR_LIST_DECL_SINGLE(RGMII1TXD0, RGMII1); +MS_PIN_DECL_(C12, SIG_EXPR_LIST_PTR(GPIOT2), SIG_EXPR_LIST_PTR(RMII1TXD0), + SIG_EXPR_LIST_PTR(RGMII1TXD0)); + +#define D12 155 +SIG_EXPR_LIST_DECL_SINGLE(GPIOT3, GPIOT3, SIG_DESC_SET(SCUA0, 3)); +SIG_EXPR_LIST_DECL_SINGLE(RMII1TXD1, RMII1, RMII1_DESC); +SIG_EXPR_LIST_DECL_SINGLE(RGMII1TXD1, RGMII1); +MS_PIN_DECL_(D12, SIG_EXPR_LIST_PTR(GPIOT3), SIG_EXPR_LIST_PTR(RMII1TXD1), + SIG_EXPR_LIST_PTR(RGMII1TXD1)); + +#define E12 156 +SIG_EXPR_LIST_DECL_SINGLE(GPIOT4, GPIOT4, SIG_DESC_SET(SCUA0, 4)); +SIG_EXPR_LIST_DECL_SINGLE(DASHE12, RMII1, RMII1_DESC); +SIG_EXPR_LIST_DECL_SINGLE(RGMII1TXD2, RGMII1); +MS_PIN_DECL_(E12, SIG_EXPR_LIST_PTR(GPIOT4), SIG_EXPR_LIST_PTR(DASHE12), + SIG_EXPR_LIST_PTR(RGMII1TXD2)); + +#define A13 157 +SIG_EXPR_LIST_DECL_SINGLE(GPIOT5, GPIOT5, SIG_DESC_SET(SCUA0, 5)); +SIG_EXPR_LIST_DECL_SINGLE(DASHA13, RMII1, RMII1_DESC); +SIG_EXPR_LIST_DECL_SINGLE(RGMII1TXD3, RGMII1); +MS_PIN_DECL_(A13, SIG_EXPR_LIST_PTR(GPIOT5), SIG_EXPR_LIST_PTR(DASHA13), + SIG_EXPR_LIST_PTR(RGMII1TXD3)); + +#define E11 164 +SIG_EXPR_LIST_DECL_SINGLE(GPIOU4, GPIOU4, SIG_DESC_SET(SCUA0, 12)); +SIG_EXPR_LIST_DECL_SINGLE(RMII1RCLK, RMII1, RMII1_DESC); +SIG_EXPR_LIST_DECL_SINGLE(RGMII1RXCK, RGMII1); +MS_PIN_DECL_(E11, SIG_EXPR_LIST_PTR(GPIOU4), SIG_EXPR_LIST_PTR(RMII1RCLK), + SIG_EXPR_LIST_PTR(RGMII1RXCK)); + +#define D11 165 +SIG_EXPR_LIST_DECL_SINGLE(GPIOU5, GPIOU5, SIG_DESC_SET(SCUA0, 13)); +SIG_EXPR_LIST_DECL_SINGLE(DASHD11, RMII1, RMII1_DESC); +SIG_EXPR_LIST_DECL_SINGLE(RGMII1RXCTL, RGMII1); +MS_PIN_DECL_(D11, SIG_EXPR_LIST_PTR(GPIOU5), SIG_EXPR_LIST_PTR(DASHD11), + SIG_EXPR_LIST_PTR(RGMII1RXCTL)); + +#define C11 166 +SIG_EXPR_LIST_DECL_SINGLE(GPIOU6, GPIOU6, SIG_DESC_SET(SCUA0, 14)); +SIG_EXPR_LIST_DECL_SINGLE(RMII1RXD0, RMII1, RMII1_DESC); +SIG_EXPR_LIST_DECL_SINGLE(RGMII1RXD0, RGMII1); +MS_PIN_DECL_(C11, SIG_EXPR_LIST_PTR(GPIOU6), SIG_EXPR_LIST_PTR(RMII1RXD0), + SIG_EXPR_LIST_PTR(RGMII1RXD0)); + +#define B11 167 +SIG_EXPR_LIST_DECL_SINGLE(GPIOU7, GPIOU7, SIG_DESC_SET(SCUA0, 15)); +SIG_EXPR_LIST_DECL_SINGLE(RMII1RXD1, RMII1, RMII1_DESC); +SIG_EXPR_LIST_DECL_SINGLE(RGMII1RXD1, RGMII1); +MS_PIN_DECL_(B11, SIG_EXPR_LIST_PTR(GPIOU7), SIG_EXPR_LIST_PTR(RMII1RXD1), + SIG_EXPR_LIST_PTR(RGMII1RXD1)); + +#define A11 168 +SIG_EXPR_LIST_DECL_SINGLE(GPIOV0, GPIOV0, SIG_DESC_SET(SCUA0, 16)); +SIG_EXPR_LIST_DECL_SINGLE(RMII1CRSDV, RMII1, RMII1_DESC); +SIG_EXPR_LIST_DECL_SINGLE(RGMII1RXD2, RGMII1); +MS_PIN_DECL_(A11, SIG_EXPR_LIST_PTR(GPIOV0), SIG_EXPR_LIST_PTR(RMII1CRSDV), + SIG_EXPR_LIST_PTR(RGMII1RXD2)); + +#define E10 169 +SIG_EXPR_LIST_DECL_SINGLE(GPIOV1, GPIOV1, SIG_DESC_SET(SCUA0, 17)); +SIG_EXPR_LIST_DECL_SINGLE(RMII1RXER, RMII1, RMII1_DESC); +SIG_EXPR_LIST_DECL_SINGLE(RGMII1RXD3, RGMII1); +MS_PIN_DECL_(E10, SIG_EXPR_LIST_PTR(GPIOV1), SIG_EXPR_LIST_PTR(RMII1RXER), + SIG_EXPR_LIST_PTR(RGMII1RXD3)); + +FUNC_GROUP_DECL(RMII1, A12, B12, C12, D12, E12, A13, E11, D11, C11, B11, A11, + E10); +FUNC_GROUP_DECL(RGMII1, A12, B12, C12, D12, E12, A13, E11, D11, C11, B11, A11, + E10); + +/* Note we account for GPIOY4-GPIOY7 even though they're not valid, thus 216 + * pins becomes 220. + */ +#define ASPEED_G4_NR_PINS 220 + +/* Pins, groups and functions are sort(1):ed alphabetically for sanity */ + +static struct pinctrl_pin_desc aspeed_g4_pins[ASPEED_G4_NR_PINS] = { + ASPEED_PINCTRL_PIN(A1), + ASPEED_PINCTRL_PIN(A11), + ASPEED_PINCTRL_PIN(A12), + ASPEED_PINCTRL_PIN(A13), + ASPEED_PINCTRL_PIN(A15), + ASPEED_PINCTRL_PIN(A18), + ASPEED_PINCTRL_PIN(A2), + ASPEED_PINCTRL_PIN(A3), + ASPEED_PINCTRL_PIN(A4), + ASPEED_PINCTRL_PIN(A5), + ASPEED_PINCTRL_PIN(A6), + ASPEED_PINCTRL_PIN(A7), + ASPEED_PINCTRL_PIN(A8), + ASPEED_PINCTRL_PIN(AA2), + ASPEED_PINCTRL_PIN(AA22), + ASPEED_PINCTRL_PIN(AA3), + ASPEED_PINCTRL_PIN(AA7), + ASPEED_PINCTRL_PIN(AB1), + ASPEED_PINCTRL_PIN(AB2), + ASPEED_PINCTRL_PIN(AB7), + ASPEED_PINCTRL_PIN(B1), + ASPEED_PINCTRL_PIN(B11), + ASPEED_PINCTRL_PIN(B12), + ASPEED_PINCTRL_PIN(B14), + ASPEED_PINCTRL_PIN(B15), + ASPEED_PINCTRL_PIN(B19), + ASPEED_PINCTRL_PIN(B2), + ASPEED_PINCTRL_PIN(B3), + ASPEED_PINCTRL_PIN(B4), + ASPEED_PINCTRL_PIN(B6), + ASPEED_PINCTRL_PIN(B7), + ASPEED_PINCTRL_PIN(C1), + ASPEED_PINCTRL_PIN(C11), + ASPEED_PINCTRL_PIN(C12), + ASPEED_PINCTRL_PIN(C14), + ASPEED_PINCTRL_PIN(C15), + ASPEED_PINCTRL_PIN(C17), + ASPEED_PINCTRL_PIN(C2), + ASPEED_PINCTRL_PIN(C3), + ASPEED_PINCTRL_PIN(C4), + ASPEED_PINCTRL_PIN(C5), + ASPEED_PINCTRL_PIN(C6), + ASPEED_PINCTRL_PIN(C7), + ASPEED_PINCTRL_PIN(D1), + ASPEED_PINCTRL_PIN(D11), + ASPEED_PINCTRL_PIN(D12), + ASPEED_PINCTRL_PIN(D14), + ASPEED_PINCTRL_PIN(D15), + ASPEED_PINCTRL_PIN(D16), + ASPEED_PINCTRL_PIN(D17), + ASPEED_PINCTRL_PIN(D18), + ASPEED_PINCTRL_PIN(D2), + ASPEED_PINCTRL_PIN(D3), + ASPEED_PINCTRL_PIN(D4), + ASPEED_PINCTRL_PIN(D5), + ASPEED_PINCTRL_PIN(D7), + ASPEED_PINCTRL_PIN(E10), + ASPEED_PINCTRL_PIN(E11), + ASPEED_PINCTRL_PIN(E12), + ASPEED_PINCTRL_PIN(E14), + ASPEED_PINCTRL_PIN(E16), + ASPEED_PINCTRL_PIN(E2), + ASPEED_PINCTRL_PIN(E3), + ASPEED_PINCTRL_PIN(E5), + ASPEED_PINCTRL_PIN(E7), + ASPEED_PINCTRL_PIN(F3), + ASPEED_PINCTRL_PIN(F4), + ASPEED_PINCTRL_PIN(F5), + ASPEED_PINCTRL_PIN(G5), + ASPEED_PINCTRL_PIN(H1), + ASPEED_PINCTRL_PIN(H19), + ASPEED_PINCTRL_PIN(H2), + ASPEED_PINCTRL_PIN(H20), + ASPEED_PINCTRL_PIN(J3), + ASPEED_PINCTRL_PIN(K18), + ASPEED_PINCTRL_PIN(L22), + ASPEED_PINCTRL_PIN(N21), + ASPEED_PINCTRL_PIN(R18), + ASPEED_PINCTRL_PIN(T1), + ASPEED_PINCTRL_PIN(T19), + ASPEED_PINCTRL_PIN(T2), + ASPEED_PINCTRL_PIN(T4), + ASPEED_PINCTRL_PIN(T5), + ASPEED_PINCTRL_PIN(U1), + ASPEED_PINCTRL_PIN(U18), + ASPEED_PINCTRL_PIN(U19), + ASPEED_PINCTRL_PIN(U2), + ASPEED_PINCTRL_PIN(U20), + ASPEED_PINCTRL_PIN(U21), + ASPEED_PINCTRL_PIN(U3), + ASPEED_PINCTRL_PIN(U4), + ASPEED_PINCTRL_PIN(U5), + ASPEED_PINCTRL_PIN(V1), + ASPEED_PINCTRL_PIN(V2), + ASPEED_PINCTRL_PIN(V20), + ASPEED_PINCTRL_PIN(V21), + ASPEED_PINCTRL_PIN(V22), + ASPEED_PINCTRL_PIN(V6), + ASPEED_PINCTRL_PIN(W1), + ASPEED_PINCTRL_PIN(W21), + ASPEED_PINCTRL_PIN(W22), + ASPEED_PINCTRL_PIN(W4), + ASPEED_PINCTRL_PIN(W5), + ASPEED_PINCTRL_PIN(Y22), + ASPEED_PINCTRL_PIN(Y3), + ASPEED_PINCTRL_PIN(Y4), + ASPEED_PINCTRL_PIN(Y5), + ASPEED_PINCTRL_PIN(Y7), +}; + +static const struct aspeed_pin_group aspeed_g4_groups[] = { + ASPEED_PINCTRL_GROUP(ACPI), + ASPEED_PINCTRL_GROUP(BMCINT), + ASPEED_PINCTRL_GROUP(DDCCLK), + ASPEED_PINCTRL_GROUP(DDCDAT), + ASPEED_PINCTRL_GROUP(FLACK), + ASPEED_PINCTRL_GROUP(FLBUSY), + ASPEED_PINCTRL_GROUP(FLWP), + ASPEED_PINCTRL_GROUP(GPID0), + ASPEED_PINCTRL_GROUP(GPIE0), + ASPEED_PINCTRL_GROUP(GPIE2), + ASPEED_PINCTRL_GROUP(GPIE4), + ASPEED_PINCTRL_GROUP(GPIE6), + ASPEED_PINCTRL_GROUP(I2C10), + ASPEED_PINCTRL_GROUP(I2C11), + ASPEED_PINCTRL_GROUP(I2C12), + ASPEED_PINCTRL_GROUP(I2C13), + ASPEED_PINCTRL_GROUP(I2C3), + ASPEED_PINCTRL_GROUP(I2C4), + ASPEED_PINCTRL_GROUP(I2C5), + ASPEED_PINCTRL_GROUP(I2C6), + ASPEED_PINCTRL_GROUP(I2C7), + ASPEED_PINCTRL_GROUP(I2C8), + ASPEED_PINCTRL_GROUP(I2C9), + ASPEED_PINCTRL_GROUP(LPCPD), + ASPEED_PINCTRL_GROUP(LPCPME), + ASPEED_PINCTRL_GROUP(LPCPME), + ASPEED_PINCTRL_GROUP(LPCSMI), + ASPEED_PINCTRL_GROUP(MDIO1), + ASPEED_PINCTRL_GROUP(MDIO2), + ASPEED_PINCTRL_GROUP(NCTS1), + ASPEED_PINCTRL_GROUP(NCTS3), + ASPEED_PINCTRL_GROUP(NCTS4), + ASPEED_PINCTRL_GROUP(NDCD1), + ASPEED_PINCTRL_GROUP(NDCD3), + ASPEED_PINCTRL_GROUP(NDCD4), + ASPEED_PINCTRL_GROUP(NDSR1), + ASPEED_PINCTRL_GROUP(NDSR3), + ASPEED_PINCTRL_GROUP(NDTR1), + ASPEED_PINCTRL_GROUP(NDTR3), + ASPEED_PINCTRL_GROUP(NRI1), + ASPEED_PINCTRL_GROUP(NRI3), + ASPEED_PINCTRL_GROUP(NRI4), + ASPEED_PINCTRL_GROUP(NRTS1), + ASPEED_PINCTRL_GROUP(NRTS3), + ASPEED_PINCTRL_GROUP(PWM0), + ASPEED_PINCTRL_GROUP(PWM1), + ASPEED_PINCTRL_GROUP(PWM2), + ASPEED_PINCTRL_GROUP(PWM3), + ASPEED_PINCTRL_GROUP(PWM4), + ASPEED_PINCTRL_GROUP(PWM5), + ASPEED_PINCTRL_GROUP(PWM6), + ASPEED_PINCTRL_GROUP(PWM7), + ASPEED_PINCTRL_GROUP(RGMII1), + ASPEED_PINCTRL_GROUP(RMII1), + ASPEED_PINCTRL_GROUP(ROM16), + ASPEED_PINCTRL_GROUP(ROM8), + ASPEED_PINCTRL_GROUP(ROMCS1), + ASPEED_PINCTRL_GROUP(ROMCS2), + ASPEED_PINCTRL_GROUP(ROMCS3), + ASPEED_PINCTRL_GROUP(ROMCS4), + ASPEED_PINCTRL_GROUP(RXD1), + ASPEED_PINCTRL_GROUP(RXD3), + ASPEED_PINCTRL_GROUP(RXD4), + ASPEED_PINCTRL_GROUP(SD1), + ASPEED_PINCTRL_GROUP(SGPMI), + ASPEED_PINCTRL_GROUP(SIOPBI), + ASPEED_PINCTRL_GROUP(SIOPBO), + ASPEED_PINCTRL_GROUP(TIMER3), + ASPEED_PINCTRL_GROUP(TIMER5), + ASPEED_PINCTRL_GROUP(TIMER6), + ASPEED_PINCTRL_GROUP(TIMER7), + ASPEED_PINCTRL_GROUP(TIMER8), + ASPEED_PINCTRL_GROUP(TXD1), + ASPEED_PINCTRL_GROUP(TXD3), + ASPEED_PINCTRL_GROUP(TXD4), + ASPEED_PINCTRL_GROUP(UART6), + ASPEED_PINCTRL_GROUP(VGAHS), + ASPEED_PINCTRL_GROUP(VGAVS), + ASPEED_PINCTRL_GROUP(VPI18), + ASPEED_PINCTRL_GROUP(VPI24), + ASPEED_PINCTRL_GROUP(VPI30), + ASPEED_PINCTRL_GROUP(VPO12), + ASPEED_PINCTRL_GROUP(VPO24), +}; + +static const struct aspeed_pin_function aspeed_g4_functions[] = { + ASPEED_PINCTRL_FUNC(ACPI), + ASPEED_PINCTRL_FUNC(BMCINT), + ASPEED_PINCTRL_FUNC(DDCCLK), + ASPEED_PINCTRL_FUNC(DDCDAT), + ASPEED_PINCTRL_FUNC(FLACK), + ASPEED_PINCTRL_FUNC(FLBUSY), + ASPEED_PINCTRL_FUNC(FLWP), + ASPEED_PINCTRL_FUNC(GPID0), + ASPEED_PINCTRL_FUNC(GPIE0), + ASPEED_PINCTRL_FUNC(GPIE2), + ASPEED_PINCTRL_FUNC(GPIE4), + ASPEED_PINCTRL_FUNC(GPIE6), + ASPEED_PINCTRL_FUNC(I2C10), + ASPEED_PINCTRL_FUNC(I2C11), + ASPEED_PINCTRL_FUNC(I2C12), + ASPEED_PINCTRL_FUNC(I2C13), + ASPEED_PINCTRL_FUNC(I2C3), + ASPEED_PINCTRL_FUNC(I2C4), + ASPEED_PINCTRL_FUNC(I2C5), + ASPEED_PINCTRL_FUNC(I2C6), + ASPEED_PINCTRL_FUNC(I2C7), + ASPEED_PINCTRL_FUNC(I2C8), + ASPEED_PINCTRL_FUNC(I2C9), + ASPEED_PINCTRL_FUNC(LPCPD), + ASPEED_PINCTRL_FUNC(LPCPME), + ASPEED_PINCTRL_FUNC(LPCSMI), + ASPEED_PINCTRL_FUNC(MDIO1), + ASPEED_PINCTRL_FUNC(MDIO2), + ASPEED_PINCTRL_FUNC(NCTS1), + ASPEED_PINCTRL_FUNC(NCTS3), + ASPEED_PINCTRL_FUNC(NCTS4), + ASPEED_PINCTRL_FUNC(NDCD1), + ASPEED_PINCTRL_FUNC(NDCD3), + ASPEED_PINCTRL_FUNC(NDCD4), + ASPEED_PINCTRL_FUNC(NDSR1), + ASPEED_PINCTRL_FUNC(NDSR3), + ASPEED_PINCTRL_FUNC(NDTR1), + ASPEED_PINCTRL_FUNC(NDTR3), + ASPEED_PINCTRL_FUNC(NRI1), + ASPEED_PINCTRL_FUNC(NRI3), + ASPEED_PINCTRL_FUNC(NRI4), + ASPEED_PINCTRL_FUNC(NRTS1), + ASPEED_PINCTRL_FUNC(NRTS3), + ASPEED_PINCTRL_FUNC(PWM0), + ASPEED_PINCTRL_FUNC(PWM1), + ASPEED_PINCTRL_FUNC(PWM2), + ASPEED_PINCTRL_FUNC(PWM3), + ASPEED_PINCTRL_FUNC(PWM4), + ASPEED_PINCTRL_FUNC(PWM5), + ASPEED_PINCTRL_FUNC(PWM6), + ASPEED_PINCTRL_FUNC(PWM7), + ASPEED_PINCTRL_FUNC(RGMII1), + ASPEED_PINCTRL_FUNC(RMII1), + ASPEED_PINCTRL_FUNC(ROM16), + ASPEED_PINCTRL_FUNC(ROM8), + ASPEED_PINCTRL_FUNC(ROMCS1), + ASPEED_PINCTRL_FUNC(ROMCS2), + ASPEED_PINCTRL_FUNC(ROMCS3), + ASPEED_PINCTRL_FUNC(ROMCS4), + ASPEED_PINCTRL_FUNC(RXD1), + ASPEED_PINCTRL_FUNC(RXD3), + ASPEED_PINCTRL_FUNC(RXD4), + ASPEED_PINCTRL_FUNC(SD1), + ASPEED_PINCTRL_FUNC(SGPMI), + ASPEED_PINCTRL_FUNC(SIOPBI), + ASPEED_PINCTRL_FUNC(SIOPBO), + ASPEED_PINCTRL_FUNC(TIMER3), + ASPEED_PINCTRL_FUNC(TIMER5), + ASPEED_PINCTRL_FUNC(TIMER6), + ASPEED_PINCTRL_FUNC(TIMER7), + ASPEED_PINCTRL_FUNC(TIMER8), + ASPEED_PINCTRL_FUNC(TXD1), + ASPEED_PINCTRL_FUNC(TXD3), + ASPEED_PINCTRL_FUNC(TXD4), + ASPEED_PINCTRL_FUNC(UART6), + ASPEED_PINCTRL_FUNC(VGAHS), + ASPEED_PINCTRL_FUNC(VGAVS), + ASPEED_PINCTRL_FUNC(VPI18), + ASPEED_PINCTRL_FUNC(VPI24), + ASPEED_PINCTRL_FUNC(VPI30), + ASPEED_PINCTRL_FUNC(VPO12), + ASPEED_PINCTRL_FUNC(VPO24), +}; + +static struct aspeed_pinctrl_data aspeed_g4_pinctrl_data = { + .pins = aspeed_g4_pins, + .npins = ARRAY_SIZE(aspeed_g4_pins), + .groups = aspeed_g4_groups, + .ngroups = ARRAY_SIZE(aspeed_g4_groups), + .functions = aspeed_g4_functions, + .nfunctions = ARRAY_SIZE(aspeed_g4_functions), +}; + +static struct pinmux_ops aspeed_g4_pinmux_ops = { + .get_functions_count = aspeed_pinmux_get_fn_count, + .get_function_name = aspeed_pinmux_get_fn_name, + .get_function_groups = aspeed_pinmux_get_fn_groups, + .set_mux = aspeed_pinmux_set_mux, + .gpio_request_enable = aspeed_gpio_request_enable, + .strict = true, +}; + +static struct pinctrl_ops aspeed_g4_pinctrl_ops = { + .get_groups_count = aspeed_pinctrl_get_groups_count, + .get_group_name = aspeed_pinctrl_get_group_name, + .get_group_pins = aspeed_pinctrl_get_group_pins, + .pin_dbg_show = aspeed_pinctrl_pin_dbg_show, + .dt_node_to_map = pinconf_generic_dt_node_to_map_pin, + .dt_free_map = pinctrl_utils_free_map, +}; + +static struct pinctrl_desc aspeed_g4_pinctrl_desc = { + .name = "aspeed-g4-pinctrl", + .pins = aspeed_g4_pins, + .npins = ARRAY_SIZE(aspeed_g4_pins), + .pctlops = &aspeed_g4_pinctrl_ops, + .pmxops = &aspeed_g4_pinmux_ops, +}; + +static int aspeed_g4_pinctrl_probe(struct platform_device *pdev) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(aspeed_g4_pins); i++) + aspeed_g4_pins[i].number = i; + + return aspeed_pinctrl_probe(pdev, &aspeed_g4_pinctrl_desc, + &aspeed_g4_pinctrl_data); +} + +static const struct of_device_id aspeed_g4_pinctrl_of_match[] = { + { .compatible = "aspeed,ast2400-pinctrl", }, + { .compatible = "aspeed,g4-pinctrl", }, + { }, +}; + +static struct platform_driver aspeed_g4_pinctrl_driver = { + .probe = aspeed_g4_pinctrl_probe, + .driver = { + .name = "aspeed-g4-pinctrl", + .of_match_table = aspeed_g4_pinctrl_of_match, + }, +}; + +static int aspeed_g4_pinctrl_init(void) +{ + return platform_driver_register(&aspeed_g4_pinctrl_driver); +} + +arch_initcall(aspeed_g4_pinctrl_init); -- cgit 1.4.1 From 56e57cb6c07f124911dfe9a6b496f541ed166931 Mon Sep 17 00:00:00 2001 From: Andrew Jeffery Date: Tue, 30 Aug 2016 17:24:26 +0930 Subject: pinctrl: Add pinctrl-aspeed-g5 driver A small subset of pins and functions are exposed. The selection of pins and functions is driven by the development of OpenBMC[1] on the AST2500 SoC, particularly around booting the IBM Witherspoon platform. [1] https://github.com/openbmc/docs Signed-off-by: Andrew Jeffery Reviewed-by: Joel Stanley Signed-off-by: Linus Walleij --- drivers/pinctrl/aspeed/Kconfig | 8 + drivers/pinctrl/aspeed/Makefile | 1 + drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c | 808 +++++++++++++++++++++++++++++ 3 files changed, 817 insertions(+) create mode 100644 drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c diff --git a/drivers/pinctrl/aspeed/Kconfig b/drivers/pinctrl/aspeed/Kconfig index 1f3d74549381..998eabef3a65 100644 --- a/drivers/pinctrl/aspeed/Kconfig +++ b/drivers/pinctrl/aspeed/Kconfig @@ -14,3 +14,11 @@ config PINCTRL_ASPEED_G4 help Say Y here to enable pin controller support for Aspeed's 4th generation SoCs. GPIO is provided by a separate GPIO driver. + +config PINCTRL_ASPEED_G5 + bool "Aspeed G5 SoC pin control" + depends on (MACH_ASPEED_G5 || COMPILE_TEST) && OF + select PINCTRL_ASPEED + help + Say Y here to enable pin controller support for Aspeed's 5th + generation SoCs. GPIO is provided by a separate GPIO driver. diff --git a/drivers/pinctrl/aspeed/Makefile b/drivers/pinctrl/aspeed/Makefile index 8675d6fd82df..191ed0fc1804 100644 --- a/drivers/pinctrl/aspeed/Makefile +++ b/drivers/pinctrl/aspeed/Makefile @@ -3,3 +3,4 @@ ccflags-y += -Woverride-init obj-$(CONFIG_PINCTRL_ASPEED) += pinctrl-aspeed.o obj-$(CONFIG_PINCTRL_ASPEED_G4) += pinctrl-aspeed-g4.o +obj-$(CONFIG_PINCTRL_ASPEED_G5) += pinctrl-aspeed-g5.o diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c b/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c new file mode 100644 index 000000000000..e1ab864e1a7f --- /dev/null +++ b/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c @@ -0,0 +1,808 @@ +/* + * Copyright (C) 2016 IBM Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "../core.h" +#include "../pinctrl-utils.h" +#include "pinctrl-aspeed.h" + +#define ASPEED_G5_NR_PINS 228 + +#define COND1 SIG_DESC_BIT(SCU90, 6, 0) +#define COND2 { SCU94, GENMASK(1, 0), 0, 0 } + +#define B14 0 +SSSF_PIN_DECL(B14, GPIOA0, MAC1LINK, SIG_DESC_SET(SCU80, 0)); + +#define E13 3 +SSSF_PIN_DECL(E13, GPIOA3, TIMER4, SIG_DESC_SET(SCU80, 3)); + +#define I2C9_DESC SIG_DESC_SET(SCU90, 22) + +#define C14 4 +SIG_EXPR_LIST_DECL_SINGLE(SCL9, I2C9, I2C9_DESC, COND1); +SIG_EXPR_LIST_DECL_SINGLE(TIMER5, TIMER5, SIG_DESC_SET(SCU80, 4), COND1); +MS_PIN_DECL(C14, GPIOA4, SCL9, TIMER5); + +FUNC_GROUP_DECL(TIMER5, C14); + +#define A13 5 +SIG_EXPR_LIST_DECL_SINGLE(SDA9, I2C9, I2C9_DESC, COND1); +SIG_EXPR_LIST_DECL_SINGLE(TIMER6, TIMER6, SIG_DESC_SET(SCU80, 5), COND1); +MS_PIN_DECL(A13, GPIOA5, SDA9, TIMER6); + +FUNC_GROUP_DECL(TIMER6, A13); + +FUNC_GROUP_DECL(I2C9, C14, A13); + +#define MDIO2_DESC SIG_DESC_SET(SCU90, 2) + +#define C13 6 +SIG_EXPR_LIST_DECL_SINGLE(MDC2, MDIO2, MDIO2_DESC, COND1); +SIG_EXPR_LIST_DECL_SINGLE(TIMER7, TIMER7, SIG_DESC_SET(SCU80, 6), COND1); +MS_PIN_DECL(C13, GPIOA6, MDC2, TIMER7); + +FUNC_GROUP_DECL(TIMER7, C13); + +#define B13 7 +SIG_EXPR_LIST_DECL_SINGLE(MDIO2, MDIO2, MDIO2_DESC, COND1); +SIG_EXPR_LIST_DECL_SINGLE(TIMER8, TIMER8, SIG_DESC_SET(SCU80, 7), COND1); +MS_PIN_DECL(B13, GPIOA7, MDIO2, TIMER8); + +FUNC_GROUP_DECL(TIMER8, B13); + +FUNC_GROUP_DECL(MDIO2, C13, B13); + +#define H20 15 +GPIO_PIN_DECL(H20, GPIOB7); + +#define SD1_DESC SIG_DESC_SET(SCU90, 0) + +#define C12 16 +#define I2C10_DESC SIG_DESC_SET(SCU90, 23) +SIG_EXPR_LIST_DECL_SINGLE(SD1CLK, SD1, SD1_DESC); +SIG_EXPR_LIST_DECL_SINGLE(SCL10, I2C10, I2C10_DESC); +MS_PIN_DECL(C12, GPIOC0, SD1CLK, SCL10); + +#define A12 17 +SIG_EXPR_LIST_DECL_SINGLE(SD1CMD, SD1, SD1_DESC); +SIG_EXPR_LIST_DECL_SINGLE(SDA10, I2C10, I2C10_DESC); +MS_PIN_DECL(A12, GPIOC1, SD1CMD, SDA10); + +FUNC_GROUP_DECL(I2C10, C12, A12); + +#define B12 18 +#define I2C11_DESC SIG_DESC_SET(SCU90, 24) +SIG_EXPR_LIST_DECL_SINGLE(SD1DAT0, SD1, SD1_DESC); +SIG_EXPR_LIST_DECL_SINGLE(SCL11, I2C11, I2C11_DESC); +MS_PIN_DECL(B12, GPIOC2, SD1DAT0, SCL11); + +#define D9 19 +SIG_EXPR_LIST_DECL_SINGLE(SD1DAT1, SD1, SD1_DESC); +SIG_EXPR_LIST_DECL_SINGLE(SDA11, I2C11, I2C11_DESC); +MS_PIN_DECL(D9, GPIOC3, SD1DAT1, SDA11); + +FUNC_GROUP_DECL(I2C11, B12, D9); + +#define D10 20 +#define I2C12_DESC SIG_DESC_SET(SCU90, 25) +SIG_EXPR_LIST_DECL_SINGLE(SD1DAT2, SD1, SD1_DESC); +SIG_EXPR_LIST_DECL_SINGLE(SCL12, I2C12, I2C12_DESC); +MS_PIN_DECL(D10, GPIOC4, SD1DAT2, SCL12); + +#define E12 21 +SIG_EXPR_LIST_DECL_SINGLE(SD1DAT3, SD1, SD1_DESC); +SIG_EXPR_LIST_DECL_SINGLE(SDA12, I2C12, I2C12_DESC); +MS_PIN_DECL(E12, GPIOC5, SD1DAT3, SDA12); + +FUNC_GROUP_DECL(I2C12, D10, E12); + +#define C11 22 +#define I2C13_DESC SIG_DESC_SET(SCU90, 26) +SIG_EXPR_LIST_DECL_SINGLE(SD1CD, SD1, SD1_DESC); +SIG_EXPR_LIST_DECL_SINGLE(SCL13, I2C13, I2C13_DESC); +MS_PIN_DECL(C11, GPIOC6, SD1CD, SCL13); + +#define B11 23 +SIG_EXPR_LIST_DECL_SINGLE(SD1WP, SD1, SD1_DESC); +SIG_EXPR_LIST_DECL_SINGLE(SDA13, I2C13, I2C13_DESC); +MS_PIN_DECL(B11, GPIOC7, SD1WP, SDA13); + +FUNC_GROUP_DECL(I2C13, C11, B11); +FUNC_GROUP_DECL(SD1, C12, A12, B12, D9, D10, E12, C11, B11); + +#define SD2_DESC SIG_DESC_SET(SCU90, 1) +#define GPID0_DESC SIG_DESC_SET(SCU8C, 8) +#define GPID_DESC SIG_DESC_SET(HW_STRAP1, 21) + +#define F19 24 +SIG_EXPR_LIST_DECL_SINGLE(SD2CLK, SD2, SD2_DESC); +SIG_EXPR_DECL(GPID0IN, GPID0, GPID0_DESC); +SIG_EXPR_DECL(GPID0IN, GPID, GPID_DESC); +SIG_EXPR_LIST_DECL_DUAL(GPID0IN, GPID0, GPID); +MS_PIN_DECL(F19, GPIOD0, SD2CLK, GPID0IN); + +#define E21 25 +SIG_EXPR_LIST_DECL_SINGLE(SD2CMD, SD2, SD2_DESC); +SIG_EXPR_DECL(GPID0OUT, GPID0, GPID0_DESC); +SIG_EXPR_DECL(GPID0OUT, GPID, GPID_DESC); +SIG_EXPR_LIST_DECL_DUAL(GPID0OUT, GPID0, GPID); +MS_PIN_DECL(E21, GPIOD1, SD2CMD, GPID0OUT); + +FUNC_GROUP_DECL(GPID0, F19, E21); + +#define GPID2_DESC SIG_DESC_SET(SCU8C, 9) + +#define D20 26 +SIG_EXPR_LIST_DECL_SINGLE(SD2DAT0, SD2, SD2_DESC); +SIG_EXPR_DECL(GPID2IN, GPID2, GPID2_DESC); +SIG_EXPR_DECL(GPID2IN, GPID, GPID_DESC); +SIG_EXPR_LIST_DECL_DUAL(GPID2IN, GPID2, GPID); +MS_PIN_DECL(D20, GPIOD2, SD2DAT0, GPID2IN); + +#define D21 27 +SIG_EXPR_LIST_DECL_SINGLE(SD2DAT1, SD2, SD2_DESC); +SIG_EXPR_DECL(GPID2OUT, GPID2, GPID2_DESC); +SIG_EXPR_DECL(GPID2OUT, GPID, GPID_DESC); +SIG_EXPR_LIST_DECL_DUAL(GPID2OUT, GPID2, GPID); +MS_PIN_DECL(D21, GPIOD3, SD2DAT1, GPID2OUT); + +FUNC_GROUP_DECL(GPID2, D20, D21); + +#define GPIE_DESC SIG_DESC_SET(HW_STRAP1, 21) +#define GPIE0_DESC SIG_DESC_SET(SCU8C, 12) + +#define B20 32 +SIG_EXPR_LIST_DECL_SINGLE(NCTS3, NCTS3, SIG_DESC_SET(SCU80, 16)); +SIG_EXPR_DECL(GPIE0IN, GPIE0, GPIE0_DESC); +SIG_EXPR_DECL(GPIE0IN, GPIE, GPIE_DESC); +SIG_EXPR_LIST_DECL_DUAL(GPIE0IN, GPIE0, GPIE); +MS_PIN_DECL(B20, GPIOE0, NCTS3, GPIE0IN); + +#define C20 33 +SIG_EXPR_LIST_DECL_SINGLE(NDCD3, NDCD3, SIG_DESC_SET(SCU80, 17)); +SIG_EXPR_DECL(GPIE0OUT, GPIE0, GPIE0_DESC); +SIG_EXPR_DECL(GPIE0OUT, GPIE, GPIE_DESC); +SIG_EXPR_LIST_DECL_DUAL(GPIE0OUT, GPIE0, GPIE); +MS_PIN_DECL(C20, GPIE0, NDCD3, GPIE0OUT); + +FUNC_GROUP_DECL(GPIE0, B20, C20); + +#define SPI1_DESC SIG_DESC_SET(HW_STRAP1, 13) +#define C18 64 +SIG_EXPR_LIST_DECL_SINGLE(SYSCS, SPI1, COND1, SPI1_DESC); +SS_PIN_DECL(C18, GPIOI0, SYSCS); + +#define E15 65 +SIG_EXPR_LIST_DECL_SINGLE(SYSCK, SPI1, COND1, SPI1_DESC); +SS_PIN_DECL(E15, GPIOI1, SYSCK); + +#define A14 66 +SIG_EXPR_LIST_DECL_SINGLE(SYSMOSI, SPI1, COND1, SPI1_DESC); +SS_PIN_DECL(A14, GPIOI2, SYSMOSI); + +#define C16 67 +SIG_EXPR_LIST_DECL_SINGLE(SYSMISO, SPI1, COND1, SPI1_DESC); +SS_PIN_DECL(C16, GPIOI3, SYSMISO); + +FUNC_GROUP_DECL(SPI1, C18, E15, A14, C16); + +#define L2 73 +SIG_EXPR_LIST_DECL_SINGLE(SGPMLD, SGPM, SIG_DESC_SET(SCU84, 9)); +SS_PIN_DECL(L2, GPIOJ1, SGPMLD); + +#define N3 74 +SIG_EXPR_LIST_DECL_SINGLE(SGPMO, SGPM, SIG_DESC_SET(SCU84, 10)); +SS_PIN_DECL(N3, GPIOJ2, SGPMO); + +#define N4 75 +SIG_EXPR_LIST_DECL_SINGLE(SGPMI, SGPM, SIG_DESC_SET(SCU84, 11)); +SS_PIN_DECL(N4, GPIOJ3, SGPMI); + +#define I2C5_DESC SIG_DESC_SET(SCU90, 18) + +#define L3 80 +SIG_EXPR_LIST_DECL_SINGLE(SCL5, I2C5, I2C5_DESC); +SS_PIN_DECL(L3, GPIOK0, SCL5); + +#define L4 81 +SIG_EXPR_LIST_DECL_SINGLE(SDA5, I2C5, I2C5_DESC); +SS_PIN_DECL(L4, GPIOK1, SDA5); + +FUNC_GROUP_DECL(I2C5, L3, L4); + +#define I2C6_DESC SIG_DESC_SET(SCU90, 19) + +#define L1 82 +SIG_EXPR_LIST_DECL_SINGLE(SCL6, I2C6, I2C6_DESC); +SS_PIN_DECL(L1, GPIOK2, SCL6); + +#define N2 83 +SIG_EXPR_LIST_DECL_SINGLE(SDA6, I2C6, I2C6_DESC); +SS_PIN_DECL(N2, GPIOK3, SDA6); + +FUNC_GROUP_DECL(I2C6, L1, N2); + +#define I2C7_DESC SIG_DESC_SET(SCU90, 20) + +#define N1 84 +SIG_EXPR_LIST_DECL_SINGLE(SCL7, I2C7, I2C7_DESC); +SS_PIN_DECL(N1, GPIOK4, SCL7); + +#define P1 85 +SIG_EXPR_LIST_DECL_SINGLE(SDA7, I2C7, I2C7_DESC); +SS_PIN_DECL(P1, GPIOK5, SDA7); + +FUNC_GROUP_DECL(I2C7, N1, P1); + +#define I2C8_DESC SIG_DESC_SET(SCU90, 21) + +#define P2 86 +SIG_EXPR_LIST_DECL_SINGLE(SCL8, I2C8, I2C8_DESC); +SS_PIN_DECL(P2, GPIOK6, SCL8); + +#define R1 87 +SIG_EXPR_LIST_DECL_SINGLE(SDA8, I2C8, I2C8_DESC); +SS_PIN_DECL(R1, GPIOK7, SDA8); + +FUNC_GROUP_DECL(I2C8, P2, R1); + +#define VPIOFF0_DESC { SCU90, GENMASK(5, 4), 0, 0 } +#define VPIOFF1_DESC { SCU90, GENMASK(5, 4), 1, 0 } +#define VPI24_DESC { SCU90, GENMASK(5, 4), 2, 0 } +#define VPIRSVD_DESC { SCU90, GENMASK(5, 4), 3, 0 } + +#define V2 104 +#define V2_DESC SIG_DESC_SET(SCU88, 0) +SIG_EXPR_LIST_DECL_SINGLE(DASHN0, DASHN0, VPIRSVD_DESC, V2_DESC); +SIG_EXPR_LIST_DECL_SINGLE(PWM0, PWM0, V2_DESC, COND2); +MS_PIN_DECL(V2, GPION0, DASHN0, PWM0); +FUNC_GROUP_DECL(PWM0, V2); + +#define W2 105 +#define W2_DESC SIG_DESC_SET(SCU88, 1) +SIG_EXPR_LIST_DECL_SINGLE(DASHN1, DASHN1, VPIRSVD_DESC, W2_DESC); +SIG_EXPR_LIST_DECL_SINGLE(PWM1, PWM1, W2_DESC, COND2); +MS_PIN_DECL(W2, GPION1, DASHN1, PWM1); +FUNC_GROUP_DECL(PWM1, W2); + +#define V3 106 +#define V3_DESC SIG_DESC_SET(SCU88, 2) +SIG_EXPR_DECL(VPIG2, VPI24, VPI24_DESC, V3_DESC, COND2); +SIG_EXPR_DECL(VPIG2, VPIRSVD, VPIRSVD_DESC, V3_DESC, COND2); +SIG_EXPR_LIST_DECL_DUAL(VPIG2, VPI24, VPIRSVD); +SIG_EXPR_LIST_DECL_SINGLE(PWM2, PWM2, V3_DESC, COND2); +MS_PIN_DECL(V3, GPION2, VPIG2, PWM2); +FUNC_GROUP_DECL(PWM2, V3); + +#define U3 107 +#define U3_DESC SIG_DESC_SET(SCU88, 3) +SIG_EXPR_DECL(VPIG3, VPI24, VPI24_DESC, U3_DESC, COND2); +SIG_EXPR_DECL(VPIG3, VPIRSVD, VPIRSVD_DESC, U3_DESC, COND2); +SIG_EXPR_LIST_DECL_DUAL(VPIG3, VPI24, VPIRSVD); +SIG_EXPR_LIST_DECL_SINGLE(PWM3, PWM3, U3_DESC, COND2); +MS_PIN_DECL(U3, GPION3, VPIG3, PWM3); +FUNC_GROUP_DECL(PWM3, U3); + +#define W3 108 +#define W3_DESC SIG_DESC_SET(SCU88, 4) +SIG_EXPR_DECL(VPIG4, VPI24, VPI24_DESC, W3_DESC, COND2); +SIG_EXPR_DECL(VPIG4, VPIRSVD, VPIRSVD_DESC, W3_DESC, COND2); +SIG_EXPR_LIST_DECL_DUAL(VPIG4, VPI24, VPIRSVD); +SIG_EXPR_LIST_DECL_SINGLE(PWM4, PWM4, W3_DESC, COND2); +MS_PIN_DECL(W3, GPION4, VPIG4, PWM4); +FUNC_GROUP_DECL(PWM4, W3); + +#define AA3 109 +#define AA3_DESC SIG_DESC_SET(SCU88, 5) +SIG_EXPR_DECL(VPIG5, VPI24, VPI24_DESC, AA3_DESC, COND2); +SIG_EXPR_DECL(VPIG5, VPIRSVD, VPIRSVD_DESC, AA3_DESC, COND2); +SIG_EXPR_LIST_DECL_DUAL(VPIG5, VPI24, VPIRSVD); +SIG_EXPR_LIST_DECL_SINGLE(PWM5, PWM5, AA3_DESC, COND2); +MS_PIN_DECL(AA3, GPION5, VPIG5, PWM5); +FUNC_GROUP_DECL(PWM5, AA3); + +#define Y3 110 +#define Y3_DESC SIG_DESC_SET(SCU88, 6) +SIG_EXPR_LIST_DECL_SINGLE(VPIG6, VPI24, VPI24_DESC, Y3_DESC); +SIG_EXPR_LIST_DECL_SINGLE(PWM6, PWM6, Y3_DESC, COND2); +MS_PIN_DECL(Y3, GPION6, VPIG6, PWM6); +FUNC_GROUP_DECL(PWM6, Y3); + +#define T4 111 +#define T4_DESC SIG_DESC_SET(SCU88, 7) +SIG_EXPR_LIST_DECL_SINGLE(VPIG7, VPI24, VPI24_DESC, T4_DESC); +SIG_EXPR_LIST_DECL_SINGLE(PWM7, PWM7, T4_DESC, COND2); +MS_PIN_DECL(T4, GPION7, VPIG7, PWM7); +FUNC_GROUP_DECL(PWM7, T4); + +#define V6 127 +SIG_EXPR_LIST_DECL_SINGLE(DASHV6, DASHV6, SIG_DESC_SET(SCU90, 28), + SIG_DESC_SET(SCU88, 23)); +SS_PIN_DECL(V6, GPIOP7, DASHV6); + +#define I2C3_DESC SIG_DESC_SET(SCU90, 16) + +#define A11 128 +SIG_EXPR_LIST_DECL_SINGLE(SCL3, I2C3, I2C3_DESC); +SS_PIN_DECL(A11, GPIOQ0, SCL3); + +#define A10 129 +SIG_EXPR_LIST_DECL_SINGLE(SDA3, I2C3, I2C3_DESC); +SS_PIN_DECL(A10, GPIOQ1, SDA3); + +FUNC_GROUP_DECL(I2C3, A11, A10); + +#define I2C4_DESC SIG_DESC_SET(SCU90, 17) + +#define A9 130 +SIG_EXPR_LIST_DECL_SINGLE(SCL4, I2C4, I2C4_DESC); +SS_PIN_DECL(A9, GPIOQ2, SCL4); + +#define B9 131 +SIG_EXPR_LIST_DECL_SINGLE(SDA4, I2C4, I2C4_DESC); +SS_PIN_DECL(B9, GPIOQ3, SDA4); + +FUNC_GROUP_DECL(I2C4, A9, B9); + +#define I2C14_DESC SIG_DESC_SET(SCU90, 27) + +#define N21 132 +SIG_EXPR_LIST_DECL_SINGLE(SCL14, I2C14, I2C14_DESC); +SS_PIN_DECL(N21, GPIOQ4, SCL14); + +#define N22 133 +SIG_EXPR_LIST_DECL_SINGLE(SDA14, I2C14, I2C14_DESC); +SS_PIN_DECL(N22, GPIOQ5, SDA14); + +FUNC_GROUP_DECL(I2C14, N21, N22); + +#define B10 134 +SSSF_PIN_DECL(B10, GPIOQ6, OSCCLK, SIG_DESC_SET(SCU2C, 1)); + +#define N20 135 +SSSF_PIN_DECL(N20, GPIOQ7, PEWAKE, SIG_DESC_SET(SCU2C, 29)); + +#define D8 142 +SIG_EXPR_LIST_DECL_SINGLE(MDC1, MDIO1, SIG_DESC_SET(SCU88, 30)); +SS_PIN_DECL(D8, GPIOR6, MDC1); + +#define E10 143 +SIG_EXPR_LIST_DECL_SINGLE(MDIO1, MDIO1, SIG_DESC_SET(SCU88, 31)); +SS_PIN_DECL(E10, GPIOR7, MDIO1); + +FUNC_GROUP_DECL(MDIO1, D8, E10); + +/* RGMII1/RMII1 */ + +#define RMII1_DESC SIG_DESC_BIT(HW_STRAP1, 6, 0) +#define RMII2_DESC SIG_DESC_BIT(HW_STRAP1, 7, 0) + +#define B5 152 +SIG_EXPR_LIST_DECL_SINGLE(GPIOT0, GPIOT0, SIG_DESC_SET(SCUA0, 0)); +SIG_EXPR_LIST_DECL_SINGLE(RMII1RCLKO, RMII1, RMII1_DESC, + SIG_DESC_SET(SCU48, 29)); +SIG_EXPR_LIST_DECL_SINGLE(RGMII1TXCK, RGMII1); +MS_PIN_DECL_(B5, SIG_EXPR_LIST_PTR(GPIOT0), SIG_EXPR_LIST_PTR(RMII1RCLKO), + SIG_EXPR_LIST_PTR(RGMII1TXCK)); + +#define E9 153 +SIG_EXPR_LIST_DECL_SINGLE(GPIOT1, GPIOT1, SIG_DESC_SET(SCUA0, 1)); +SIG_EXPR_LIST_DECL_SINGLE(RMII1TXEN, RMII1, RMII1_DESC); +SIG_EXPR_LIST_DECL_SINGLE(RGMII1TXCTL, RGMII1); +MS_PIN_DECL_(E9, SIG_EXPR_LIST_PTR(GPIOT1), SIG_EXPR_LIST_PTR(RMII1TXEN), + SIG_EXPR_LIST_PTR(RGMII1TXCTL)); + +#define F9 154 +SIG_EXPR_LIST_DECL_SINGLE(GPIOT2, GPIOT2, SIG_DESC_SET(SCUA0, 2)); +SIG_EXPR_LIST_DECL_SINGLE(RMII1TXD0, RMII1, RMII1_DESC); +SIG_EXPR_LIST_DECL_SINGLE(RGMII1TXD0, RGMII1); +MS_PIN_DECL_(F9, SIG_EXPR_LIST_PTR(GPIOT2), SIG_EXPR_LIST_PTR(RMII1TXD0), + SIG_EXPR_LIST_PTR(RGMII1TXD0)); + +#define A5 155 +SIG_EXPR_LIST_DECL_SINGLE(GPIOT3, GPIOT3, SIG_DESC_SET(SCUA0, 3)); +SIG_EXPR_LIST_DECL_SINGLE(RMII1TXD1, RMII1, RMII1_DESC); +SIG_EXPR_LIST_DECL_SINGLE(RGMII1TXD1, RGMII1); +MS_PIN_DECL_(A5, SIG_EXPR_LIST_PTR(GPIOT3), SIG_EXPR_LIST_PTR(RMII1TXD1), + SIG_EXPR_LIST_PTR(RGMII1TXD1)); + +#define E7 156 +SIG_EXPR_LIST_DECL_SINGLE(GPIOT4, GPIOT4, SIG_DESC_SET(SCUA0, 4)); +SIG_EXPR_LIST_DECL_SINGLE(RMII1DASH0, RMII1, RMII1_DESC); +SIG_EXPR_LIST_DECL_SINGLE(RGMII1TXD2, RGMII1); +MS_PIN_DECL_(E7, SIG_EXPR_LIST_PTR(GPIOT4), SIG_EXPR_LIST_PTR(RMII1DASH0), + SIG_EXPR_LIST_PTR(RGMII1TXD2)); + +#define D7 157 +SIG_EXPR_LIST_DECL_SINGLE(GPIOT5, GPIOT5, SIG_DESC_SET(SCUA0, 5)); +SIG_EXPR_LIST_DECL_SINGLE(RMII1DASH1, RMII1, RMII1_DESC); +SIG_EXPR_LIST_DECL_SINGLE(RGMII1TXD3, RGMII1); +MS_PIN_DECL_(D7, SIG_EXPR_LIST_PTR(GPIOT5), SIG_EXPR_LIST_PTR(RMII1DASH1), + SIG_EXPR_LIST_PTR(RGMII1TXD3)); + +#define B2 158 +SIG_EXPR_LIST_DECL_SINGLE(GPIOT6, GPIOT6, SIG_DESC_SET(SCUA0, 6)); +SIG_EXPR_LIST_DECL_SINGLE(RMII2RCLKO, RMII2, RMII2_DESC, + SIG_DESC_SET(SCU48, 30)); +SIG_EXPR_LIST_DECL_SINGLE(RGMII2TXCK, RGMII2); +MS_PIN_DECL_(B2, SIG_EXPR_LIST_PTR(GPIOT6), SIG_EXPR_LIST_PTR(RMII2RCLKO), + SIG_EXPR_LIST_PTR(RGMII2TXCK)); + +#define B1 159 +SIG_EXPR_LIST_DECL_SINGLE(GPIOT7, GPIOT7, SIG_DESC_SET(SCUA0, 7)); +SIG_EXPR_LIST_DECL_SINGLE(RMII2TXEN, RMII2, RMII2_DESC); +SIG_EXPR_LIST_DECL_SINGLE(RGMII2TXCTL, RGMII2); +MS_PIN_DECL_(B1, SIG_EXPR_LIST_PTR(GPIOT7), SIG_EXPR_LIST_PTR(RMII2TXEN), + SIG_EXPR_LIST_PTR(RGMII2TXCTL)); + +#define A2 160 +SIG_EXPR_LIST_DECL_SINGLE(GPIOU0, GPIOU0, SIG_DESC_SET(SCUA0, 8)); +SIG_EXPR_LIST_DECL_SINGLE(RMII2TXD0, RMII2, RMII2_DESC); +SIG_EXPR_LIST_DECL_SINGLE(RGMII2TXD0, RGMII2); +MS_PIN_DECL_(A2, SIG_EXPR_LIST_PTR(GPIOU0), SIG_EXPR_LIST_PTR(RMII2TXD0), + SIG_EXPR_LIST_PTR(RGMII2TXD0)); + +#define B3 161 +SIG_EXPR_LIST_DECL_SINGLE(GPIOU1, GPIOU1, SIG_DESC_SET(SCUA0, 9)); +SIG_EXPR_LIST_DECL_SINGLE(RMII2TXD1, RMII2, RMII2_DESC); +SIG_EXPR_LIST_DECL_SINGLE(RGMII2TXD1, RGMII2); +MS_PIN_DECL_(B3, SIG_EXPR_LIST_PTR(GPIOU1), SIG_EXPR_LIST_PTR(RMII2TXD1), + SIG_EXPR_LIST_PTR(RGMII2TXD1)); + +#define D5 162 +SIG_EXPR_LIST_DECL_SINGLE(GPIOU2, GPIOU2, SIG_DESC_SET(SCUA0, 10)); +SIG_EXPR_LIST_DECL_SINGLE(RMII2DASH0, RMII2, RMII2_DESC); +SIG_EXPR_LIST_DECL_SINGLE(RGMII2TXD2, RGMII2); +MS_PIN_DECL_(D5, SIG_EXPR_LIST_PTR(GPIOU2), SIG_EXPR_LIST_PTR(RMII2DASH0), + SIG_EXPR_LIST_PTR(RGMII2TXD2)); + +#define D4 163 +SIG_EXPR_LIST_DECL_SINGLE(GPIOU3, GPIOU3, SIG_DESC_SET(SCUA0, 11)); +SIG_EXPR_LIST_DECL_SINGLE(RMII2DASH1, RMII2, RMII2_DESC); +SIG_EXPR_LIST_DECL_SINGLE(RGMII2TXD3, RGMII2); +MS_PIN_DECL_(D4, SIG_EXPR_LIST_PTR(GPIOU3), SIG_EXPR_LIST_PTR(RMII2DASH1), + SIG_EXPR_LIST_PTR(RGMII2TXD3)); + +#define B4 164 +SIG_EXPR_LIST_DECL_SINGLE(GPIOU4, GPIOU4, SIG_DESC_SET(SCUA0, 12)); +SIG_EXPR_LIST_DECL_SINGLE(RMII1RCLKI, RMII1, RMII1_DESC); +SIG_EXPR_LIST_DECL_SINGLE(RGMII1RXCK, RGMII1); +MS_PIN_DECL_(B4, SIG_EXPR_LIST_PTR(GPIOU4), SIG_EXPR_LIST_PTR(RMII1RCLKI), + SIG_EXPR_LIST_PTR(RGMII1RXCK)); + +#define A4 165 +SIG_EXPR_LIST_DECL_SINGLE(GPIOU5, GPIOU5, SIG_DESC_SET(SCUA0, 13)); +SIG_EXPR_LIST_DECL_SINGLE(RMII1DASH2, RMII1, RMII1_DESC); +SIG_EXPR_LIST_DECL_SINGLE(RGMII1RXCTL, RGMII1); +MS_PIN_DECL_(A4, SIG_EXPR_LIST_PTR(GPIOU5), SIG_EXPR_LIST_PTR(RMII1DASH2), + SIG_EXPR_LIST_PTR(RGMII1RXCTL)); + +#define A3 166 +SIG_EXPR_LIST_DECL_SINGLE(GPIOU6, GPIOU6, SIG_DESC_SET(SCUA0, 14)); +SIG_EXPR_LIST_DECL_SINGLE(RMII1RXD0, RMII1, RMII1_DESC); +SIG_EXPR_LIST_DECL_SINGLE(RGMII1RXD0, RGMII1); +MS_PIN_DECL_(A3, SIG_EXPR_LIST_PTR(GPIOU6), SIG_EXPR_LIST_PTR(RMII1RXD0), + SIG_EXPR_LIST_PTR(RGMII1RXD0)); + +#define D6 167 +SIG_EXPR_LIST_DECL_SINGLE(GPIOU7, GPIOU7, SIG_DESC_SET(SCUA0, 15)); +SIG_EXPR_LIST_DECL_SINGLE(RMII1RXD1, RMII1, RMII1_DESC); +SIG_EXPR_LIST_DECL_SINGLE(RGMII1RXD1, RGMII1); +MS_PIN_DECL_(D6, SIG_EXPR_LIST_PTR(GPIOU7), SIG_EXPR_LIST_PTR(RMII1RXD1), + SIG_EXPR_LIST_PTR(RGMII1RXD1)); + +#define C5 168 +SIG_EXPR_LIST_DECL_SINGLE(GPIOV0, GPIOV0, SIG_DESC_SET(SCUA0, 16)); +SIG_EXPR_LIST_DECL_SINGLE(RMII1CRSDV, RMII1, RMII1_DESC); +SIG_EXPR_LIST_DECL_SINGLE(RGMII1RXD2, RGMII1); +MS_PIN_DECL_(C5, SIG_EXPR_LIST_PTR(GPIOV0), SIG_EXPR_LIST_PTR(RMII1CRSDV), + SIG_EXPR_LIST_PTR(RGMII1RXD2)); + +#define C4 169 +SIG_EXPR_LIST_DECL_SINGLE(GPIOV1, GPIOV1, SIG_DESC_SET(SCUA0, 17)); +SIG_EXPR_LIST_DECL_SINGLE(RMII1RXER, RMII1, RMII1_DESC); +SIG_EXPR_LIST_DECL_SINGLE(RGMII1RXD3, RGMII1); +MS_PIN_DECL_(C4, SIG_EXPR_LIST_PTR(GPIOV1), SIG_EXPR_LIST_PTR(RMII1RXER), + SIG_EXPR_LIST_PTR(RGMII1RXD3)); + +FUNC_GROUP_DECL(RGMII1, B4, A4, A3, D6, C5, C4, B5, E9, F9, A5, E7, D7); +FUNC_GROUP_DECL(RMII1, B4, A3, D6, C5, C4, B5, E9, F9, A5); + +#define C2 170 +SIG_EXPR_LIST_DECL_SINGLE(GPIOV2, GPIOV2, SIG_DESC_SET(SCUA0, 18)); +SIG_EXPR_LIST_DECL_SINGLE(RMII2RCLKI, RMII2, RMII2_DESC); +SIG_EXPR_LIST_DECL_SINGLE(RGMII2RXCK, RGMII2); +MS_PIN_DECL_(C2, SIG_EXPR_LIST_PTR(GPIOV2), SIG_EXPR_LIST_PTR(RMII2RCLKI), + SIG_EXPR_LIST_PTR(RGMII2RXCK)); + +#define C1 171 +SIG_EXPR_LIST_DECL_SINGLE(GPIOV3, GPIOV3, SIG_DESC_SET(SCUA0, 19)); +SIG_EXPR_LIST_DECL_SINGLE(RMII2DASH2, RMII2, RMII2_DESC); +SIG_EXPR_LIST_DECL_SINGLE(RGMII2RXCTL, RGMII2); +MS_PIN_DECL_(C1, SIG_EXPR_LIST_PTR(GPIOV3), SIG_EXPR_LIST_PTR(RMII2DASH2), + SIG_EXPR_LIST_PTR(RGMII2RXCTL)); + +#define C3 172 +SIG_EXPR_LIST_DECL_SINGLE(GPIOV4, GPIOV4, SIG_DESC_SET(SCUA0, 20)); +SIG_EXPR_LIST_DECL_SINGLE(RMII2RXD0, RMII2, RMII2_DESC); +SIG_EXPR_LIST_DECL_SINGLE(RGMII2RXD0, RGMII2); +MS_PIN_DECL_(C3, SIG_EXPR_LIST_PTR(GPIOV4), SIG_EXPR_LIST_PTR(RMII2RXD0), + SIG_EXPR_LIST_PTR(RGMII2RXD0)); + +#define D1 173 +SIG_EXPR_LIST_DECL_SINGLE(GPIOV5, GPIOV5, SIG_DESC_SET(SCUA0, 21)); +SIG_EXPR_LIST_DECL_SINGLE(RMII2RXD1, RMII2, RMII2_DESC); +SIG_EXPR_LIST_DECL_SINGLE(RGMII2RXD1, RGMII2); +MS_PIN_DECL_(D1, SIG_EXPR_LIST_PTR(GPIOV5), SIG_EXPR_LIST_PTR(RMII2RXD1), + SIG_EXPR_LIST_PTR(RGMII2RXD1)); + +#define D2 174 +SIG_EXPR_LIST_DECL_SINGLE(GPIOV6, GPIOV6, SIG_DESC_SET(SCUA0, 22)); +SIG_EXPR_LIST_DECL_SINGLE(RMII2CRSDV, RMII2, RMII2_DESC); +SIG_EXPR_LIST_DECL_SINGLE(RGMII2RXD2, RGMII2); +MS_PIN_DECL_(D2, SIG_EXPR_LIST_PTR(GPIOV6), SIG_EXPR_LIST_PTR(RMII2CRSDV), + SIG_EXPR_LIST_PTR(RGMII2RXD2)); + +#define E6 175 +SIG_EXPR_LIST_DECL_SINGLE(GPIOV7, GPIOV7, SIG_DESC_SET(SCUA0, 23)); +SIG_EXPR_LIST_DECL_SINGLE(RMII2RXER, RMII2, RMII2_DESC); +SIG_EXPR_LIST_DECL_SINGLE(RGMII2RXD3, RGMII2); +MS_PIN_DECL_(E6, SIG_EXPR_LIST_PTR(GPIOV7), SIG_EXPR_LIST_PTR(RMII2RXER), + SIG_EXPR_LIST_PTR(RGMII2RXD3)); + +FUNC_GROUP_DECL(RGMII2, B2, B1, A2, B3, D5, D4, C2, C1, C3, D1, D2, E6); +FUNC_GROUP_DECL(RMII2, B2, B1, A2, B3, C2, C3, D1, D2, E6); + +/* Pins, groups and functions are sort(1):ed alphabetically for sanity */ + +static struct pinctrl_pin_desc aspeed_g5_pins[ASPEED_G5_NR_PINS] = { + ASPEED_PINCTRL_PIN(A10), + ASPEED_PINCTRL_PIN(A11), + ASPEED_PINCTRL_PIN(A12), + ASPEED_PINCTRL_PIN(A13), + ASPEED_PINCTRL_PIN(A14), + ASPEED_PINCTRL_PIN(A2), + ASPEED_PINCTRL_PIN(A3), + ASPEED_PINCTRL_PIN(A4), + ASPEED_PINCTRL_PIN(A5), + ASPEED_PINCTRL_PIN(A9), + ASPEED_PINCTRL_PIN(AA3), + ASPEED_PINCTRL_PIN(B1), + ASPEED_PINCTRL_PIN(B10), + ASPEED_PINCTRL_PIN(B11), + ASPEED_PINCTRL_PIN(B12), + ASPEED_PINCTRL_PIN(B13), + ASPEED_PINCTRL_PIN(B14), + ASPEED_PINCTRL_PIN(B2), + ASPEED_PINCTRL_PIN(B20), + ASPEED_PINCTRL_PIN(B3), + ASPEED_PINCTRL_PIN(B4), + ASPEED_PINCTRL_PIN(B5), + ASPEED_PINCTRL_PIN(B9), + ASPEED_PINCTRL_PIN(C1), + ASPEED_PINCTRL_PIN(C11), + ASPEED_PINCTRL_PIN(C12), + ASPEED_PINCTRL_PIN(C13), + ASPEED_PINCTRL_PIN(C14), + ASPEED_PINCTRL_PIN(C16), + ASPEED_PINCTRL_PIN(C18), + ASPEED_PINCTRL_PIN(C2), + ASPEED_PINCTRL_PIN(C20), + ASPEED_PINCTRL_PIN(C3), + ASPEED_PINCTRL_PIN(C4), + ASPEED_PINCTRL_PIN(C5), + ASPEED_PINCTRL_PIN(D1), + ASPEED_PINCTRL_PIN(D10), + ASPEED_PINCTRL_PIN(D2), + ASPEED_PINCTRL_PIN(D20), + ASPEED_PINCTRL_PIN(D21), + ASPEED_PINCTRL_PIN(D4), + ASPEED_PINCTRL_PIN(D5), + ASPEED_PINCTRL_PIN(D6), + ASPEED_PINCTRL_PIN(D7), + ASPEED_PINCTRL_PIN(D8), + ASPEED_PINCTRL_PIN(D9), + ASPEED_PINCTRL_PIN(E10), + ASPEED_PINCTRL_PIN(E12), + ASPEED_PINCTRL_PIN(E13), + ASPEED_PINCTRL_PIN(E15), + ASPEED_PINCTRL_PIN(E21), + ASPEED_PINCTRL_PIN(E6), + ASPEED_PINCTRL_PIN(E7), + ASPEED_PINCTRL_PIN(E9), + ASPEED_PINCTRL_PIN(F19), + ASPEED_PINCTRL_PIN(F9), + ASPEED_PINCTRL_PIN(H20), + ASPEED_PINCTRL_PIN(L1), + ASPEED_PINCTRL_PIN(L2), + ASPEED_PINCTRL_PIN(L3), + ASPEED_PINCTRL_PIN(L4), + ASPEED_PINCTRL_PIN(N1), + ASPEED_PINCTRL_PIN(N2), + ASPEED_PINCTRL_PIN(N20), + ASPEED_PINCTRL_PIN(N21), + ASPEED_PINCTRL_PIN(N22), + ASPEED_PINCTRL_PIN(N3), + ASPEED_PINCTRL_PIN(N4), + ASPEED_PINCTRL_PIN(P1), + ASPEED_PINCTRL_PIN(P2), + ASPEED_PINCTRL_PIN(R1), + ASPEED_PINCTRL_PIN(T4), + ASPEED_PINCTRL_PIN(U3), + ASPEED_PINCTRL_PIN(V2), + ASPEED_PINCTRL_PIN(V3), + ASPEED_PINCTRL_PIN(V6), + ASPEED_PINCTRL_PIN(W2), + ASPEED_PINCTRL_PIN(W3), + ASPEED_PINCTRL_PIN(Y3), +}; + +static const struct aspeed_pin_group aspeed_g5_groups[] = { + ASPEED_PINCTRL_GROUP(GPID0), + ASPEED_PINCTRL_GROUP(GPID2), + ASPEED_PINCTRL_GROUP(GPIE0), + ASPEED_PINCTRL_GROUP(I2C10), + ASPEED_PINCTRL_GROUP(I2C11), + ASPEED_PINCTRL_GROUP(I2C12), + ASPEED_PINCTRL_GROUP(I2C13), + ASPEED_PINCTRL_GROUP(I2C14), + ASPEED_PINCTRL_GROUP(I2C3), + ASPEED_PINCTRL_GROUP(I2C4), + ASPEED_PINCTRL_GROUP(I2C5), + ASPEED_PINCTRL_GROUP(I2C6), + ASPEED_PINCTRL_GROUP(I2C7), + ASPEED_PINCTRL_GROUP(I2C8), + ASPEED_PINCTRL_GROUP(I2C9), + ASPEED_PINCTRL_GROUP(MAC1LINK), + ASPEED_PINCTRL_GROUP(MDIO1), + ASPEED_PINCTRL_GROUP(MDIO2), + ASPEED_PINCTRL_GROUP(OSCCLK), + ASPEED_PINCTRL_GROUP(PEWAKE), + ASPEED_PINCTRL_GROUP(PWM0), + ASPEED_PINCTRL_GROUP(PWM1), + ASPEED_PINCTRL_GROUP(PWM2), + ASPEED_PINCTRL_GROUP(PWM3), + ASPEED_PINCTRL_GROUP(PWM4), + ASPEED_PINCTRL_GROUP(PWM5), + ASPEED_PINCTRL_GROUP(PWM6), + ASPEED_PINCTRL_GROUP(PWM7), + ASPEED_PINCTRL_GROUP(RGMII1), + ASPEED_PINCTRL_GROUP(RGMII2), + ASPEED_PINCTRL_GROUP(RMII1), + ASPEED_PINCTRL_GROUP(RMII2), + ASPEED_PINCTRL_GROUP(SD1), + ASPEED_PINCTRL_GROUP(SPI1), + ASPEED_PINCTRL_GROUP(TIMER4), + ASPEED_PINCTRL_GROUP(TIMER5), + ASPEED_PINCTRL_GROUP(TIMER6), + ASPEED_PINCTRL_GROUP(TIMER7), + ASPEED_PINCTRL_GROUP(TIMER8), +}; + +static const struct aspeed_pin_function aspeed_g5_functions[] = { + ASPEED_PINCTRL_FUNC(GPID0), + ASPEED_PINCTRL_FUNC(GPID2), + ASPEED_PINCTRL_FUNC(GPIE0), + ASPEED_PINCTRL_FUNC(I2C10), + ASPEED_PINCTRL_FUNC(I2C11), + ASPEED_PINCTRL_FUNC(I2C12), + ASPEED_PINCTRL_FUNC(I2C13), + ASPEED_PINCTRL_FUNC(I2C14), + ASPEED_PINCTRL_FUNC(I2C3), + ASPEED_PINCTRL_FUNC(I2C4), + ASPEED_PINCTRL_FUNC(I2C5), + ASPEED_PINCTRL_FUNC(I2C6), + ASPEED_PINCTRL_FUNC(I2C7), + ASPEED_PINCTRL_FUNC(I2C8), + ASPEED_PINCTRL_FUNC(I2C9), + ASPEED_PINCTRL_FUNC(MAC1LINK), + ASPEED_PINCTRL_FUNC(MDIO1), + ASPEED_PINCTRL_FUNC(MDIO2), + ASPEED_PINCTRL_FUNC(OSCCLK), + ASPEED_PINCTRL_FUNC(PEWAKE), + ASPEED_PINCTRL_FUNC(PWM0), + ASPEED_PINCTRL_FUNC(PWM1), + ASPEED_PINCTRL_FUNC(PWM2), + ASPEED_PINCTRL_FUNC(PWM3), + ASPEED_PINCTRL_FUNC(PWM4), + ASPEED_PINCTRL_FUNC(PWM5), + ASPEED_PINCTRL_FUNC(PWM6), + ASPEED_PINCTRL_FUNC(PWM7), + ASPEED_PINCTRL_FUNC(RGMII1), + ASPEED_PINCTRL_FUNC(RGMII2), + ASPEED_PINCTRL_FUNC(RMII1), + ASPEED_PINCTRL_FUNC(RMII2), + ASPEED_PINCTRL_FUNC(SD1), + ASPEED_PINCTRL_FUNC(SPI1), + ASPEED_PINCTRL_FUNC(TIMER4), + ASPEED_PINCTRL_FUNC(TIMER5), + ASPEED_PINCTRL_FUNC(TIMER6), + ASPEED_PINCTRL_FUNC(TIMER7), + ASPEED_PINCTRL_FUNC(TIMER8), +}; + +static struct aspeed_pinctrl_data aspeed_g5_pinctrl_data = { + .pins = aspeed_g5_pins, + .npins = ARRAY_SIZE(aspeed_g5_pins), + .groups = aspeed_g5_groups, + .ngroups = ARRAY_SIZE(aspeed_g5_groups), + .functions = aspeed_g5_functions, + .nfunctions = ARRAY_SIZE(aspeed_g5_functions), +}; + +static struct pinmux_ops aspeed_g5_pinmux_ops = { + .get_functions_count = aspeed_pinmux_get_fn_count, + .get_function_name = aspeed_pinmux_get_fn_name, + .get_function_groups = aspeed_pinmux_get_fn_groups, + .set_mux = aspeed_pinmux_set_mux, + .gpio_request_enable = aspeed_gpio_request_enable, + .strict = true, +}; + +static struct pinctrl_ops aspeed_g5_pinctrl_ops = { + .get_groups_count = aspeed_pinctrl_get_groups_count, + .get_group_name = aspeed_pinctrl_get_group_name, + .get_group_pins = aspeed_pinctrl_get_group_pins, + .pin_dbg_show = aspeed_pinctrl_pin_dbg_show, + .dt_node_to_map = pinconf_generic_dt_node_to_map_pin, + .dt_free_map = pinctrl_utils_free_map, +}; + +static struct pinctrl_desc aspeed_g5_pinctrl_desc = { + .name = "aspeed-g5-pinctrl", + .pins = aspeed_g5_pins, + .npins = ARRAY_SIZE(aspeed_g5_pins), + .pctlops = &aspeed_g5_pinctrl_ops, + .pmxops = &aspeed_g5_pinmux_ops, +}; + +static int aspeed_g5_pinctrl_probe(struct platform_device *pdev) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(aspeed_g5_pins); i++) + aspeed_g5_pins[i].number = i; + + return aspeed_pinctrl_probe(pdev, &aspeed_g5_pinctrl_desc, + &aspeed_g5_pinctrl_data); +} + +static const struct of_device_id aspeed_g5_pinctrl_of_match[] = { + { .compatible = "aspeed,ast2500-pinctrl", }, + { .compatible = "aspeed,g5-pinctrl", }, + { }, +}; + +static struct platform_driver aspeed_g5_pinctrl_driver = { + .probe = aspeed_g5_pinctrl_probe, + .driver = { + .name = "aspeed-g5-pinctrl", + .of_match_table = aspeed_g5_pinctrl_of_match, + }, +}; + +static int aspeed_g5_pinctrl_init(void) +{ + return platform_driver_register(&aspeed_g5_pinctrl_driver); +} + +arch_initcall(aspeed_g5_pinctrl_init); -- cgit 1.4.1 From ac91ab51e4f882db65449ff821a5664bad4b164c Mon Sep 17 00:00:00 2001 From: Mylène Josserand Date: Wed, 7 Sep 2016 16:53:57 +0200 Subject: pinctrl: sunxi: Add GR8 controller support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Just like the other member of the sunxi family, let's add a pinctrl table for the muxing options. Signed-off-by: Mylène Josserand Signed-off-by: Maxime Ripard Acked-by: Chen-Yu Tsai Signed-off-by: Linus Walleij --- .../bindings/pinctrl/allwinner,sunxi-pinctrl.txt | 1 + drivers/pinctrl/sunxi/Kconfig | 4 + drivers/pinctrl/sunxi/Makefile | 1 + drivers/pinctrl/sunxi/pinctrl-gr8.c | 541 +++++++++++++++++++++ 4 files changed, 547 insertions(+) create mode 100644 drivers/pinctrl/sunxi/pinctrl-gr8.c diff --git a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt index 69617220c5d6..1685821eea41 100644 --- a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt @@ -23,6 +23,7 @@ Required properties: "allwinner,sun8i-h3-pinctrl" "allwinner,sun8i-h3-r-pinctrl" "allwinner,sun50i-a64-pinctrl" + "nextthing,gr8-pinctrl" - reg: Should contain the register physical address and length for the pin controller. diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig index aaf075b972f5..bff1ffc6f01e 100644 --- a/drivers/pinctrl/sunxi/Kconfig +++ b/drivers/pinctrl/sunxi/Kconfig @@ -17,6 +17,10 @@ config PINCTRL_SUN5I_A13 def_bool MACH_SUN5I select PINCTRL_SUNXI +config PINCTRL_GR8 + def_bool MACH_SUN5I + select PINCTRL_SUNXI_COMMON + config PINCTRL_SUN6I_A31 def_bool MACH_SUN6I select PINCTRL_SUNXI diff --git a/drivers/pinctrl/sunxi/Makefile b/drivers/pinctrl/sunxi/Makefile index 2d8b64e222e0..95f93d0561fc 100644 --- a/drivers/pinctrl/sunxi/Makefile +++ b/drivers/pinctrl/sunxi/Makefile @@ -5,6 +5,7 @@ obj-y += pinctrl-sunxi.o obj-$(CONFIG_PINCTRL_SUN4I_A10) += pinctrl-sun4i-a10.o obj-$(CONFIG_PINCTRL_SUN5I_A10S) += pinctrl-sun5i-a10s.o obj-$(CONFIG_PINCTRL_SUN5I_A13) += pinctrl-sun5i-a13.o +obj-$(CONFIG_PINCTRL_GR8) += pinctrl-gr8.o obj-$(CONFIG_PINCTRL_SUN6I_A31) += pinctrl-sun6i-a31.o obj-$(CONFIG_PINCTRL_SUN6I_A31S) += pinctrl-sun6i-a31s.o obj-$(CONFIG_PINCTRL_SUN6I_A31_R) += pinctrl-sun6i-a31-r.o diff --git a/drivers/pinctrl/sunxi/pinctrl-gr8.c b/drivers/pinctrl/sunxi/pinctrl-gr8.c new file mode 100644 index 000000000000..2904d2b7378b --- /dev/null +++ b/drivers/pinctrl/sunxi/pinctrl-gr8.c @@ -0,0 +1,541 @@ +/* + * NextThing GR8 SoCs pinctrl driver. + * + * Copyright (C) 2016 Mylene Josserand + * + * Based on pinctrl-sun5i-a13.c + * + * Mylene Josserand + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include +#include +#include +#include +#include + +#include "pinctrl-sunxi.h" + +static const struct sunxi_desc_pin sun5i_gr8_pins[] = { + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2c0")), /* SCK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2c0")), /* SDA */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "pwm0"), + SUNXI_FUNCTION(0x3, "spdif"), /* DO */ + SUNXI_FUNCTION_IRQ(0x6, 16)), /* EINT16 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "ir0"), /* TX */ + SUNXI_FUNCTION_IRQ(0x6, 17)), /* EINT17 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 4), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "ir0"), /* RX */ + SUNXI_FUNCTION_IRQ(0x6, 18)), /* EINT18 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 5), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2s0"), /* MCLK */ + SUNXI_FUNCTION_IRQ(0x6, 19)), /* EINT19 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 6), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2s0"), /* BCLK */ + SUNXI_FUNCTION_IRQ(0x6, 20)), /* EINT20 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 7), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2s0"), /* LRCK */ + SUNXI_FUNCTION_IRQ(0x6, 21)), /* EINT21 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 8), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2s0"), /* DO */ + SUNXI_FUNCTION_IRQ(0x6, 22)), /* EINT22 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 9), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2s0"), /* DI */ + SUNXI_FUNCTION(0x3, "spdif"), /* DI */ + SUNXI_FUNCTION_IRQ(0x6, 23)), /* EINT23 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 10), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi2"), /* CS1 */ + SUNXI_FUNCTION(0x3, "spdif"), /* DO */ + SUNXI_FUNCTION_IRQ(0x6, 24)), /* EINT24 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 11), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi2"), /* CS0 */ + SUNXI_FUNCTION(0x3, "jtag"), /* MS0 */ + SUNXI_FUNCTION_IRQ(0x6, 25)), /* EINT25 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 12), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi2"), /* CLK */ + SUNXI_FUNCTION(0x3, "jtag"), /* CK0 */ + SUNXI_FUNCTION_IRQ(0x6, 26)), /* EINT26 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 13), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi2"), /* MOSI */ + SUNXI_FUNCTION(0x3, "jtag"), /* DO0 */ + SUNXI_FUNCTION_IRQ(0x6, 27)), /* EINT27 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 14), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi2"), /* MISO */ + SUNXI_FUNCTION(0x3, "jtag"), /* DI0 */ + SUNXI_FUNCTION_IRQ(0x6, 28)), /* EINT28 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 15), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2c1")), /* SCK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 16), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2c1")), /* SDA */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 17), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2c2")), /* SCK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 18), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2c2")), /* SDA */ + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* NWE */ + SUNXI_FUNCTION(0x3, "spi0")), /* MOSI */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* NALE */ + SUNXI_FUNCTION(0x3, "spi0")), /* MISO */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* NCLE */ + SUNXI_FUNCTION(0x3, "spi0")), /* CLK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* NCE1 */ + SUNXI_FUNCTION(0x3, "spi0")), /* CS0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 4), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0")), /* NCE0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 5), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0")), /* NRE */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 6), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* NRB0 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* CMD */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 7), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* NRB1 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* CLK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 8), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* NDQ0 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* D0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 9), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* NDQ1 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* D1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 10), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* NDQ2 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* D2 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 11), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* NDQ3 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* D3 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 12), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* NDQ4 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* D4 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 13), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* NDQ5 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* D5 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* NDQ6 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* D6 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 15), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* NDQ7 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* D7 */ + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 19), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* NDQS */ + SUNXI_FUNCTION(0x3, "uart2"), /* RX */ + SUNXI_FUNCTION(0x4, "uart3")), /* RTS */ + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D2 */ + SUNXI_FUNCTION(0x3, "uart2")), /* TX */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D3 */ + SUNXI_FUNCTION(0x3, "uart2")), /* RX */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 4), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D4 */ + SUNXI_FUNCTION(0x3, "uart2")), /* CTS */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 5), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D5 */ + SUNXI_FUNCTION(0x3, "uart2")), /* RTS */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 6), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D6 */ + SUNXI_FUNCTION(0x3, "emac")), /* ECRS */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 7), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D7 */ + SUNXI_FUNCTION(0x3, "emac")), /* ECOL */ + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 10), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D10 */ + SUNXI_FUNCTION(0x3, "emac")), /* ERXD0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 11), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D11 */ + SUNXI_FUNCTION(0x3, "emac")), /* ERXD1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 12), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D12 */ + SUNXI_FUNCTION(0x3, "emac")), /* ERXD2 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 13), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D13 */ + SUNXI_FUNCTION(0x3, "emac")), /* ERXD3 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 14), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D14 */ + SUNXI_FUNCTION(0x3, "emac")), /* ERXCK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 15), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D15 */ + SUNXI_FUNCTION(0x3, "emac")), /* ERXERR */ + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 18), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D18 */ + SUNXI_FUNCTION(0x3, "emac")), /* ERXDV */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 19), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D19 */ + SUNXI_FUNCTION(0x3, "emac")), /* ETXD0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 20), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D20 */ + SUNXI_FUNCTION(0x3, "emac")), /* ETXD1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 21), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D21 */ + SUNXI_FUNCTION(0x3, "emac")), /* ETXD2 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 22), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D22 */ + SUNXI_FUNCTION(0x3, "emac")), /* ETXD3 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 23), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D23 */ + SUNXI_FUNCTION(0x3, "emac")), /* ETXEN */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 24), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* CLK */ + SUNXI_FUNCTION(0x3, "emac")), /* ETXCK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 25), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* DE */ + SUNXI_FUNCTION(0x3, "emac")), /* ETXERR*/ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 26), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* HSYNC */ + SUNXI_FUNCTION(0x3, "emac")), /* EMDC */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 27), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* VSYNC */ + SUNXI_FUNCTION(0x3, "emac")), /* EMDIO */ + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x2, "ts0"), /* CLK */ + SUNXI_FUNCTION(0x3, "csi0"), /* PCLK */ + SUNXI_FUNCTION(0x4, "spi2"), /* CS0 */ + SUNXI_FUNCTION_IRQ(0x6, 14)), /* EINT14 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x2, "ts0"), /* ERR */ + SUNXI_FUNCTION(0x3, "csi0"), /* MCLK */ + SUNXI_FUNCTION(0x4, "spi2"), /* CLK */ + SUNXI_FUNCTION_IRQ(0x6, 15)), /* EINT15 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x2, "ts0"), /* SYNC */ + SUNXI_FUNCTION(0x3, "csi0"), /* HSYNC */ + SUNXI_FUNCTION(0x4, "spi2")), /* MOSI */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "ts0"), /* DVLD */ + SUNXI_FUNCTION(0x3, "csi0"), /* VSYNC */ + SUNXI_FUNCTION(0x4, "spi2")), /* MISO */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 4), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "ts0"), /* D0 */ + SUNXI_FUNCTION(0x3, "csi0"), /* D0 */ + SUNXI_FUNCTION(0x4, "mmc2")), /* D0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 5), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "ts0"), /* D1 */ + SUNXI_FUNCTION(0x3, "csi0"), /* D1 */ + SUNXI_FUNCTION(0x4, "mmc2")), /* D1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 6), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "ts0"), /* D2 */ + SUNXI_FUNCTION(0x3, "csi0"), /* D2 */ + SUNXI_FUNCTION(0x4, "mmc2")), /* D2 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 7), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "ts0"), /* D3 */ + SUNXI_FUNCTION(0x3, "csi0"), /* D3 */ + SUNXI_FUNCTION(0x4, "mmc2")), /* D3 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 8), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "ts0"), /* D4 */ + SUNXI_FUNCTION(0x3, "csi0"), /* D4 */ + SUNXI_FUNCTION(0x4, "mmc2")), /* CMD */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 9), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "ts0"), /* D5 */ + SUNXI_FUNCTION(0x3, "csi0"), /* D5 */ + SUNXI_FUNCTION(0x4, "mmc2")), /* CLK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 10), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "ts0"), /* D6 */ + SUNXI_FUNCTION(0x3, "csi0"), /* D6 */ + SUNXI_FUNCTION(0x4, "uart1")), /* TX */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 11), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "ts0"), /* D7 */ + SUNXI_FUNCTION(0x3, "csi0"), /* D7 */ + SUNXI_FUNCTION(0x4, "uart1")), /* RX */ + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc0"), /* D1 */ + SUNXI_FUNCTION(0x4, "jtag")), /* MS1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc0"), /* D0 */ + SUNXI_FUNCTION(0x4, "jtag")), /* DI1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc0"), /* CLK */ + SUNXI_FUNCTION(0x4, "uart0")), /* TX */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc0"), /* CMD */ + SUNXI_FUNCTION(0x4, "jtag")), /* DO1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc0"), /* D3 */ + SUNXI_FUNCTION(0x4, "uart0")), /* RX */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc0"), /* D2 */ + SUNXI_FUNCTION(0x4, "jtag")), /* CK1 */ + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x2, "gps"), /* CLK */ + SUNXI_FUNCTION_IRQ(0x6, 0)), /* EINT0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x2, "gps"), /* SIGN */ + SUNXI_FUNCTION_IRQ(0x6, 1)), /* EINT1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x2, "gps"), /* MAG */ + SUNXI_FUNCTION_IRQ(0x6, 2)), /* EINT2 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc1"), /* CMD */ + SUNXI_FUNCTION(0x3, "ms"), /* BS */ + SUNXI_FUNCTION(0x4, "uart1"), /* TX */ + SUNXI_FUNCTION_IRQ(0x6, 3)), /* EINT3 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc1"), /* CLK */ + SUNXI_FUNCTION(0x3, "ms"), /* CLK */ + SUNXI_FUNCTION(0x4, "uart1"), /* RX */ + SUNXI_FUNCTION_IRQ(0x6, 4)), /* EINT4 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc1"), /* D0 */ + SUNXI_FUNCTION(0x3, "ms"), /* D0 */ + SUNXI_FUNCTION(0x4, "uart1"), /* CTS */ + SUNXI_FUNCTION_IRQ(0x6, 5)), /* EINT5 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 6), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc1"), /* D1 */ + SUNXI_FUNCTION(0x3, "ms"), /* D1 */ + SUNXI_FUNCTION(0x4, "uart1"), /* RTS */ + SUNXI_FUNCTION(0x5, "uart2"), /* RTS */ + SUNXI_FUNCTION_IRQ(0x6, 6)), /* EINT6 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 7), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc1"), /* D2 */ + SUNXI_FUNCTION(0x3, "ms"), /* D2 */ + SUNXI_FUNCTION(0x5, "uart2"), /* TX */ + SUNXI_FUNCTION_IRQ(0x6, 7)), /* EINT7 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 8), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc1"), /* D3 */ + SUNXI_FUNCTION(0x3, "ms"), /* D3 */ + SUNXI_FUNCTION(0x5, "uart2"), /* RX */ + SUNXI_FUNCTION_IRQ(0x6, 8)), /* EINT8 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 9), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi1"), /* CS0 */ + SUNXI_FUNCTION(0x3, "uart3"), /* TX */ + SUNXI_FUNCTION_IRQ(0x6, 9)), /* EINT9 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi1"), /* CLK */ + SUNXI_FUNCTION(0x3, "uart3"), /* RX */ + SUNXI_FUNCTION_IRQ(0x6, 10)), /* EINT10 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 11), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi1"), /* MOSI */ + SUNXI_FUNCTION(0x3, "uart3"), /* CTS */ + SUNXI_FUNCTION_IRQ(0x6, 11)), /* EINT11 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 12), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi1"), /* MISO */ + SUNXI_FUNCTION(0x3, "uart3"), /* RTS */ + SUNXI_FUNCTION_IRQ(0x6, 12)), /* EINT12 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 13), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi1"), /* CS1 */ + SUNXI_FUNCTION(0x3, "pwm1"), + SUNXI_FUNCTION(0x5, "uart2"), /* CTS */ + SUNXI_FUNCTION_IRQ(0x6, 13)), /* EINT13 */ +}; + +static const struct sunxi_pinctrl_desc sun5i_gr8_pinctrl_data = { + .pins = sun5i_gr8_pins, + .npins = ARRAY_SIZE(sun5i_gr8_pins), + .irq_banks = 1, +}; + +static int sun5i_gr8_pinctrl_probe(struct platform_device *pdev) +{ + return sunxi_pinctrl_init(pdev, + &sun5i_gr8_pinctrl_data); +} + +static const struct of_device_id sun5i_gr8_pinctrl_match[] = { + { .compatible = "nextthing,gr8-pinctrl", }, + {} +}; +MODULE_DEVICE_TABLE(of, sun5i_gr8_pinctrl_match); + +static struct platform_driver sun5i_gr8_pinctrl_driver = { + .probe = sun5i_gr8_pinctrl_probe, + .driver = { + .name = "gr8-pinctrl", + .of_match_table = sun5i_gr8_pinctrl_match, + }, +}; +module_platform_driver(sun5i_gr8_pinctrl_driver); + +MODULE_AUTHOR("Mylene Josserand Date: Wed, 31 Aug 2016 08:50:49 +0000 Subject: pinctrl/amd: Configure GPIO register using BIOS settings In the function amd_gpio_irq_set_type, use the settings provided by the BIOS,when the LevelTrig is Edge and activeLevel is HIGH, to configure the GPIO registers. Ignore the settings from client. Reviewed-by: Pankaj Sen Signed-off-by:Nitesh Kumar Agrawal Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-amd.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/drivers/pinctrl/pinctrl-amd.c b/drivers/pinctrl/pinctrl-amd.c index 634b4d30eefb..962746e6ab04 100644 --- a/drivers/pinctrl/pinctrl-amd.c +++ b/drivers/pinctrl/pinctrl-amd.c @@ -403,12 +403,27 @@ static int amd_gpio_irq_set_type(struct irq_data *d, unsigned int type) int ret = 0; u32 pin_reg; unsigned long flags; + u32 level_trig; + u32 active_level; struct gpio_chip *gc = irq_data_get_irq_chip_data(d); struct amd_gpio *gpio_dev = gpiochip_get_data(gc); spin_lock_irqsave(&gpio_dev->lock, flags); pin_reg = readl(gpio_dev->base + (d->hwirq)*4); + /* + * When level_trig is set EDGE and active_level is set HIGH in BIOS + * default settings, ignore incoming settings from client and use + * BIOS settings to configure GPIO register. + */ + level_trig = pin_reg & (LEVEL_TRIGGER << LEVEL_TRIG_OFF); + active_level = pin_reg & (ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); + + if((!level_trig) && + ((active_level >> ACTIVE_LEVEL_OFF) == ACTIVE_HIGH)) { + type = IRQ_TYPE_EDGE_FALLING; + } + switch (type & IRQ_TYPE_SENSE_MASK) { case IRQ_TYPE_EDGE_RISING: pin_reg &= ~BIT(LEVEL_TRIG_OFF); -- cgit 1.4.1 From f3b4b7c48e5998af8c009821c7dbb2137db33b35 Mon Sep 17 00:00:00 2001 From: Julia Lawall Date: Thu, 1 Sep 2016 20:42:19 +0200 Subject: pinctrl: ns2: constify pinctrl_ops and pinmux_ops structures Check for pinctrl_ops and pinmux_ops structures that are only stored in the pctlops field and the pmxops field, respectively, of a pinctrl_desc structure. These fields are declared const, so pinctrl_ops and pinmux_ops structures that have this property can be declared as const also. The semantic patch that makes this change in the pinctrl_ops is as follows. The pinmux_ops case is similar. (http://coccinelle.lip6.fr/) // @r disable optional_qualifier@ identifier i; position p; @@ static struct pinctrl_ops i@p = { ... }; @ok@ identifier r.i; struct pinctrl_desc e; position p; @@ e.pctlops = &i@p; @bad@ position p != {r.p,ok.p}; identifier r.i; struct pinctrl_ops e; @@ e@i@p @depends on !bad disable optional_qualifier@ identifier r.i; @@ static +const struct pinctrl_ops i = { ... }; // Signed-off-by: Julia Lawall Signed-off-by: Linus Walleij --- drivers/pinctrl/bcm/pinctrl-ns2-mux.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/bcm/pinctrl-ns2-mux.c b/drivers/pinctrl/bcm/pinctrl-ns2-mux.c index ca817896ed24..13a4c2774157 100644 --- a/drivers/pinctrl/bcm/pinctrl-ns2-mux.c +++ b/drivers/pinctrl/bcm/pinctrl-ns2-mux.c @@ -531,7 +531,7 @@ static void ns2_pin_dbg_show(struct pinctrl_dev *pctrl_dev, seq_printf(s, " %s", dev_name(pctrl_dev->dev)); } -static struct pinctrl_ops ns2_pinctrl_ops = { +static const struct pinctrl_ops ns2_pinctrl_ops = { .get_groups_count = ns2_get_groups_count, .get_group_name = ns2_get_group_name, .get_group_pins = ns2_get_group_pins, @@ -959,7 +959,7 @@ static int ns2_pin_config_set(struct pinctrl_dev *pctrldev, unsigned int pin, out: return ret; } -static struct pinmux_ops ns2_pinmux_ops = { +static const struct pinmux_ops ns2_pinmux_ops = { .get_functions_count = ns2_get_functions_count, .get_function_name = ns2_get_function_name, .get_function_groups = ns2_get_function_groups, -- cgit 1.4.1 From c87da270c11fcf995fb0bc7248e446821b32f573 Mon Sep 17 00:00:00 2001 From: Julia Lawall Date: Thu, 1 Sep 2016 20:42:20 +0200 Subject: pinctrl: nsp: constify pinctrl_ops and pinmux_ops structures Check for pinctrl_ops and pinmux_ops structures that are only stored in the pctlops field and the pmxops field, respectively, of a pinctrl_desc structure. These fields are declared const, so pinctrl_ops and pinmux_ops structures that have this property can be declared as const also. The semantic patch that makes this change in the pinctrl_ops is as follows. The pinmux_ops case is similar. (http://coccinelle.lip6.fr/) // @r disable optional_qualifier@ identifier i; position p; @@ static struct pinctrl_ops i@p = { ... }; @ok@ identifier r.i; struct pinctrl_desc e; position p; @@ e.pctlops = &i@p; @bad@ position p != {r.p,ok.p}; identifier r.i; struct pinctrl_ops e; @@ e@i@p @depends on !bad disable optional_qualifier@ identifier r.i; @@ static +const struct pinctrl_ops i = { ... }; // Signed-off-by: Julia Lawall Signed-off-by: Linus Walleij --- drivers/pinctrl/bcm/pinctrl-nsp-mux.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/bcm/pinctrl-nsp-mux.c b/drivers/pinctrl/bcm/pinctrl-nsp-mux.c index 4149db309c8b..35c17653c694 100644 --- a/drivers/pinctrl/bcm/pinctrl-nsp-mux.c +++ b/drivers/pinctrl/bcm/pinctrl-nsp-mux.c @@ -348,7 +348,7 @@ static void nsp_pin_dbg_show(struct pinctrl_dev *pctrl_dev, seq_printf(s, " %s", dev_name(pctrl_dev->dev)); } -static struct pinctrl_ops nsp_pinctrl_ops = { +static const struct pinctrl_ops nsp_pinctrl_ops = { .get_groups_count = nsp_get_groups_count, .get_group_name = nsp_get_group_name, .get_group_pins = nsp_get_group_pins, @@ -518,7 +518,7 @@ static void nsp_gpio_disable_free(struct pinctrl_dev *pctrl_dev, spin_unlock_irqrestore(&pinctrl->lock, flags); } -static struct pinmux_ops nsp_pinmux_ops = { +static const struct pinmux_ops nsp_pinmux_ops = { .get_functions_count = nsp_get_functions_count, .get_function_name = nsp_get_function_name, .get_function_groups = nsp_get_function_groups, -- cgit 1.4.1 From 5fe2501fbf8d21d57fef2eb0a54d50f5a0c6f4c4 Mon Sep 17 00:00:00 2001 From: Julia Lawall Date: Thu, 1 Sep 2016 20:42:21 +0200 Subject: pinctrl: bcm281xx: constify pinctrl_ops and pinmux_ops structures Check for pinctrl_ops and pinmux_ops structures that are only stored in the pctlops field and the pmxops field, respectively, of a pinctrl_desc structure. These fields are declared const, so pinctrl_ops and pinmux_ops structures that have this property can be declared as const also. The semantic patch that makes this change in the pinctrl_ops is as follows. The pinmux_ops case is similar. (http://coccinelle.lip6.fr/) // @r disable optional_qualifier@ identifier i; position p; @@ static struct pinctrl_ops i@p = { ... }; @ok@ identifier r.i; struct pinctrl_desc e; position p; @@ e.pctlops = &i@p; @bad@ position p != {r.p,ok.p}; identifier r.i; struct pinctrl_ops e; @@ e@i@p @depends on !bad disable optional_qualifier@ identifier r.i; @@ static +const struct pinctrl_ops i = { ... }; // Signed-off-by: Julia Lawall Signed-off-by: Linus Walleij --- drivers/pinctrl/bcm/pinctrl-bcm281xx.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/bcm/pinctrl-bcm281xx.c b/drivers/pinctrl/bcm/pinctrl-bcm281xx.c index 582f6df446e8..a5331fdfc795 100644 --- a/drivers/pinctrl/bcm/pinctrl-bcm281xx.c +++ b/drivers/pinctrl/bcm/pinctrl-bcm281xx.c @@ -1018,7 +1018,7 @@ static void bcm281xx_pinctrl_pin_dbg_show(struct pinctrl_dev *pctldev, seq_printf(s, " %s", dev_name(pctldev->dev)); } -static struct pinctrl_ops bcm281xx_pinctrl_ops = { +static const struct pinctrl_ops bcm281xx_pinctrl_ops = { .get_groups_count = bcm281xx_pinctrl_get_groups_count, .get_group_name = bcm281xx_pinctrl_get_group_name, .get_group_pins = bcm281xx_pinctrl_get_group_pins, @@ -1080,7 +1080,7 @@ static int bcm281xx_pinmux_set(struct pinctrl_dev *pctldev, return rc; } -static struct pinmux_ops bcm281xx_pinctrl_pinmux_ops = { +static const struct pinmux_ops bcm281xx_pinctrl_pinmux_ops = { .get_functions_count = bcm281xx_pinctrl_get_fcns_count, .get_function_name = bcm281xx_pinctrl_get_fcn_name, .get_function_groups = bcm281xx_pinctrl_get_fcn_groups, -- cgit 1.4.1 From 66cd89df8c043cc3a1a3d28c0a73f7c733935898 Mon Sep 17 00:00:00 2001 From: Milo Kim Date: Wed, 31 Aug 2016 17:25:19 +0900 Subject: pinctrl: sunxi: Remove unsupported PWM channel pinmux in H3 H3 has single PWM channel. The second PWM channel is not supported, so the pinctrl function should be removed. Signed-off-by: Milo Kim Acked-by: Chen-Yu Tsai Signed-off-by: Linus Walleij --- drivers/pinctrl/sunxi/pinctrl-sun8i-h3.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/pinctrl/sunxi/pinctrl-sun8i-h3.c b/drivers/pinctrl/sunxi/pinctrl-sun8i-h3.c index 26a2ad3b651f..518a92df4418 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sun8i-h3.c +++ b/drivers/pinctrl/sunxi/pinctrl-sun8i-h3.c @@ -60,7 +60,6 @@ static const struct sunxi_desc_pin sun8i_h3_pins[] = { SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "sim"), /* PWREN */ - SUNXI_FUNCTION(0x3, "pwm1"), SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)), /* PA_EINT6 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 7), SUNXI_FUNCTION(0x0, "gpio_in"), -- cgit 1.4.1 From 446bd7dd922edd033d28ef9aa8c594c1c2d05289 Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Sat, 3 Sep 2016 00:50:30 +0300 Subject: pinctrl: sh-pfc: r8a7792: Add QSPI pin groups Add QSPI pin groups to the R8A7792 PFC driver. Based on the original (and large) patch by Vladimir Barinov . Signed-off-by: Sergei Shtylyov Acked-by: Linus Walleij Signed-off-by: Geert Uytterhoeven --- drivers/pinctrl/sh-pfc/pfc-r8a7792.c | 33 +++++++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7792.c b/drivers/pinctrl/sh-pfc/pfc-r8a7792.c index 92c670992b3d..0a3e4e03259b 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7792.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7792.c @@ -1034,6 +1034,29 @@ static const unsigned int lbsc_ex_cs5_pins[] = { static const unsigned int lbsc_ex_cs5_mux[] = { EX_CS5_N_MARK, }; +/* - QSPI ------------------------------------------------------------------- */ +static const unsigned int qspi_ctrl_pins[] = { + /* SPCLK, SSL */ + RCAR_GP_PIN(3, 25), RCAR_GP_PIN(3, 26), +}; +static const unsigned int qspi_ctrl_mux[] = { + SPCLK_MARK, SSL_MARK, +}; +static const unsigned int qspi_data2_pins[] = { + /* MOSI_IO0, MISO_IO1 */ + RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5), +}; +static const unsigned int qspi_data2_mux[] = { + MOSI_IO0_MARK, MISO_IO1_MARK, +}; +static const unsigned int qspi_data4_pins[] = { + /* MOSI_IO0, MISO_IO1, IO2, IO3 */ + RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 23), + RCAR_GP_PIN(3, 24), +}; +static const unsigned int qspi_data4_mux[] = { + MOSI_IO0_MARK, MISO_IO1_MARK, IO2_MARK, IO3_MARK, +}; /* - SCIF0 ------------------------------------------------------------------ */ static const unsigned int scif0_data_pins[] = { /* RX, TX */ @@ -1585,6 +1608,9 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(lbsc_ex_cs3), SH_PFC_PIN_GROUP(lbsc_ex_cs4), SH_PFC_PIN_GROUP(lbsc_ex_cs5), + SH_PFC_PIN_GROUP(qspi_ctrl), + SH_PFC_PIN_GROUP(qspi_data2), + SH_PFC_PIN_GROUP(qspi_data4), SH_PFC_PIN_GROUP(scif0_data), SH_PFC_PIN_GROUP(scif0_clk), SH_PFC_PIN_GROUP(scif0_ctrl), @@ -1708,6 +1734,12 @@ static const char * const lbsc_groups[] = { "lbsc_ex_cs5", }; +static const char * const qspi_groups[] = { + "qspi_ctrl", + "qspi_data2", + "qspi_data4", +}; + static const char * const scif0_groups[] = { "scif0_data", "scif0_clk", @@ -1808,6 +1840,7 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(du1), SH_PFC_FUNCTION(intc), SH_PFC_FUNCTION(lbsc), + SH_PFC_FUNCTION(qspi), SH_PFC_FUNCTION(scif0), SH_PFC_FUNCTION(scif3), SH_PFC_FUNCTION(sdhi0), -- cgit 1.4.1 From c30716894e96ed1e76bf32ae68c5438350700496 Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Mon, 5 Sep 2016 23:17:31 +0300 Subject: pinctrl: sh-pfc: r8a7792: Add MSIOF pin groups Add MSIOF0/1 pin groups to the R8A7792 PFC driver. Based on the original (and large) patch by Vladimir Barinov . Signed-off-by: Sergei Shtylyov Signed-off-by: Geert Uytterhoeven --- drivers/pinctrl/sh-pfc/pfc-r8a7792.c | 82 ++++++++++++++++++++++++++++++++++++ 1 file changed, 82 insertions(+) diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7792.c b/drivers/pinctrl/sh-pfc/pfc-r8a7792.c index 0a3e4e03259b..21badb6166b9 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7792.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7792.c @@ -1034,6 +1034,64 @@ static const unsigned int lbsc_ex_cs5_pins[] = { static const unsigned int lbsc_ex_cs5_mux[] = { EX_CS5_N_MARK, }; +/* - MSIOF0 ----------------------------------------------------------------- */ +static const unsigned int msiof0_clk_pins[] = { + /* SCK */ + RCAR_GP_PIN(10, 0), +}; +static const unsigned int msiof0_clk_mux[] = { + MSIOF0_SCK_MARK, +}; +static const unsigned int msiof0_sync_pins[] = { + /* SYNC */ + RCAR_GP_PIN(10, 1), +}; +static const unsigned int msiof0_sync_mux[] = { + MSIOF0_SYNC_MARK, +}; +static const unsigned int msiof0_rx_pins[] = { + /* RXD */ + RCAR_GP_PIN(10, 4), +}; +static const unsigned int msiof0_rx_mux[] = { + MSIOF0_RXD_MARK, +}; +static const unsigned int msiof0_tx_pins[] = { + /* TXD */ + RCAR_GP_PIN(10, 3), +}; +static const unsigned int msiof0_tx_mux[] = { + MSIOF0_TXD_MARK, +}; +/* - MSIOF1 ----------------------------------------------------------------- */ +static const unsigned int msiof1_clk_pins[] = { + /* SCK */ + RCAR_GP_PIN(10, 5), +}; +static const unsigned int msiof1_clk_mux[] = { + MSIOF1_SCK_MARK, +}; +static const unsigned int msiof1_sync_pins[] = { + /* SYNC */ + RCAR_GP_PIN(10, 6), +}; +static const unsigned int msiof1_sync_mux[] = { + MSIOF1_SYNC_MARK, +}; +static const unsigned int msiof1_rx_pins[] = { + /* RXD */ + RCAR_GP_PIN(10, 9), +}; +static const unsigned int msiof1_rx_mux[] = { + MSIOF1_RXD_MARK, +}; +static const unsigned int msiof1_tx_pins[] = { + /* TXD */ + RCAR_GP_PIN(10, 8), +}; +static const unsigned int msiof1_tx_mux[] = { + MSIOF1_TXD_MARK, +}; /* - QSPI ------------------------------------------------------------------- */ static const unsigned int qspi_ctrl_pins[] = { /* SPCLK, SSL */ @@ -1608,6 +1666,14 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(lbsc_ex_cs3), SH_PFC_PIN_GROUP(lbsc_ex_cs4), SH_PFC_PIN_GROUP(lbsc_ex_cs5), + SH_PFC_PIN_GROUP(msiof0_clk), + SH_PFC_PIN_GROUP(msiof0_sync), + SH_PFC_PIN_GROUP(msiof0_rx), + SH_PFC_PIN_GROUP(msiof0_tx), + SH_PFC_PIN_GROUP(msiof1_clk), + SH_PFC_PIN_GROUP(msiof1_sync), + SH_PFC_PIN_GROUP(msiof1_rx), + SH_PFC_PIN_GROUP(msiof1_tx), SH_PFC_PIN_GROUP(qspi_ctrl), SH_PFC_PIN_GROUP(qspi_data2), SH_PFC_PIN_GROUP(qspi_data4), @@ -1734,6 +1800,20 @@ static const char * const lbsc_groups[] = { "lbsc_ex_cs5", }; +static const char * const msiof0_groups[] = { + "msiof0_clk", + "msiof0_sync", + "msiof0_rx", + "msiof0_tx", +}; + +static const char * const msiof1_groups[] = { + "msiof1_clk", + "msiof1_sync", + "msiof1_rx", + "msiof1_tx", +}; + static const char * const qspi_groups[] = { "qspi_ctrl", "qspi_data2", @@ -1840,6 +1920,8 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(du1), SH_PFC_FUNCTION(intc), SH_PFC_FUNCTION(lbsc), + SH_PFC_FUNCTION(msiof0), + SH_PFC_FUNCTION(msiof1), SH_PFC_FUNCTION(qspi), SH_PFC_FUNCTION(scif0), SH_PFC_FUNCTION(scif3), -- cgit 1.4.1 From 40ade582194668aa4336a30f96c9d592c46a1928 Mon Sep 17 00:00:00 2001 From: Niklas Söderlund Date: Tue, 6 Sep 2016 17:14:14 +0200 Subject: pinctrl: sh-pfc: Return pinconf with arguments in packed format MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The pinconf-generic code expects configurations with arguments to be returned in a packed format in order to be displayed properly by pinconf_generic_dump_one(). Reading /sys/kernel/debug/pinctrl/e6060000.pfc/pinconf-pins on r8a7795/salvator-x now shows: pin 101 (GP_3_5): output drive strength (9 mA), pin power source (3300 selector) Instead of: pin 101 (GP_3_5): output drive strength (0 mA), pin power source (0 selector) Signed-off-by: Niklas Söderlund Tested-by: Geert Uytterhoeven Signed-off-by: Geert Uytterhoeven --- drivers/pinctrl/sh-pfc/pinctrl.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/drivers/pinctrl/sh-pfc/pinctrl.c b/drivers/pinctrl/sh-pfc/pinctrl.c index e208ee04a9f4..c5772584594c 100644 --- a/drivers/pinctrl/sh-pfc/pinctrl.c +++ b/drivers/pinctrl/sh-pfc/pinctrl.c @@ -596,6 +596,7 @@ static int sh_pfc_pinconf_get(struct pinctrl_dev *pctldev, unsigned _pin, struct sh_pfc *pfc = pmx->pfc; enum pin_config_param param = pinconf_to_config_param(*config); unsigned long flags; + unsigned int arg; if (!sh_pfc_pinconf_validate(pfc, _pin, param)) return -ENOTSUPP; @@ -616,7 +617,7 @@ static int sh_pfc_pinconf_get(struct pinctrl_dev *pctldev, unsigned _pin, if (bias != param) return -EINVAL; - *config = 0; + arg = 0; break; } @@ -627,7 +628,7 @@ static int sh_pfc_pinconf_get(struct pinctrl_dev *pctldev, unsigned _pin, if (ret < 0) return ret; - *config = ret; + arg = ret; break; } @@ -646,7 +647,7 @@ static int sh_pfc_pinconf_get(struct pinctrl_dev *pctldev, unsigned _pin, val = sh_pfc_read_reg(pfc, pocctrl, 32); spin_unlock_irqrestore(&pfc->lock, flags); - *config = (val & BIT(bit)) ? 3300 : 1800; + arg = (val & BIT(bit)) ? 3300 : 1800; break; } @@ -654,6 +655,7 @@ static int sh_pfc_pinconf_get(struct pinctrl_dev *pctldev, unsigned _pin, return -ENOTSUPP; } + *config = pinconf_to_config_packed(param, arg); return 0; } -- cgit 1.4.1 From c5901bdcbc6142b686b15d0b4a959aa19a350af1 Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Thu, 8 Sep 2016 13:57:33 +0200 Subject: pinctrl: sh-pfc: r8a7796: Add voltage switch operations for SDHI This patch supports the {get,set}_io_voltage operations of SDHI. This operates the POCCTRL0 register on R8A7796 SoC and makes 1.8v/3.3v voltage switch. Based on work by Takeshi Kihara and Wolfram Sang. Cc: Takeshi Kihara Signed-off-by: Simon Horman Reviewed-by: Wolfram Sang Signed-off-by: Geert Uytterhoeven --- drivers/pinctrl/sh-pfc/pfc-r8a7796.c | 28 ++++++++++++++++++++++++++-- 1 file changed, 26 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c index f8ab74dd0506..dc9b671ccf2e 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c @@ -23,8 +23,12 @@ PORT_GP_16(0, fn, sfx), \ PORT_GP_29(1, fn, sfx), \ PORT_GP_15(2, fn, sfx), \ - PORT_GP_16(3, fn, sfx), \ - PORT_GP_18(4, fn, sfx), \ + PORT_GP_CFG_12(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \ + PORT_GP_1(3, 12, fn, sfx), \ + PORT_GP_1(3, 13, fn, sfx), \ + PORT_GP_1(3, 14, fn, sfx), \ + PORT_GP_1(3, 15, fn, sfx), \ + PORT_GP_CFG_18(4, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \ PORT_GP_26(5, fn, sfx), \ PORT_GP_32(6, fn, sfx), \ PORT_GP_4(7, fn, sfx) @@ -2627,8 +2631,28 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { { }, }; +static int r8a7796_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl) +{ + int bit = -EINVAL; + + *pocctrl = 0xe6060380; + + if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 11)) + bit = pin & 0x1f; + + if (pin >= RCAR_GP_PIN(4, 0) && pin <= RCAR_GP_PIN(4, 17)) + bit = (pin & 0x1f) + 12; + + return bit; +} + +static const struct sh_pfc_soc_operations r8a7796_pinmux_ops = { + .pin_to_pocctrl = r8a7796_pin_to_pocctrl, +}; + const struct sh_pfc_soc_info r8a7796_pinmux_info = { .name = "r8a77960_pfc", + .ops = &r8a7796_pinmux_ops, .unlock_reg = 0xe6060000, /* PMMR */ .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, -- cgit 1.4.1 From 5803348cfcead8ac768e3c86bbe6f5afb5a10935 Mon Sep 17 00:00:00 2001 From: Marc Zyngier Date: Tue, 6 Sep 2016 14:58:15 +0100 Subject: pinctrl/at91: Don't provide a default trigger type at91 used to set a default trigger type for GPIO interrupts in order to cope with the old board files. These days are long gone, and it all gets probed through DT. Andras Szemzo reported that the Ethernet device on his board was bailing to be probed, due to a conflict in interrupt trigger. Surely enough, this is due to this default trigger still being present, and turning this into a IRQ_TYPE_NONE fixes the issue. Reported-by: Andras Szemzo Tested-by: Andras Szemzo Cc: Linus Walleij Cc: Jean-Christophe PLAGNIOL-VILLARD Signed-off-by: Marc Zyngier Acked-by: Nicolas Ferre Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-at91.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/pinctrl-at91.c b/drivers/pinctrl/pinctrl-at91.c index 80daead3a5a1..9f0904185909 100644 --- a/drivers/pinctrl/pinctrl-at91.c +++ b/drivers/pinctrl/pinctrl-at91.c @@ -1614,7 +1614,7 @@ static int at91_gpio_of_irq_setup(struct platform_device *pdev, &gpio_irqchip, 0, handle_edge_irq, - IRQ_TYPE_EDGE_BOTH); + IRQ_TYPE_NONE); if (ret) { dev_err(&pdev->dev, "at91_gpio.%d: Couldn't add irqchip to gpiochip.\n", at91_gpio->pioc_idx); -- cgit 1.4.1 From 430be10dd356fe9f1c142222fb9cc78feb00e86f Mon Sep 17 00:00:00 2001 From: Vladimir Zapolskiy Date: Thu, 8 Sep 2016 04:48:14 +0300 Subject: pinctrl: imx: accept gpio request/free from pinctrl While only Freescale Vybrid SoC has settings of GPIO capabilities done by iomux controller, it is only a matter of GPIO controller driver implementation for the rest of Freescale/NXP SoCs from iMX series. As a practical example on GPIO request a pad function should be switched to GPIO, but because this requires updates to all particular iMX pinctrl drivers, for simplicity at the moment add only a proper connection between shared pinctrl-imx and pinctrl/pinmux core, namely .gpio_request_enable/.gpio_disable_free/.gpio_set_direction callbacks should return success to a caller. This change allows to progress by adding request/free callbacks into gpio-mxc.c driver. Signed-off-by: Vladimir Zapolskiy Acked-by: Shawn Guo Signed-off-by: Linus Walleij --- drivers/pinctrl/freescale/pinctrl-imx.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/freescale/pinctrl-imx.c b/drivers/pinctrl/freescale/pinctrl-imx.c index 56fd88013850..47613201269a 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx.c +++ b/drivers/pinctrl/freescale/pinctrl-imx.c @@ -315,7 +315,7 @@ static int imx_pmx_gpio_request_enable(struct pinctrl_dev *pctldev, /* Currently implementation only for shared mux/conf register */ if (!(info->flags & SHARE_MUX_CONF_REG)) - return -EINVAL; + return 0; pin_reg = &info->pin_regs[offset]; if (pin_reg->mux_reg == -1) @@ -380,7 +380,7 @@ static int imx_pmx_gpio_set_direction(struct pinctrl_dev *pctldev, * They are part of the shared mux/conf register. */ if (!(info->flags & SHARE_MUX_CONF_REG)) - return -EINVAL; + return 0; pin_reg = &info->pin_regs[offset]; if (pin_reg->mux_reg == -1) -- cgit 1.4.1 From e188cbf7564fba80e8339b9406e8740f3e495c63 Mon Sep 17 00:00:00 2001 From: Vladimir Zapolskiy Date: Thu, 8 Sep 2016 04:48:15 +0300 Subject: gpio: mxc: shift gpio_mxc_init() to subsys_initcall level In general situation on-SoC GPIO controller drivers should be probed after pinctrl/pinmux controller driver, because on-SoC GPIOs utilize a pin/pad as a resource provided and controlled by pinctrl subsystem. This is stated in multiple places, e.g. from drivers/Makefile: GPIO must come after pinctrl as gpios may need to mux pins etc Looking at Freescale iMX SoC series specifics, imx*_pinctrl_init() functions are called at arch_initcall and postcore_initcall init levels, so the change of initcall level for gpio-mxc driver from postcore_initcall to subsys_initcall level is sufficient. Also note that the most of GPIO controller drivers settled at subsys_initcall level. If pinctrl subsystem manages pads with GPIO functions, the change is needed to avoid unwanted driver probe deferrals during kernel boot. Signed-off-by: Vladimir Zapolskiy Acked-by: Shawn Guo Signed-off-by: Linus Walleij --- drivers/gpio/gpio-mxc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpio/gpio-mxc.c b/drivers/gpio/gpio-mxc.c index 1b342a3842c8..1fdd5d804b5b 100644 --- a/drivers/gpio/gpio-mxc.c +++ b/drivers/gpio/gpio-mxc.c @@ -510,7 +510,7 @@ static int __init gpio_mxc_init(void) { return platform_driver_register(&mxc_gpio_driver); } -postcore_initcall(gpio_mxc_init); +subsys_initcall(gpio_mxc_init); MODULE_AUTHOR("Freescale Semiconductor, " "Daniel Mack , " -- cgit 1.4.1 From 4c806c9891100e80cbd6be654de7c8ca6f6be3ef Mon Sep 17 00:00:00 2001 From: Vladimir Zapolskiy Date: Thu, 8 Sep 2016 04:48:16 +0300 Subject: gpio: mxc: add generic gpio request/free callbacks to pinctrl If a GPIO controller description in board DTB contains information about mappings between GPIOs and pads under IOMUX control use it to request and free GPIOs with respect to pinctrl/pinmux subsystems. One of immediate positive functional changes is inability to request non-existing GPIOs, i.e. if there is no pad such. Also pinctrl/pinmux may now properly account pads occupied by requested GPIOs. The change has no effect, if "gpio-ranges" property is not found including the case if a board has no DTB firmware. Signed-off-by: Vladimir Zapolskiy Acked-by: Shawn Guo Signed-off-by: Linus Walleij --- drivers/gpio/gpio-mxc.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/gpio/gpio-mxc.c b/drivers/gpio/gpio-mxc.c index 1fdd5d804b5b..e38989a4fa0c 100644 --- a/drivers/gpio/gpio-mxc.c +++ b/drivers/gpio/gpio-mxc.c @@ -458,6 +458,11 @@ static int mxc_gpio_probe(struct platform_device *pdev) if (err) goto out_bgio; + if (of_property_read_bool(np, "gpio-ranges")) { + port->gc.request = gpiochip_generic_request; + port->gc.free = gpiochip_generic_free; + } + port->gc.to_irq = mxc_gpio_to_irq; port->gc.base = (pdev->id < 0) ? of_alias_get_id(np, "gpio") * 32 : pdev->id * 32; -- cgit 1.4.1 From c11a0442b0fe01244de09849f62a0370482a0196 Mon Sep 17 00:00:00 2001 From: Vincent Stehlé Date: Wed, 31 Aug 2016 14:30:50 +0200 Subject: pinctrl: intel: merrifield: fix dup size in probe MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit In function mrfld_pinctrl_probe(), when duplicating the mrfld_families array the requested memory region length is multiplied once too many by the number of elements in the original array. Fix this to spare some memory. Fixes: 4e80c8f505741cbd ("pinctrl: intel: Add Intel Merrifield pin controller support") Signed-off-by: Vincent Stehlé Acked-by: Andy Shevchenko Signed-off-by: Linus Walleij --- drivers/pinctrl/intel/pinctrl-merrifield.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/intel/pinctrl-merrifield.c b/drivers/pinctrl/intel/pinctrl-merrifield.c index 7fb765642ee7..7826c7f0cb7c 100644 --- a/drivers/pinctrl/intel/pinctrl-merrifield.c +++ b/drivers/pinctrl/intel/pinctrl-merrifield.c @@ -854,7 +854,7 @@ static int mrfld_pinctrl_probe(struct platform_device *pdev) */ nfamilies = ARRAY_SIZE(mrfld_families), families = devm_kmemdup(&pdev->dev, mrfld_families, - nfamilies * sizeof(mrfld_families), + sizeof(mrfld_families), GFP_KERNEL); if (!families) return -ENOMEM; -- cgit 1.4.1 From b09eed7f811de64f1352634baa48ca8aecddac51 Mon Sep 17 00:00:00 2001 From: Sylwester Nawrocki Date: Thu, 1 Sep 2016 13:59:00 +0200 Subject: pinctrl: samsung: Remove an always false dev->of_node test samsung_pinctrl_probe() can be called only after matching the driver by the compatible string so this already implies a non null dev->of_node. Remove the always false test and related error trace. While at it drop another error log in case of memory allocation failure - any errors are logged by the memory subsystem. Signed-off-by: Sylwester Nawrocki Reviewed-by: Krzysztof Kozlowski Signed-off-by: Linus Walleij --- drivers/pinctrl/samsung/pinctrl-samsung.c | 10 +--------- 1 file changed, 1 insertion(+), 9 deletions(-) diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.c b/drivers/pinctrl/samsung/pinctrl-samsung.c index 513fe6b23248..620727fabe64 100644 --- a/drivers/pinctrl/samsung/pinctrl-samsung.c +++ b/drivers/pinctrl/samsung/pinctrl-samsung.c @@ -1041,17 +1041,9 @@ static int samsung_pinctrl_probe(struct platform_device *pdev) struct resource *res; int ret; - if (!dev->of_node) { - dev_err(dev, "device tree node not found\n"); - return -ENODEV; - } - drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL); - if (!drvdata) { - dev_err(dev, "failed to allocate memory for driver's " - "private data\n"); + if (!drvdata) return -ENOMEM; - } ctrl = samsung_pinctrl_get_soc_data(drvdata, pdev); if (IS_ERR(ctrl)) { -- cgit 1.4.1 From 23fb16194b95089b3cf5eb88d446662ee7da0f43 Mon Sep 17 00:00:00 2001 From: Alexandre TORGUE Date: Fri, 9 Sep 2016 16:42:00 +0200 Subject: pinctrl: Add IRQ related DT properties of STM32 pinctrl Signed-off-by: Maxime Coquelin Acked-by: Rob Herring Signed-off-by: Alexandre TORGUE Signed-off-by: Linus Walleij --- Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt index 587bffb9cbc6..a0eed99214b5 100644 --- a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt @@ -14,6 +14,9 @@ Required properies: - #size-cells : The value of this property must be 1 - ranges : defines mapping between pin controller node (parent) to gpio-bank node (children). + - interrupt-parent: phandle of the interrupt parent to which the external + GPIO interrupts are forwarded to. + - st,syscfg: phandle of the syscfg node used for IRQ mux selection. - pins-are-numbered: Specify the subnodes are using numbered pinmux to specify pins. -- cgit 1.4.1 From 0eb9f683336d7eb99a3b75987620417c574ffb57 Mon Sep 17 00:00:00 2001 From: Alexandre TORGUE Date: Fri, 9 Sep 2016 16:42:01 +0200 Subject: pinctrl: Add IRQ support to STM32 gpios This patch adds IRQ support to STM32 gpios. The EXTI controller has 16 lines dedicated to GPIOs. EXTI line n can be connected to only line n of one of the GPIO ports, for example EXTI0 can be connected to either PA0, or PB0, or PC0... This port selection is done by specifying the port number into System Config registers. Signed-off-by: Maxime Coquelin Signed-off-by: Alexandre TORGUE Signed-off-by: Linus Walleij --- drivers/pinctrl/stm32/Kconfig | 1 + drivers/pinctrl/stm32/pinctrl-stm32.c | 163 +++++++++++++++++++++++++++++++++- 2 files changed, 163 insertions(+), 1 deletion(-) diff --git a/drivers/pinctrl/stm32/Kconfig b/drivers/pinctrl/stm32/Kconfig index 4c40dae384d1..24bc68308af2 100644 --- a/drivers/pinctrl/stm32/Kconfig +++ b/drivers/pinctrl/stm32/Kconfig @@ -6,6 +6,7 @@ config PINCTRL_STM32 select PINMUX select GENERIC_PINCONF select GPIOLIB + select MFD_SYSCON config PINCTRL_STM32F429 bool "STMicroelectronics STM32F429 pin control" if COMPILE_TEST && !MACH_STM32F429 diff --git a/drivers/pinctrl/stm32/pinctrl-stm32.c b/drivers/pinctrl/stm32/pinctrl-stm32.c index 4ae596bf19b5..4f01025a0941 100644 --- a/drivers/pinctrl/stm32/pinctrl-stm32.c +++ b/drivers/pinctrl/stm32/pinctrl-stm32.c @@ -8,6 +8,8 @@ #include #include #include +#include +#include #include #include #include @@ -20,6 +22,7 @@ #include #include #include +#include #include #include @@ -40,6 +43,7 @@ #define STM32_GPIO_AFRH 0x24 #define STM32_GPIO_PINS_PER_BANK 16 +#define STM32_GPIO_IRQ_LINE 16 #define gpio_range_to_bank(chip) \ container_of(chip, struct stm32_gpio_bank, range) @@ -65,6 +69,8 @@ struct stm32_gpio_bank { spinlock_t lock; struct gpio_chip gpio_chip; struct pinctrl_gpio_range range; + struct fwnode_handle *fwnode; + struct irq_domain *domain; }; struct stm32_pinctrl { @@ -77,6 +83,9 @@ struct stm32_pinctrl { struct stm32_gpio_bank *banks; unsigned nbanks; const struct stm32_pinctrl_match_data *match_data; + struct irq_domain *domain; + struct regmap *regmap; + struct regmap_field *irqmux[STM32_GPIO_PINS_PER_BANK]; }; static inline int stm32_gpio_pin(int gpio) @@ -174,6 +183,20 @@ static int stm32_gpio_direction_output(struct gpio_chip *chip, return 0; } + +static int stm32_gpio_to_irq(struct gpio_chip *chip, unsigned int offset) +{ + struct stm32_gpio_bank *bank = gpiochip_get_data(chip); + struct irq_fwspec fwspec; + + fwspec.fwnode = bank->fwnode; + fwspec.param_count = 2; + fwspec.param[0] = offset; + fwspec.param[1] = IRQ_TYPE_NONE; + + return irq_create_fwspec_mapping(&fwspec); +} + static struct gpio_chip stm32_gpio_template = { .request = stm32_gpio_request, .free = stm32_gpio_free, @@ -181,10 +204,92 @@ static struct gpio_chip stm32_gpio_template = { .set = stm32_gpio_set, .direction_input = stm32_gpio_direction_input, .direction_output = stm32_gpio_direction_output, + .to_irq = stm32_gpio_to_irq, }; -/* Pinctrl functions */ +static struct irq_chip stm32_gpio_irq_chip = { + .name = "stm32gpio", + .irq_eoi = irq_chip_eoi_parent, + .irq_mask = irq_chip_mask_parent, + .irq_unmask = irq_chip_unmask_parent, + .irq_set_type = irq_chip_set_type_parent, +}; + +static int stm32_gpio_domain_translate(struct irq_domain *d, + struct irq_fwspec *fwspec, + unsigned long *hwirq, + unsigned int *type) +{ + if ((fwspec->param_count != 2) || + (fwspec->param[0] >= STM32_GPIO_IRQ_LINE)) + return -EINVAL; + + *hwirq = fwspec->param[0]; + *type = fwspec->param[1]; + return 0; +} +static void stm32_gpio_domain_activate(struct irq_domain *d, + struct irq_data *irq_data) +{ + struct stm32_gpio_bank *bank = d->host_data; + struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); + + regmap_field_write(pctl->irqmux[irq_data->hwirq], bank->range.id); +} + +static int stm32_gpio_domain_alloc(struct irq_domain *d, + unsigned int virq, + unsigned int nr_irqs, void *data) +{ + struct stm32_gpio_bank *bank = d->host_data; + struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); + struct irq_fwspec *fwspec = data; + struct irq_fwspec parent_fwspec; + irq_hw_number_t hwirq; + int ret; + + hwirq = fwspec->param[0]; + parent_fwspec.fwnode = d->parent->fwnode; + parent_fwspec.param_count = 2; + parent_fwspec.param[0] = fwspec->param[0]; + parent_fwspec.param[1] = fwspec->param[1]; + + irq_domain_set_hwirq_and_chip(d, virq, hwirq, &stm32_gpio_irq_chip, + bank); + + ret = gpiochip_lock_as_irq(&bank->gpio_chip, hwirq); + if (ret) { + dev_err(pctl->dev, "Unable to configure STM32 %s%ld as IRQ\n", + bank->gpio_chip.label, hwirq); + return ret; + } + + ret = irq_domain_alloc_irqs_parent(d, virq, nr_irqs, &parent_fwspec); + if (ret) + gpiochip_unlock_as_irq(&bank->gpio_chip, hwirq); + + return ret; +} + +static void stm32_gpio_domain_free(struct irq_domain *d, unsigned int virq, + unsigned int nr_irqs) +{ + struct stm32_gpio_bank *bank = d->host_data; + struct irq_data *data = irq_get_irq_data(virq); + + irq_domain_free_irqs_common(d, virq, nr_irqs); + gpiochip_unlock_as_irq(&bank->gpio_chip, data->hwirq); +} + +static const struct irq_domain_ops stm32_gpio_domain_ops = { + .translate = stm32_gpio_domain_translate, + .alloc = stm32_gpio_domain_alloc, + .free = stm32_gpio_domain_free, + .activate = stm32_gpio_domain_activate, +}; + +/* Pinctrl functions */ static struct stm32_pinctrl_group * stm32_pctrl_find_group_by_pin(struct stm32_pinctrl *pctl, u32 pin) { @@ -857,6 +962,17 @@ static int stm32_gpiolib_register_bank(struct stm32_pinctrl *pctl, range->pin_base = range->base = range->id * STM32_GPIO_PINS_PER_BANK; range->npins = bank->gpio_chip.ngpio; range->gc = &bank->gpio_chip; + + /* create irq hierarchical domain */ + bank->fwnode = of_node_to_fwnode(np); + + bank->domain = irq_domain_create_hierarchy(pctl->domain, 0, + STM32_GPIO_IRQ_LINE, bank->fwnode, + &stm32_gpio_domain_ops, bank); + + if (!bank->domain) + return -ENODEV; + err = gpiochip_add_data(&bank->gpio_chip, bank); if (err) { dev_err(dev, "Failed to add gpiochip(%d)!\n", bank_nr); @@ -867,6 +983,47 @@ static int stm32_gpiolib_register_bank(struct stm32_pinctrl *pctl, return 0; } +static int stm32_pctrl_dt_setup_irq(struct platform_device *pdev, + struct stm32_pinctrl *pctl) +{ + struct device_node *np = pdev->dev.of_node, *parent; + struct device *dev = &pdev->dev; + struct regmap *rm; + int offset, ret, i; + + parent = of_irq_find_parent(np); + if (!parent) + return -ENXIO; + + pctl->domain = irq_find_host(parent); + if (!pctl->domain) + return -ENXIO; + + pctl->regmap = syscon_regmap_lookup_by_phandle(np, "st,syscfg"); + if (IS_ERR(pctl->regmap)) + return PTR_ERR(pctl->regmap); + + rm = pctl->regmap; + + ret = of_property_read_u32_index(np, "st,syscfg", 1, &offset); + if (ret) + return ret; + + for (i = 0; i < STM32_GPIO_PINS_PER_BANK; i++) { + struct reg_field mux; + + mux.reg = offset + (i / 4) * 4; + mux.lsb = (i % 4) * 4; + mux.msb = mux.lsb + 3; + + pctl->irqmux[i] = devm_regmap_field_alloc(dev, rm, mux); + if (IS_ERR(pctl->irqmux[i])) + return PTR_ERR(pctl->irqmux[i]); + } + + return 0; +} + static int stm32_pctrl_build_state(struct platform_device *pdev) { struct stm32_pinctrl *pctl = platform_get_drvdata(pdev); @@ -935,6 +1092,10 @@ int stm32_pctl_probe(struct platform_device *pdev) return -EINVAL; } + ret = stm32_pctrl_dt_setup_irq(pdev, pctl); + if (ret) + return ret; + for_each_child_of_node(np, child) if (of_property_read_bool(child, "gpio-controller")) banks++; -- cgit 1.4.1 From e084448b5d26bfebe8a7b9c43bb57e685567563d Mon Sep 17 00:00:00 2001 From: "Agrawal, Nitesh-kumar" Date: Fri, 9 Sep 2016 15:18:09 +0000 Subject: pinctrl/amd: switch to using a bool for level The earlier patch can be simplified by using a bool to indicate level trigger. Reviewed-by: Pankaj Sen Signed-off-by: Nitesh Kumar Agrawal [Fixup to earlier manually applied patch] Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-amd.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/drivers/pinctrl/pinctrl-amd.c b/drivers/pinctrl/pinctrl-amd.c index 962746e6ab04..be8ae98871f5 100644 --- a/drivers/pinctrl/pinctrl-amd.c +++ b/drivers/pinctrl/pinctrl-amd.c @@ -403,7 +403,7 @@ static int amd_gpio_irq_set_type(struct irq_data *d, unsigned int type) int ret = 0; u32 pin_reg; unsigned long flags; - u32 level_trig; + bool level_trig; u32 active_level; struct gpio_chip *gc = irq_data_get_irq_chip_data(d); struct amd_gpio *gpio_dev = gpiochip_get_data(gc); @@ -416,13 +416,12 @@ static int amd_gpio_irq_set_type(struct irq_data *d, unsigned int type) * default settings, ignore incoming settings from client and use * BIOS settings to configure GPIO register. */ - level_trig = pin_reg & (LEVEL_TRIGGER << LEVEL_TRIG_OFF); + level_trig = !(pin_reg & (LEVEL_TRIGGER << LEVEL_TRIG_OFF)); active_level = pin_reg & (ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); - if((!level_trig) && - ((active_level >> ACTIVE_LEVEL_OFF) == ACTIVE_HIGH)) { + if(level_trig && + ((active_level >> ACTIVE_LEVEL_OFF) == ACTIVE_HIGH)) type = IRQ_TYPE_EDGE_FALLING; - } switch (type & IRQ_TYPE_SENSE_MASK) { case IRQ_TYPE_EDGE_RISING: -- cgit 1.4.1 From d9048cdbc9ed3103eef95adfe29f6482d23b1316 Mon Sep 17 00:00:00 2001 From: Julia Lawall Date: Sun, 11 Sep 2016 14:14:40 +0200 Subject: pinctrl: stm32: constify gpio_chip structures These structures are only used to copy into other structures, so declare them as const. The semantic patch that makes this change is as follows: (http://coccinelle.lip6.fr/) // @r disable optional_qualifier@ identifier i; position p; @@ static struct gpio_chip i@p = { ... }; @ok@ identifier r.i; expression e; position p; @@ e = i@p; @bad@ position p != {r.p,ok.p}; identifier r.i; struct gpio_chip e; @@ e@i@p @depends on !bad disable optional_qualifier@ identifier r.i; @@ static +const struct gpio_chip i = { ... }; // Signed-off-by: Julia Lawall Signed-off-by: Linus Walleij --- drivers/pinctrl/stm32/pinctrl-stm32.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/stm32/pinctrl-stm32.c b/drivers/pinctrl/stm32/pinctrl-stm32.c index 4f01025a0941..200667f08c37 100644 --- a/drivers/pinctrl/stm32/pinctrl-stm32.c +++ b/drivers/pinctrl/stm32/pinctrl-stm32.c @@ -197,7 +197,7 @@ static int stm32_gpio_to_irq(struct gpio_chip *chip, unsigned int offset) return irq_create_fwspec_mapping(&fwspec); } -static struct gpio_chip stm32_gpio_template = { +static const struct gpio_chip stm32_gpio_template = { .request = stm32_gpio_request, .free = stm32_gpio_free, .get = stm32_gpio_get, -- cgit 1.4.1 From 03e9888f955cc0950a15713a93af8946c56a37bb Mon Sep 17 00:00:00 2001 From: Julia Lawall Date: Sun, 11 Sep 2016 14:14:39 +0200 Subject: pinctrl: mediatek: constify gpio_chip structures These structures are only used to copy into other structures, so declare them as const. The semantic patch that makes this change is as follows: (http://coccinelle.lip6.fr/) // @r disable optional_qualifier@ identifier i; position p; @@ static struct gpio_chip i@p = { ... }; @ok@ identifier r.i; expression e; position p; @@ e = i@p; @bad@ position p != {r.p,ok.p}; identifier r.i; struct gpio_chip e; @@ e@i@p @depends on !bad disable optional_qualifier@ identifier r.i; @@ static +const struct gpio_chip i = { ... }; // Signed-off-by: Julia Lawall Signed-off-by: Linus Walleij --- drivers/pinctrl/mediatek/pinctrl-mtk-common.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c index ba2b03dbfe3b..f9aef2ac03a1 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c @@ -1054,7 +1054,7 @@ static int mtk_gpio_set_debounce(struct gpio_chip *chip, unsigned offset, return 0; } -static struct gpio_chip mtk_gpio_chip = { +static const struct gpio_chip mtk_gpio_chip = { .owner = THIS_MODULE, .request = gpiochip_generic_request, .free = gpiochip_generic_free, -- cgit 1.4.1 From 55956035266d8f5d825f30add0d7af3850cca0ad Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Fri, 9 Sep 2016 11:26:50 +0200 Subject: pinctrl: aspeed: fix regmap error handling The newly added aspeed driver tries to check for a negative return value from a pinctrl function, but stores the intermediate value in a 'bool' variable, which cannot work: drivers/pinctrl/aspeed/pinctrl-aspeed.c: In function 'aspeed_sig_expr_set': drivers/pinctrl/aspeed/pinctrl-aspeed.c:192:11: error: comparison of constant '0' with boolean expression is always false [-Werror=bool-compare] This slightly reworks the logic to use an explicit comparison with zero before assigning to the temporary variable. Reported-by: Colin King Signed-off-by: Arnd Bergmann Acked-by: Joel Stanley Reviewed-by: Andrew Jeffery Signed-off-by: Linus Walleij --- drivers/pinctrl/aspeed/pinctrl-aspeed.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed.c b/drivers/pinctrl/aspeed/pinctrl-aspeed.c index 7d461fc30d3c..0391f9f13f3e 100644 --- a/drivers/pinctrl/aspeed/pinctrl-aspeed.c +++ b/drivers/pinctrl/aspeed/pinctrl-aspeed.c @@ -187,10 +187,10 @@ static bool aspeed_sig_expr_set(const struct aspeed_sig_expr *expr, continue; ret = regmap_update_bits(map, desc->reg, desc->mask, - pattern << __ffs(desc->mask)); + pattern << __ffs(desc->mask)) == 0; - if (ret < 0) - return false; + if (!ret) + return ret; } return aspeed_sig_expr_eval(expr, enable, map); -- cgit 1.4.1 From 9b5fb0ca5d512fc28369484a4d03d376d0b17e39 Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Sun, 11 Sep 2016 14:39:02 +0200 Subject: pinctrl: meson-gxbb: add the missing SDIO interrupt pin This adds the SDIO interrupt pin which can be used by sd_emmc_a. Signed-off-by: Martin Blumenstingl Suggested-by: Neil Armstrong Fixes: 29885a656511 ("pinctrl: meson-gxbb: add the pins for the SDIO/sd_emmc_a controller") Acked-by: Kevin Hilman Signed-off-by: Linus Walleij --- drivers/pinctrl/meson/pinctrl-meson-gxbb.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/pinctrl/meson/pinctrl-meson-gxbb.c b/drivers/pinctrl/meson/pinctrl-meson-gxbb.c index b4e2e9f15818..f115638e8699 100644 --- a/drivers/pinctrl/meson/pinctrl-meson-gxbb.c +++ b/drivers/pinctrl/meson/pinctrl-meson-gxbb.c @@ -169,6 +169,7 @@ static const unsigned int sdio_d2_pins[] = { PIN(GPIOX_2, EE_OFF) }; static const unsigned int sdio_d3_pins[] = { PIN(GPIOX_3, EE_OFF) }; static const unsigned int sdio_cmd_pins[] = { PIN(GPIOX_4, EE_OFF) }; static const unsigned int sdio_clk_pins[] = { PIN(GPIOX_5, EE_OFF) }; +static const unsigned int sdio_irq_pins[] = { PIN(GPIOX_7, EE_OFF) }; static const unsigned int uart_tx_a_pins[] = { PIN(GPIOX_12, EE_OFF) }; static const unsigned int uart_rx_a_pins[] = { PIN(GPIOX_13, EE_OFF) }; @@ -383,6 +384,7 @@ static struct meson_pmx_group meson_gxbb_periphs_groups[] = { GROUP(sdio_d3, 8, 2), GROUP(sdio_cmd, 8, 1), GROUP(sdio_clk, 8, 0), + GROUP(sdio_irq, 8, 11), GROUP(uart_tx_a, 4, 13), GROUP(uart_rx_a, 4, 12), GROUP(uart_cts_a, 4, 11), @@ -522,7 +524,7 @@ static const char * const sdcard_groups[] = { static const char * const sdio_groups[] = { "sdio_d0", "sdio_d1", "sdio_d2", "sdio_d3", - "sdio_cmd", "sdio_clk", + "sdio_cmd", "sdio_clk", "sdio_irq", }; static const char * const uart_a_groups[] = { -- cgit 1.4.1 From eb4ec68acf5ebb312d29840287e465d3d414b07e Mon Sep 17 00:00:00 2001 From: Deepak Date: Tue, 13 Sep 2016 12:43:04 +0530 Subject: driver: base: pinctrl: return error from pinctrl_bind_pins() strict pin controller returns -EINVAL in case of pin request which is already claimed by somebody else. Following is the sequence of calling pin_request() from pinctrl_bind_pins():- pinctrl_bind_pins()->pinctrl_select_state()->pinmux_enable_setting()-> pin_request() But pinctrl_bind_pins() only returns -EPROBE_DEFER which makes device driver probe successful even if the pin request is rejected by the pin controller subsystem. This commit modifies pinctrl_bind_pins() to return error if the pin is rejected by pin control subsystem. Signed-off-by: Deepak Das [Rewrote to be cleaner] Signed-off-by: Linus Walleij --- drivers/base/pinctrl.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/drivers/base/pinctrl.c b/drivers/base/pinctrl.c index 076297592754..5917b4b5fb99 100644 --- a/drivers/base/pinctrl.c +++ b/drivers/base/pinctrl.c @@ -91,9 +91,13 @@ cleanup_alloc: devm_kfree(dev, dev->pins); dev->pins = NULL; - /* Only return deferrals */ - if (ret != -EPROBE_DEFER) - ret = 0; + /* Return deferrals */ + if (ret == -EPROBE_DEFER) + return ret; + /* Return serious errors */ + if (ret == -EINVAL) + return ret; + /* We ignore errors like -ENOENT meaning no pinctrl state */ - return ret; + return 0; } -- cgit 1.4.1 From 905933af8924dc4e93aea5f9dadb61049b0c5325 Mon Sep 17 00:00:00 2001 From: Alexandre TORGUE Date: Tue, 13 Sep 2016 15:28:12 +0200 Subject: pinctrl: Fix "st,syscfg" definition for STM32 pinctrl "st,syscfg" entry was bad described. Signed-off-by: Alexandre TORGUE Signed-off-by: Linus Walleij --- Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt index a0eed99214b5..f9753c416974 100644 --- a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt @@ -16,7 +16,9 @@ Required properies: gpio-bank node (children). - interrupt-parent: phandle of the interrupt parent to which the external GPIO interrupts are forwarded to. - - st,syscfg: phandle of the syscfg node used for IRQ mux selection. + - st,syscfg: Should be phandle/offset pair. The phandle to the syscon node + which includes IRQ mux selection register, and the offset of the IRQ mux + selection register. - pins-are-numbered: Specify the subnodes are using numbered pinmux to specify pins. -- cgit 1.4.1 From 9a6caa13f85e8ed7f2079acd8fe01a8d11ab3413 Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Mon, 12 Sep 2016 09:36:33 +0200 Subject: pinctrl: sh-pfc: Add PORT_GP_24 helper macro This follows the style of existing PORT_GP_X macros and will be used by a follow-up patch for the r8a7791 SoC. Signed-off-by: Simon Horman Acked-by: Linus Walleij Signed-off-by: Geert Uytterhoeven --- drivers/pinctrl/sh-pfc/sh_pfc.h | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/sh-pfc/sh_pfc.h b/drivers/pinctrl/sh-pfc/sh_pfc.h index c24067edcec4..2345421103db 100644 --- a/drivers/pinctrl/sh-pfc/sh_pfc.h +++ b/drivers/pinctrl/sh-pfc/sh_pfc.h @@ -422,9 +422,13 @@ extern const struct sh_pfc_soc_info shx3_pinmux_info; PORT_GP_CFG_1(bank, 22, fn, sfx, cfg) #define PORT_GP_23(bank, fn, sfx) PORT_GP_CFG_23(bank, fn, sfx, 0) -#define PORT_GP_CFG_26(bank, fn, sfx, cfg) \ +#define PORT_GP_CFG_24(bank, fn, sfx, cfg) \ PORT_GP_CFG_23(bank, fn, sfx, cfg), \ - PORT_GP_CFG_1(bank, 23, fn, sfx, cfg), \ + PORT_GP_CFG_1(bank, 23, fn, sfx, cfg) +#define PORT_GP_24(bank, fn, sfx) PORT_GP_CFG_24(bank, fn, sfx, 0) + +#define PORT_GP_CFG_26(bank, fn, sfx, cfg) \ + PORT_GP_CFG_24(bank, fn, sfx, cfg), \ PORT_GP_CFG_1(bank, 24, fn, sfx, cfg), \ PORT_GP_CFG_1(bank, 25, fn, sfx, cfg) #define PORT_GP_26(bank, fn, sfx) PORT_GP_CFG_26(bank, fn, sfx, 0) -- cgit 1.4.1 From 0e1396f101da63c1ea3a1868d6e549f3ca20dd5b Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Mon, 12 Sep 2016 09:36:34 +0200 Subject: pinctrl: sh-pfc: r8a7791: Implement voltage switching for SDHI All the SHDIs can operate with either 3.3V or 1.8V signals, depending on negotiation with the card. Based on work by Wolfram Sang for the r8a7790. Signed-off-by: Simon Horman Acked-by: Wolfram Sang Acked-by: Linus Walleij Signed-off-by: Geert Uytterhoeven --- drivers/pinctrl/sh-pfc/pfc-r8a7791.c | 29 ++++++++++++++++++++++++++++- 1 file changed, 28 insertions(+), 1 deletion(-) diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7791.c b/drivers/pinctrl/sh-pfc/pfc-r8a7791.c index 0c1a60c9a844..7ca37c3019ab 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7791.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7791.c @@ -13,6 +13,10 @@ #include "sh_pfc.h" +/* + * Pins 0-23 assigned to GPIO bank 6 can be used for SD interfaces in + * which case they support both 3.3V and 1.8V signalling. + */ #define CPU_ALL_PORT(fn, sfx) \ PORT_GP_32(0, fn, sfx), \ PORT_GP_26(1, fn, sfx), \ @@ -20,7 +24,15 @@ PORT_GP_32(3, fn, sfx), \ PORT_GP_32(4, fn, sfx), \ PORT_GP_32(5, fn, sfx), \ - PORT_GP_32(6, fn, sfx), \ + PORT_GP_CFG_24(6, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \ + PORT_GP_1(6, 24, fn, sfx), \ + PORT_GP_1(6, 25, fn, sfx), \ + PORT_GP_1(6, 26, fn, sfx), \ + PORT_GP_1(6, 27, fn, sfx), \ + PORT_GP_1(6, 28, fn, sfx), \ + PORT_GP_1(6, 29, fn, sfx), \ + PORT_GP_1(6, 30, fn, sfx), \ + PORT_GP_1(6, 31, fn, sfx), \ PORT_GP_26(7, fn, sfx) enum { @@ -6404,9 +6416,24 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { { }, }; +static int r8a7791_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl) +{ + if (pin < RCAR_GP_PIN(6, 0) || pin > RCAR_GP_PIN(6, 23)) + return -EINVAL; + + *pocctrl = 0xe606008c; + + return 31 - (pin & 0x1f); +} + +static const struct sh_pfc_soc_operations r8a7791_pinmux_ops = { + .pin_to_pocctrl = r8a7791_pin_to_pocctrl, +}; + #ifdef CONFIG_PINCTRL_PFC_R8A7791 const struct sh_pfc_soc_info r8a7791_pinmux_info = { .name = "r8a77910_pfc", + .ops = &r8a7791_pinmux_ops, .unlock_reg = 0xe6060000, /* PMMR */ .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, -- cgit 1.4.1 From 77fd4136e58c642482f03d293d5717658a569b4b Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Mon, 12 Sep 2016 09:36:35 +0200 Subject: pinctrl: sh-pfc: r8a7794: Implement voltage switching for SDHI All the SHDIs can operate with either 3.3V or 1.8V signals, depending on negotiation with the card. Based on work by Wolfram Sang for the r8a7790. Signed-off-by: Simon Horman Acked-by: Wolfram Sang Acked-by: Linus Walleij Signed-off-by: Geert Uytterhoeven --- drivers/pinctrl/sh-pfc/pfc-r8a7794.c | 28 +++++++++++++++++++++++++++- 1 file changed, 27 insertions(+), 1 deletion(-) diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7794.c b/drivers/pinctrl/sh-pfc/pfc-r8a7794.c index 8bc2cf0c594e..ed734f560c84 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7794.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7794.c @@ -22,7 +22,9 @@ PORT_GP_32(3, fn, sfx), \ PORT_GP_32(4, fn, sfx), \ PORT_GP_28(5, fn, sfx), \ - PORT_GP_26(6, fn, sfx) + PORT_GP_CFG_24(6, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \ + PORT_GP_1(6, 24, fn, sfx), \ + PORT_GP_1(6, 25, fn, sfx) enum { PINMUX_RESERVED = 0, @@ -5160,8 +5162,32 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { { }, }; +static int r8a7794_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl) +{ + *pocctrl = 0xe606006c; + + switch (pin & 0x1f) { + case 6: return 23; + case 7: return 16; + case 14: return 15; + case 15: return 8; + case 0 ... 5: + case 8 ... 13: + return 22 - (pin & 0x1f); + case 16 ... 23: + return 47 - (pin & 0x1f); + } + + return -EINVAL; +} + +static const struct sh_pfc_soc_operations r8a7794_pinmux_ops = { + .pin_to_pocctrl = r8a7794_pin_to_pocctrl, +}; + const struct sh_pfc_soc_info r8a7794_pinmux_info = { .name = "r8a77940_pfc", + .ops = &r8a7794_pinmux_ops, .unlock_reg = 0xe6060000, /* PMMR */ .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, -- cgit 1.4.1 From 6812f19e17c1ac67774175023824bdcbe9a23674 Mon Sep 17 00:00:00 2001 From: Jerome Brunet Date: Tue, 13 Sep 2016 17:12:21 +0200 Subject: pinctrl: amlogic: gxbb: add spi nor pins Add EE domains pins for the SPI flash controller Acked-by: Kevin Hilman Signed-off-by: Jerome Brunet Signed-off-by: Linus Walleij --- drivers/pinctrl/meson/pinctrl-meson-gxbb.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/drivers/pinctrl/meson/pinctrl-meson-gxbb.c b/drivers/pinctrl/meson/pinctrl-meson-gxbb.c index f115638e8699..573901887cee 100644 --- a/drivers/pinctrl/meson/pinctrl-meson-gxbb.c +++ b/drivers/pinctrl/meson/pinctrl-meson-gxbb.c @@ -156,6 +156,11 @@ static const unsigned int emmc_clk_pins[] = { PIN(BOOT_8, EE_OFF) }; static const unsigned int emmc_cmd_pins[] = { PIN(BOOT_10, EE_OFF) }; static const unsigned int emmc_ds_pins[] = { PIN(BOOT_15, EE_OFF) }; +static const unsigned int nor_d_pins[] = { PIN(BOOT_11, EE_OFF) }; +static const unsigned int nor_q_pins[] = { PIN(BOOT_12, EE_OFF) }; +static const unsigned int nor_c_pins[] = { PIN(BOOT_13, EE_OFF) }; +static const unsigned int nor_cs_pins[] = { PIN(BOOT_15, EE_OFF) }; + static const unsigned int sdcard_d0_pins[] = { PIN(CARD_1, EE_OFF) }; static const unsigned int sdcard_d1_pins[] = { PIN(CARD_0, EE_OFF) }; static const unsigned int sdcard_d2_pins[] = { PIN(CARD_5, EE_OFF) }; @@ -430,6 +435,10 @@ static struct meson_pmx_group meson_gxbb_periphs_groups[] = { GROUP(emmc_clk, 4, 18), GROUP(emmc_cmd, 4, 19), GROUP(emmc_ds, 4, 31), + GROUP(nor_d, 5, 1), + GROUP(nor_q, 5, 3), + GROUP(nor_c, 5, 2), + GROUP(nor_cs, 5, 0), /* Bank CARD */ GROUP(sdcard_d1, 2, 14), @@ -517,6 +526,10 @@ static const char * const emmc_groups[] = { "emmc_nand_d07", "emmc_clk", "emmc_cmd", "emmc_ds", }; +static const char * const nor_groups[] = { + "nor_d", "nor_q", "nor_c", "nor_cs", +}; + static const char * const sdcard_groups[] = { "sdcard_d0", "sdcard_d1", "sdcard_d2", "sdcard_d3", "sdcard_cmd", "sdcard_clk", @@ -619,6 +632,7 @@ static const char * const pwm_ao_b_groups[] = { static struct meson_pmx_func meson_gxbb_periphs_functions[] = { FUNCTION(gpio_periphs), FUNCTION(emmc), + FUNCTION(nor), FUNCTION(sdcard), FUNCTION(sdio), FUNCTION(uart_a), -- cgit 1.4.1 From 49cf2f29acab4ab0f14ff0d574cd4d3a76bdce53 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Wed, 14 Sep 2016 12:13:06 +0200 Subject: pinctrl: stm32: add IRQ_DOMAIN_HIERARCHY dependency The newly added irqchip support for the stm32 pinctrl driver uses hierarchical IRQ domains as provided by the NVIC primary irqchip. This works great for any configuration that may be relevant on stm32, but when doing compile-testing (randconfig), we can enable it without NVIC or any other primary irqchip that enables IRQ_DOMAIN_HIERARCHY: drivers/pinctrl/stm32/pinctrl-stm32.c:212:13: error: 'irq_chip_eoi_parent' undeclared here (not in a function) drivers/pinctrl/stm32/pinctrl-stm32.c:213:20: error: 'irq_chip_mask_parent' undeclared here (not in a function) drivers/pinctrl/stm32/pinctrl-stm32.c:214:20: error: 'irq_chip_unmask_parent' undeclared here (not in a function) drivers/pinctrl/stm32/pinctrl-stm32.c:215:20: error: 'irq_chip_set_type_parent' undeclared here (not in a function) This adds a Kconfig dependency to limit compile-testing to configurations that have IRQ_DOMAIN_HIERARCHY already enabled. It's not obvious whether we should use 'depends on' or 'select' here, I think either one works, with 'depends on' being more intuitive, while 'select' would be less likely to cause dependency loops. Signed-off-by: Arnd Bergmann Fixes: 0eb9f683336d ("pinctrl: Add IRQ support to STM32 gpios") Signed-off-by: Linus Walleij --- drivers/pinctrl/stm32/Kconfig | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/stm32/Kconfig b/drivers/pinctrl/stm32/Kconfig index 24bc68308af2..c03dce7a22df 100644 --- a/drivers/pinctrl/stm32/Kconfig +++ b/drivers/pinctrl/stm32/Kconfig @@ -10,13 +10,13 @@ config PINCTRL_STM32 config PINCTRL_STM32F429 bool "STMicroelectronics STM32F429 pin control" if COMPILE_TEST && !MACH_STM32F429 - depends on OF + depends on OF && IRQ_DOMAIN_HIERARCHY default MACH_STM32F429 select PINCTRL_STM32 config PINCTRL_STM32F746 bool "STMicroelectronics STM32F746 pin control" if COMPILE_TEST && !MACH_STM32F746 - depends on OF + depends on OF && IRQ_DOMAIN_HIERARCHY default MACH_STM32F746 select PINCTRL_STM32 -- cgit 1.4.1 From cd1e3b01c7d30ce5e69cbd760e1edbd4d682c30d Mon Sep 17 00:00:00 2001 From: Jerome Brunet Date: Tue, 13 Sep 2016 17:12:22 +0200 Subject: pinctrl: amlogic: gxbb: add nand pins Add EE domains pins for the NAND flash controller. Even tough we have no driver for the NAND flash controller yet, we need to have these pins in pinctrl as the actual pin are shared with the spifc controller. The bootloader on the S905-P200 setup pinmux for the NAND controller so we need the kernel to properly deactivate this if necessary. Acked-by: Kevin Hilman Signed-off-by: Jerome Brunet Signed-off-by: Linus Walleij --- drivers/pinctrl/meson/pinctrl-meson-gxbb.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/drivers/pinctrl/meson/pinctrl-meson-gxbb.c b/drivers/pinctrl/meson/pinctrl-meson-gxbb.c index 573901887cee..b06cc12f2500 100644 --- a/drivers/pinctrl/meson/pinctrl-meson-gxbb.c +++ b/drivers/pinctrl/meson/pinctrl-meson-gxbb.c @@ -176,6 +176,15 @@ static const unsigned int sdio_cmd_pins[] = { PIN(GPIOX_4, EE_OFF) }; static const unsigned int sdio_clk_pins[] = { PIN(GPIOX_5, EE_OFF) }; static const unsigned int sdio_irq_pins[] = { PIN(GPIOX_7, EE_OFF) }; +static const unsigned int nand_ce0_pins[] = { PIN(BOOT_8, EE_OFF) }; +static const unsigned int nand_ce1_pins[] = { PIN(BOOT_9, EE_OFF) }; +static const unsigned int nand_rb0_pins[] = { PIN(BOOT_10, EE_OFF) }; +static const unsigned int nand_ale_pins[] = { PIN(BOOT_11, EE_OFF) }; +static const unsigned int nand_cle_pins[] = { PIN(BOOT_12, EE_OFF) }; +static const unsigned int nand_wen_clk_pins[] = { PIN(BOOT_13, EE_OFF) }; +static const unsigned int nand_ren_wr_pins[] = { PIN(BOOT_14, EE_OFF) }; +static const unsigned int nand_dqs_pins[] = { PIN(BOOT_15, EE_OFF) }; + static const unsigned int uart_tx_a_pins[] = { PIN(GPIOX_12, EE_OFF) }; static const unsigned int uart_rx_a_pins[] = { PIN(GPIOX_13, EE_OFF) }; static const unsigned int uart_cts_a_pins[] = { PIN(GPIOX_14, EE_OFF) }; @@ -439,6 +448,14 @@ static struct meson_pmx_group meson_gxbb_periphs_groups[] = { GROUP(nor_q, 5, 3), GROUP(nor_c, 5, 2), GROUP(nor_cs, 5, 0), + GROUP(nand_ce0, 4, 26), + GROUP(nand_ce1, 4, 27), + GROUP(nand_rb0, 4, 25), + GROUP(nand_ale, 4, 24), + GROUP(nand_cle, 4, 23), + GROUP(nand_wen_clk, 4, 22), + GROUP(nand_ren_wr, 4, 21), + GROUP(nand_dqs, 4, 20), /* Bank CARD */ GROUP(sdcard_d1, 2, 14), @@ -540,6 +557,11 @@ static const char * const sdio_groups[] = { "sdio_cmd", "sdio_clk", "sdio_irq", }; +static const char * const nand_groups[] = { + "nand_ce0", "nand_ce1", "nand_rb0", "nand_ale", "nand_cle", + "nand_wen_clk", "nand_ren_wr", "nand_dqs", +}; + static const char * const uart_a_groups[] = { "uart_tx_a", "uart_rx_a", "uart_cts_a", "uart_rts_a", }; @@ -635,6 +657,7 @@ static struct meson_pmx_func meson_gxbb_periphs_functions[] = { FUNCTION(nor), FUNCTION(sdcard), FUNCTION(sdio), + FUNCTION(nand), FUNCTION(uart_a), FUNCTION(uart_b), FUNCTION(uart_c), -- cgit 1.4.1 From 0ef823bee705a52372dfb3a9b4f3098bf9b6ae22 Mon Sep 17 00:00:00 2001 From: Jerome Brunet Date: Wed, 14 Sep 2016 11:45:28 +0200 Subject: pinctrl: amlogic: gxbb: add i2c pins Add EE domains pins for the i2c devices A,B,C Signed-off-by: Jerome Brunet Acked-by: Kevin Hilman Signed-off-by: Linus Walleij --- drivers/pinctrl/meson/pinctrl-meson-gxbb.c | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/drivers/pinctrl/meson/pinctrl-meson-gxbb.c b/drivers/pinctrl/meson/pinctrl-meson-gxbb.c index b06cc12f2500..c3928aa3fefa 100644 --- a/drivers/pinctrl/meson/pinctrl-meson-gxbb.c +++ b/drivers/pinctrl/meson/pinctrl-meson-gxbb.c @@ -200,6 +200,15 @@ static const unsigned int uart_rx_c_pins[] = { PIN(GPIOY_14, EE_OFF) }; static const unsigned int uart_cts_c_pins[] = { PIN(GPIOX_11, EE_OFF) }; static const unsigned int uart_rts_c_pins[] = { PIN(GPIOX_12, EE_OFF) }; +static const unsigned int i2c_sck_a_pins[] = { PIN(GPIODV_25, EE_OFF) }; +static const unsigned int i2c_sda_a_pins[] = { PIN(GPIODV_24, EE_OFF) }; + +static const unsigned int i2c_sck_b_pins[] = { PIN(GPIODV_27, EE_OFF) }; +static const unsigned int i2c_sda_b_pins[] = { PIN(GPIODV_26, EE_OFF) }; + +static const unsigned int i2c_sck_c_pins[] = { PIN(GPIODV_29, EE_OFF) }; +static const unsigned int i2c_sda_c_pins[] = { PIN(GPIODV_28, EE_OFF) }; + static const unsigned int eth_mdio_pins[] = { PIN(GPIOZ_0, EE_OFF) }; static const unsigned int eth_mdc_pins[] = { PIN(GPIOZ_1, EE_OFF) }; static const unsigned int eth_clk_rx_clk_pins[] = { PIN(GPIOZ_2, EE_OFF) }; @@ -438,6 +447,12 @@ static struct meson_pmx_group meson_gxbb_periphs_groups[] = { GROUP(uart_rts_b, 2, 26), GROUP(pwm_b, 3, 21), GROUP(pwm_d, 3, 20), + GROUP(i2c_sck_a, 7, 27), + GROUP(i2c_sda_a, 7, 26), + GROUP(i2c_sck_b, 7, 25), + GROUP(i2c_sda_b, 7, 24), + GROUP(i2c_sck_c, 7, 23), + GROUP(i2c_sda_c, 7, 22), /* Bank BOOT */ GROUP(emmc_nand_d07, 4, 30), @@ -574,6 +589,18 @@ static const char * const uart_c_groups[] = { "uart_tx_c", "uart_rx_c", "uart_cts_c", "uart_rts_c", }; +static const char * const i2c_a_groups[] = { + "i2c_sck_a", "i2c_sda_a", +}; + +static const char * const i2c_b_groups[] = { + "i2c_sck_b", "i2c_sda_b", +}; + +static const char * const i2c_c_groups[] = { + "i2c_sck_c", "i2c_sda_c", +}; + static const char * const eth_groups[] = { "eth_mdio", "eth_mdc", "eth_clk_rx_clk", "eth_rx_dv", "eth_rxd0", "eth_rxd1", "eth_rxd2", "eth_rxd3", @@ -661,6 +688,9 @@ static struct meson_pmx_func meson_gxbb_periphs_functions[] = { FUNCTION(uart_a), FUNCTION(uart_b), FUNCTION(uart_c), + FUNCTION(i2c_a), + FUNCTION(i2c_b), + FUNCTION(i2c_c), FUNCTION(eth), FUNCTION(pwm_a_x), FUNCTION(pwm_a_y), -- cgit 1.4.1 From 147e1468b2a36300595e2952a539a29394b4468c Mon Sep 17 00:00:00 2001 From: Peter Griffin Date: Wed, 14 Sep 2016 14:27:51 +0100 Subject: pinctrl: st: Remove STiH415/6 SoC pinctrl driver support. STiH415/6 SoC support is being removed from the kernel. This patch updates the ST pinctrl driver and removes references to these obsolete platforms. As some structures referenced by STiH407 based configuration were shared with STiH416 we update these names to match the remaining supported platform. Signed-off-by: Peter Griffin Cc: Cc: Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-st.c | 76 ++++++++------------------------------------ 1 file changed, 14 insertions(+), 62 deletions(-) diff --git a/drivers/pinctrl/pinctrl-st.c b/drivers/pinctrl/pinctrl-st.c index 2e5c545f5040..99da4cf91031 100644 --- a/drivers/pinctrl/pinctrl-st.c +++ b/drivers/pinctrl/pinctrl-st.c @@ -335,61 +335,25 @@ struct st_pinctrl { }; /* SOC specific data */ -/* STiH415 data */ -static const unsigned int stih415_input_delays[] = {0, 500, 1000, 1500}; -static const unsigned int stih415_output_delays[] = {0, 1000, 2000, 3000}; - -#define STIH415_PCTRL_COMMON_DATA \ - .rt_style = st_retime_style_packed, \ - .input_delays = stih415_input_delays, \ - .ninput_delays = ARRAY_SIZE(stih415_input_delays), \ - .output_delays = stih415_output_delays, \ - .noutput_delays = ARRAY_SIZE(stih415_output_delays) - -static const struct st_pctl_data stih415_sbc_data = { - STIH415_PCTRL_COMMON_DATA, - .alt = 0, .oe = 5, .pu = 7, .od = 9, .rt = 16, -}; - -static const struct st_pctl_data stih415_front_data = { - STIH415_PCTRL_COMMON_DATA, - .alt = 0, .oe = 8, .pu = 10, .od = 12, .rt = 16, -}; - -static const struct st_pctl_data stih415_rear_data = { - STIH415_PCTRL_COMMON_DATA, - .alt = 0, .oe = 6, .pu = 8, .od = 10, .rt = 38, -}; - -static const struct st_pctl_data stih415_left_data = { - STIH415_PCTRL_COMMON_DATA, - .alt = 0, .oe = 3, .pu = 4, .od = 5, .rt = 6, -}; - -static const struct st_pctl_data stih415_right_data = { - STIH415_PCTRL_COMMON_DATA, - .alt = 0, .oe = 5, .pu = 7, .od = 9, .rt = 11, -}; -/* STiH416 data */ -static const unsigned int stih416_delays[] = {0, 300, 500, 750, 1000, 1250, +static const unsigned int stih407_delays[] = {0, 300, 500, 750, 1000, 1250, 1500, 1750, 2000, 2250, 2500, 2750, 3000, 3250 }; -static const struct st_pctl_data stih416_data = { - .rt_style = st_retime_style_dedicated, - .input_delays = stih416_delays, - .ninput_delays = ARRAY_SIZE(stih416_delays), - .output_delays = stih416_delays, - .noutput_delays = ARRAY_SIZE(stih416_delays), +static const struct st_pctl_data stih407_data = { + .rt_style = st_retime_style_dedicated, + .input_delays = stih407_delays, + .ninput_delays = ARRAY_SIZE(stih407_delays), + .output_delays = stih407_delays, + .noutput_delays = ARRAY_SIZE(stih407_delays), .alt = 0, .oe = 40, .pu = 50, .od = 60, .rt = 100, }; static const struct st_pctl_data stih407_flashdata = { .rt_style = st_retime_style_none, - .input_delays = stih416_delays, - .ninput_delays = ARRAY_SIZE(stih416_delays), - .output_delays = stih416_delays, - .noutput_delays = ARRAY_SIZE(stih416_delays), + .input_delays = stih407_delays, + .ninput_delays = ARRAY_SIZE(stih407_delays), + .output_delays = stih407_delays, + .noutput_delays = ARRAY_SIZE(stih407_delays), .alt = 0, .oe = -1, /* Not Available */ .pu = -1, /* Not Available */ @@ -1562,21 +1526,9 @@ static int st_gpiolib_register_bank(struct st_pinctrl *info, } static const struct of_device_id st_pctl_of_match[] = { - { .compatible = "st,stih415-sbc-pinctrl", .data = &stih415_sbc_data }, - { .compatible = "st,stih415-rear-pinctrl", .data = &stih415_rear_data }, - { .compatible = "st,stih415-left-pinctrl", .data = &stih415_left_data }, - { .compatible = "st,stih415-right-pinctrl", - .data = &stih415_right_data }, - { .compatible = "st,stih415-front-pinctrl", - .data = &stih415_front_data }, - { .compatible = "st,stih416-sbc-pinctrl", .data = &stih416_data}, - { .compatible = "st,stih416-front-pinctrl", .data = &stih416_data}, - { .compatible = "st,stih416-rear-pinctrl", .data = &stih416_data}, - { .compatible = "st,stih416-fvdp-fe-pinctrl", .data = &stih416_data}, - { .compatible = "st,stih416-fvdp-lite-pinctrl", .data = &stih416_data}, - { .compatible = "st,stih407-sbc-pinctrl", .data = &stih416_data}, - { .compatible = "st,stih407-front-pinctrl", .data = &stih416_data}, - { .compatible = "st,stih407-rear-pinctrl", .data = &stih416_data}, + { .compatible = "st,stih407-sbc-pinctrl", .data = &stih407_data}, + { .compatible = "st,stih407-front-pinctrl", .data = &stih407_data}, + { .compatible = "st,stih407-rear-pinctrl", .data = &stih407_data}, { .compatible = "st,stih407-flash-pinctrl", .data = &stih407_flashdata}, { /* sentinel */ } }; -- cgit 1.4.1 From 07bc299b11617d54a948797270bbfe09ecc2f87a Mon Sep 17 00:00:00 2001 From: Peter Griffin Date: Wed, 14 Sep 2016 14:27:52 +0100 Subject: pinctrl: st: Remove obsolete platforms from pinctrl-st dt doc STiH415/6 SoC support is being removed from the kernel. This patch updates the ST pinctrl dt doc and removes references to these obsolete platforms. It also updates the dt example to the currently supported STiH407 platform. Signed-off-by: Peter Griffin Cc: Cc: Cc: Signed-off-by: Linus Walleij --- .../devicetree/bindings/pinctrl/pinctrl-st.txt | 33 +++++++++++----------- 1 file changed, 16 insertions(+), 17 deletions(-) diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-st.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-st.txt index e6cc5e8f6438..013c675b5b64 100644 --- a/Documentation/devicetree/bindings/pinctrl/pinctrl-st.txt +++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-st.txt @@ -30,8 +30,7 @@ Second type has a dedicated interrupt per gpio bank. Pin controller node: Required properties: -- compatible : should be "st,--pinctrl" - like st,stih415-sbc-pinctrl, st,stih415-front-pinctrl and so on. +- compatible : should be "st,stih407--pinctrl" - st,syscfg : Should be a phandle of the syscfg node. - st,retime-pin-mask : Should be mask to specify which pins can be retimed. If the property is not present, it is assumed that all the pins in the @@ -80,23 +79,23 @@ include/dt-bindings/interrupt-controller/irq.h Example: pin-controller-sbc { - #address-cells = <1>; - #size-cells = <1>; - compatible = "st,stih415-sbc-pinctrl"; - st,syscfg = <&syscfg_sbc>; - reg = <0xfe61f080 0x4>; - reg-names = "irqmux"; - interrupts = ; - interrupt-names = "irqmux"; - ranges = <0 0xfe610000 0x5000>; - - PIO0: gpio@fe610000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,stih407-sbc-pinctrl"; + st,syscfg = <&syscfg_sbc>; + reg = <0x0961f080 0x4>; + reg-names = "irqmux"; + interrupts = ; + interrupt-names = "irqmux"; + ranges = <0 0x09610000 0x6000>; + + pio0: gpio@09610000 { gpio-controller; - #gpio-cells = <2>; + #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; - reg = <0 0x100>; - st,bank-name = "PIO0"; + reg = <0x0 0x100>; + st,bank-name = "PIO0"; }; ... pin-functions nodes follow... @@ -166,7 +165,7 @@ pin-controller { sdhci0:sdhci@fe810000{ ... - interrupt-parent = <&PIO3>; + interrupt-parent = <&pio3>; #interrupt-cells = <2>; interrupts = <3 IRQ_TYPE_LEVEL_HIGH>; /* Interrupt line via PIO3-3 */ interrupt-names = "card-detect"; -- cgit 1.4.1 From 31ebe86d6ef5f3280705e7ac9ab366f60f4e699c Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Mon, 19 Sep 2016 10:17:32 +0200 Subject: pinctrl: nomadik: don't default-flag IRQs as falling There is no point in adding any default trigger for these GPIO interrupts: the device tree should contain all trigger information and the platforms using the driver boots exclusively from device tree. Also the boot log is nagging me to fix this: [ 0.771057] ------------[ cut here ]------------ [ 0.775695] WARNING: CPU: 0 PID: 1 at ../drivers/gpio/gpiolib.c:1622 _gpiochip_irqchip_add+0x138/0x160 [ 0.785034] /soc/gpio@8012e000: Ignoring 2 default trigger (...) [ 0.942962] gpio 8012e000.gpio: at address e08f8000 (etc ad nauseam) Suggested-by: Marc Zyngier Acked-by: Marc Zyngier Signed-off-by: Linus Walleij --- drivers/pinctrl/nomadik/pinctrl-nomadik.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/nomadik/pinctrl-nomadik.c b/drivers/pinctrl/nomadik/pinctrl-nomadik.c index 205fb399268a..d318ca055489 100644 --- a/drivers/pinctrl/nomadik/pinctrl-nomadik.c +++ b/drivers/pinctrl/nomadik/pinctrl-nomadik.c @@ -1177,7 +1177,7 @@ static int nmk_gpio_probe(struct platform_device *dev) irqchip, 0, handle_edge_irq, - IRQ_TYPE_EDGE_FALLING); + IRQ_TYPE_NONE); if (ret) { dev_err(&dev->dev, "could not add irqchip\n"); gpiochip_remove(&nmk_chip->chip); -- cgit 1.4.1 From 79b804cb6af4f128b2c53f0887c02537a7eb5824 Mon Sep 17 00:00:00 2001 From: Mika Westerberg Date: Tue, 20 Sep 2016 15:15:21 +0300 Subject: gpiolib: Make it possible to exclude GPIOs from IRQ domain When using GPIO irqchip helpers to setup irqchip for a gpiolib based driver, it is not possible to select which GPIOs to add to the IRQ domain. Instead it just adds all GPIOs which is not always desired. For example there might be GPIOs that for some reason cannot generated normal interrupts at all. To support this we add a flag irq_need_valid_mask to struct gpio_chip. When this flag is set the core allocates irq_valid_mask that holds one bit for each GPIO the chip has. By default all bits are set but drivers can manipulate this using set_bit() and clear_bit() accordingly. Then when gpiochip_irqchip_add() is called, this mask is checked and all GPIOs with bit is set are added to the IRQ domain created for the GPIO chip. Suggested-by: Linus Walleij Signed-off-by: Mika Westerberg Signed-off-by: Linus Walleij --- Documentation/gpio/driver.txt | 6 ++++ drivers/gpio/gpiolib.c | 66 +++++++++++++++++++++++++++++++++++++++++-- include/linux/gpio/driver.h | 6 ++++ 3 files changed, 75 insertions(+), 3 deletions(-) diff --git a/Documentation/gpio/driver.txt b/Documentation/gpio/driver.txt index 6cb35a78eff4..368d5a294d89 100644 --- a/Documentation/gpio/driver.txt +++ b/Documentation/gpio/driver.txt @@ -262,6 +262,12 @@ symbol: to the container using container_of(). (See Documentation/driver-model/design-patterns.txt) + If there is a need to exclude certain GPIOs from the IRQ domain, one can + set .irq_need_valid_mask of the gpiochip before gpiochip_add_data() is + called. This allocates .irq_valid_mask with as many bits set as there are + GPIOs in the chip. Drivers can exclude GPIOs by clearing bits from this + mask. The mask must be filled in before gpiochip_irqchip_add() is called. + * gpiochip_set_chained_irqchip(): sets up a chained irq handler for a gpio_chip from a parent IRQ and passes the struct gpio_chip* as handler data. (Notice handler data, since the irqchip data is likely used by the diff --git a/drivers/gpio/gpiolib.c b/drivers/gpio/gpiolib.c index 53ff25ac66d8..23be4daefeed 100644 --- a/drivers/gpio/gpiolib.c +++ b/drivers/gpio/gpiolib.c @@ -71,6 +71,8 @@ LIST_HEAD(gpio_devices); static void gpiochip_free_hogs(struct gpio_chip *chip); static void gpiochip_irqchip_remove(struct gpio_chip *gpiochip); +static int gpiochip_irqchip_init_valid_mask(struct gpio_chip *gpiochip); +static void gpiochip_irqchip_free_valid_mask(struct gpio_chip *gpiochip); static bool gpiolib_initialized; @@ -1167,6 +1169,10 @@ int gpiochip_add_data(struct gpio_chip *chip, void *data) if (status) goto err_remove_from_list; + status = gpiochip_irqchip_init_valid_mask(chip); + if (status) + goto err_remove_from_list; + status = of_gpiochip_add(chip); if (status) goto err_remove_chip; @@ -1192,6 +1198,7 @@ err_remove_chip: acpi_gpiochip_remove(chip); gpiochip_free_hogs(chip); of_gpiochip_remove(chip); + gpiochip_irqchip_free_valid_mask(chip); err_remove_from_list: spin_lock_irqsave(&gpio_lock, flags); list_del(&gdev->list); @@ -1401,6 +1408,40 @@ static struct gpio_chip *find_chip_by_name(const char *name) * The following is irqchip helper code for gpiochips. */ +static int gpiochip_irqchip_init_valid_mask(struct gpio_chip *gpiochip) +{ + int i; + + if (!gpiochip->irq_need_valid_mask) + return 0; + + gpiochip->irq_valid_mask = kcalloc(BITS_TO_LONGS(gpiochip->ngpio), + sizeof(long), GFP_KERNEL); + if (!gpiochip->irq_valid_mask) + return -ENOMEM; + + /* Assume by default all GPIOs are valid */ + for (i = 0; i < gpiochip->ngpio; i++) + set_bit(i, gpiochip->irq_valid_mask); + + return 0; +} + +static void gpiochip_irqchip_free_valid_mask(struct gpio_chip *gpiochip) +{ + kfree(gpiochip->irq_valid_mask); + gpiochip->irq_valid_mask = NULL; +} + +static bool gpiochip_irqchip_irq_valid(const struct gpio_chip *gpiochip, + unsigned int offset) +{ + /* No mask means all valid */ + if (likely(!gpiochip->irq_valid_mask)) + return true; + return test_bit(offset, gpiochip->irq_valid_mask); +} + /** * gpiochip_set_chained_irqchip() - sets a chained irqchip to a gpiochip * @gpiochip: the gpiochip to set the irqchip chain to @@ -1442,9 +1483,12 @@ void gpiochip_set_chained_irqchip(struct gpio_chip *gpiochip, } /* Set the parent IRQ for all affected IRQs */ - for (offset = 0; offset < gpiochip->ngpio; offset++) + for (offset = 0; offset < gpiochip->ngpio; offset++) { + if (!gpiochip_irqchip_irq_valid(gpiochip, offset)) + continue; irq_set_parent(irq_find_mapping(gpiochip->irqdomain, offset), parent_irq); + } } EXPORT_SYMBOL_GPL(gpiochip_set_chained_irqchip); @@ -1551,9 +1595,12 @@ static void gpiochip_irqchip_remove(struct gpio_chip *gpiochip) /* Remove all IRQ mappings and delete the domain */ if (gpiochip->irqdomain) { - for (offset = 0; offset < gpiochip->ngpio; offset++) + for (offset = 0; offset < gpiochip->ngpio; offset++) { + if (!gpiochip_irqchip_irq_valid(gpiochip, offset)) + continue; irq_dispose_mapping( irq_find_mapping(gpiochip->irqdomain, offset)); + } irq_domain_remove(gpiochip->irqdomain); } @@ -1562,6 +1609,8 @@ static void gpiochip_irqchip_remove(struct gpio_chip *gpiochip) gpiochip->irqchip->irq_release_resources = NULL; gpiochip->irqchip = NULL; } + + gpiochip_irqchip_free_valid_mask(gpiochip); } /** @@ -1597,6 +1646,7 @@ int _gpiochip_irqchip_add(struct gpio_chip *gpiochip, struct lock_class_key *lock_key) { struct device_node *of_node; + bool irq_base_set = false; unsigned int offset; unsigned irq_base = 0; @@ -1646,13 +1696,17 @@ int _gpiochip_irqchip_add(struct gpio_chip *gpiochip, * necessary to allocate descriptors for all IRQs. */ for (offset = 0; offset < gpiochip->ngpio; offset++) { + if (!gpiochip_irqchip_irq_valid(gpiochip, offset)) + continue; irq_base = irq_create_mapping(gpiochip->irqdomain, offset); - if (offset == 0) + if (!irq_base_set) { /* * Store the base into the gpiochip to be used when * unmapping the irqs. */ gpiochip->irq_base = irq_base; + irq_base_set = true; + } } acpi_gpiochip_request_interrupts(gpiochip); @@ -1664,6 +1718,12 @@ EXPORT_SYMBOL_GPL(_gpiochip_irqchip_add); #else /* CONFIG_GPIOLIB_IRQCHIP */ static void gpiochip_irqchip_remove(struct gpio_chip *gpiochip) {} +static inline int gpiochip_irqchip_init_valid_mask(struct gpio_chip *gpiochip) +{ + return 0; +} +static inline void gpiochip_irqchip_free_valid_mask(struct gpio_chip *gpiochip) +{ } #endif /* CONFIG_GPIOLIB_IRQCHIP */ diff --git a/include/linux/gpio/driver.h b/include/linux/gpio/driver.h index 50882e09289b..420b837f2aa7 100644 --- a/include/linux/gpio/driver.h +++ b/include/linux/gpio/driver.h @@ -112,6 +112,10 @@ enum single_ended_mode { * initialization, provided by GPIO driver * @irq_parent: GPIO IRQ chip parent/bank linux irq number, * provided by GPIO driver + * @irq_need_valid_mask: If set core allocates @irq_valid_mask with all + * bits set to one + * @irq_valid_mask: If not %NULL holds bitmask of GPIOs which are valid to + * be included in IRQ domain of the chip * @lock_key: per GPIO IRQ chip lockdep class * * A gpio_chip can help platforms abstract various sources of GPIOs so @@ -190,6 +194,8 @@ struct gpio_chip { irq_flow_handler_t irq_handler; unsigned int irq_default_type; int irq_parent; + bool irq_need_valid_mask; + unsigned long *irq_valid_mask; struct lock_class_key *lock_key; #endif -- cgit 1.4.1 From 47c950d1020226179d278297c85ba6a988ee398b Mon Sep 17 00:00:00 2001 From: Mika Westerberg Date: Tue, 20 Sep 2016 15:15:22 +0300 Subject: pinctrl: cherryview: Do not add all southwest and north GPIOs to IRQ domain It turns out that for north and southwest communities, they can only generate GPIO interrupts for lower 8 interrupts (IntSel value). The upper part (8-15) can only generate GPEs (General Purpose Events). Now the reason why EC events such as pressing hotkeys does not work if we mask all the interrupts is that in order to generate either interrupts or GPEs the INTMASK register must have that particular interrupt unmasked. In case of GPEs the CPU does not trigger normal interrupt (and thus the GPIO driver does not see it) but instead it causes SCI (System Control Interrupt) to be triggered with the GPE in question set. To make this all work as expected we only add those GPIOs to the IRQ domain that can actually generate interrupts (IntSel value 0-7) and skip others. Signed-off-by: Mika Westerberg Signed-off-by: Linus Walleij --- drivers/pinctrl/intel/pinctrl-cherryview.c | 34 +++++++++++++++++++++++++++++- 1 file changed, 33 insertions(+), 1 deletion(-) diff --git a/drivers/pinctrl/intel/pinctrl-cherryview.c b/drivers/pinctrl/intel/pinctrl-cherryview.c index 0fe8fad25e4d..d23be3a2fb35 100644 --- a/drivers/pinctrl/intel/pinctrl-cherryview.c +++ b/drivers/pinctrl/intel/pinctrl-cherryview.c @@ -134,6 +134,7 @@ struct chv_gpio_pinrange { * @gpio_ranges: An array of GPIO ranges in this community * @ngpio_ranges: Number of GPIO ranges * @ngpios: Total number of GPIOs in this community + * @nirqs: Total number of IRQs this community can generate */ struct chv_community { const char *uid; @@ -146,6 +147,7 @@ struct chv_community { const struct chv_gpio_pinrange *gpio_ranges; size_t ngpio_ranges; size_t ngpios; + size_t nirqs; }; struct chv_pin_context { @@ -396,6 +398,12 @@ static const struct chv_community southwest_community = { .gpio_ranges = southwest_gpio_ranges, .ngpio_ranges = ARRAY_SIZE(southwest_gpio_ranges), .ngpios = ARRAY_SIZE(southwest_pins), + /* + * Southwest community can benerate GPIO interrupts only for the + * first 8 interrupts. The upper half (8-15) can only be used to + * trigger GPEs. + */ + .nirqs = 8, }; static const struct pinctrl_pin_desc north_pins[] = { @@ -479,6 +487,12 @@ static const struct chv_community north_community = { .gpio_ranges = north_gpio_ranges, .ngpio_ranges = ARRAY_SIZE(north_gpio_ranges), .ngpios = ARRAY_SIZE(north_pins), + /* + * North community can benerate GPIO interrupts only for the first + * 8 interrupts. The upper half (8-15) can only be used to trigger + * GPEs. + */ + .nirqs = 8, }; static const struct pinctrl_pin_desc east_pins[] = { @@ -521,6 +535,7 @@ static const struct chv_community east_community = { .gpio_ranges = east_gpio_ranges, .ngpio_ranges = ARRAY_SIZE(east_gpio_ranges), .ngpios = ARRAY_SIZE(east_pins), + .nirqs = 16, }; static const struct pinctrl_pin_desc southeast_pins[] = { @@ -646,6 +661,7 @@ static const struct chv_community southeast_community = { .gpio_ranges = southeast_gpio_ranges, .ngpio_ranges = ARRAY_SIZE(southeast_gpio_ranges), .ngpios = ARRAY_SIZE(southeast_pins), + .nirqs = 16, }; static const struct chv_community *chv_communities[] = { @@ -1497,7 +1513,7 @@ static void chv_gpio_irq_handler(struct irq_desc *desc) chained_irq_enter(chip, desc); pending = readl(pctrl->regs + CHV_INTSTAT); - for_each_set_bit(intr_line, &pending, 16) { + for_each_set_bit(intr_line, &pending, pctrl->community->nirqs) { unsigned irq, offset; offset = pctrl->intr_lines[intr_line]; @@ -1520,6 +1536,7 @@ static int chv_gpio_probe(struct chv_pinctrl *pctrl, int irq) chip->label = dev_name(pctrl->dev); chip->parent = pctrl->dev; chip->base = -1; + chip->irq_need_valid_mask = true; ret = gpiochip_add_data(chip, pctrl); if (ret) { @@ -1539,6 +1556,21 @@ static int chv_gpio_probe(struct chv_pinctrl *pctrl, int irq) offset += range->npins; } + /* Do not add GPIOs that can only generate GPEs to the IRQ domain */ + for (i = 0; i < pctrl->community->npins; i++) { + const struct pinctrl_pin_desc *desc; + u32 intsel; + + desc = &pctrl->community->pins[i]; + + intsel = readl(chv_padreg(pctrl, desc->number, CHV_PADCTRL0)); + intsel &= CHV_PADCTRL0_INTSEL_MASK; + intsel >>= CHV_PADCTRL0_INTSEL_SHIFT; + + if (intsel >= pctrl->community->nirqs) + clear_bit(i, chip->irq_valid_mask); + } + /* Clear all interrupts */ chv_writel(0xffff, pctrl->regs + CHV_INTSTAT); -- cgit 1.4.1 From d1073418d952f6a3557a888ffd666cc8c21362b1 Mon Sep 17 00:00:00 2001 From: Mika Westerberg Date: Tue, 20 Sep 2016 15:15:23 +0300 Subject: pinctrl: cherryview: Convert to use devm_gpiochip_add_data() This simplifies the error handling and allows us to drop the whole chv_pinctrl_remove() function. Signed-off-by: Mika Westerberg Signed-off-by: Linus Walleij --- drivers/pinctrl/intel/pinctrl-cherryview.c | 21 +++------------------ 1 file changed, 3 insertions(+), 18 deletions(-) diff --git a/drivers/pinctrl/intel/pinctrl-cherryview.c b/drivers/pinctrl/intel/pinctrl-cherryview.c index d23be3a2fb35..30389f4ccab4 100644 --- a/drivers/pinctrl/intel/pinctrl-cherryview.c +++ b/drivers/pinctrl/intel/pinctrl-cherryview.c @@ -1538,7 +1538,7 @@ static int chv_gpio_probe(struct chv_pinctrl *pctrl, int irq) chip->base = -1; chip->irq_need_valid_mask = true; - ret = gpiochip_add_data(chip, pctrl); + ret = devm_gpiochip_add_data(pctrl->dev, chip, pctrl); if (ret) { dev_err(pctrl->dev, "Failed to register gpiochip\n"); return ret; @@ -1550,7 +1550,7 @@ static int chv_gpio_probe(struct chv_pinctrl *pctrl, int irq) range->base, range->npins); if (ret) { dev_err(pctrl->dev, "failed to add GPIO pin range\n"); - goto fail; + return ret; } offset += range->npins; @@ -1578,17 +1578,12 @@ static int chv_gpio_probe(struct chv_pinctrl *pctrl, int irq) handle_bad_irq, IRQ_TYPE_NONE); if (ret) { dev_err(pctrl->dev, "failed to add IRQ chip\n"); - goto fail; + return ret; } gpiochip_set_chained_irqchip(chip, &chv_gpio_irqchip, irq, chv_gpio_irq_handler); return 0; - -fail: - gpiochip_remove(chip); - - return ret; } static int chv_pinctrl_probe(struct platform_device *pdev) @@ -1656,15 +1651,6 @@ static int chv_pinctrl_probe(struct platform_device *pdev) return 0; } -static int chv_pinctrl_remove(struct platform_device *pdev) -{ - struct chv_pinctrl *pctrl = platform_get_drvdata(pdev); - - gpiochip_remove(&pctrl->chip); - - return 0; -} - #ifdef CONFIG_PM_SLEEP static int chv_pinctrl_suspend(struct device *dev) { @@ -1761,7 +1747,6 @@ MODULE_DEVICE_TABLE(acpi, chv_pinctrl_acpi_match); static struct platform_driver chv_pinctrl_driver = { .probe = chv_pinctrl_probe, - .remove = chv_pinctrl_remove, .driver = { .name = "cherryview-pinctrl", .pm = &chv_pinctrl_pm_ops, -- cgit 1.4.1 From 01dabe91b1fef93130207e1a04bdf0a092a9fb21 Mon Sep 17 00:00:00 2001 From: Nilesh Bacchewar Date: Wed, 21 Sep 2016 16:35:23 -0700 Subject: pinctrl: intel: Configure GPIO chip IRQ as wakeup interrupts On some Intel BXT platform, wake-up from suspend-to-idle on pressing power-button is not working. Its noticed that gpio-keys driver marking the second level IRQ/power-button as wake capable but Intel pintctrl driver is missing to mark GPIO chip/controller IRQ which first level IRQ as wake cable if its GPIO pin IRQ is wakeble. So, though the first level IRQ gets generated on power-button press, since it is not marked as wake capable resume/wake-up flow is not happening. Intel pintctrl/GPIO driver need to mark GPIO chip/controller IRQ (first level IRQ) as wake capable iff GPIO pin's IRQ (second level IRQ) is marked as wake cable. Changes in v2: - Add missing irq initialisation. Signed-off-by: Nilesh Bacchewar Reviewed-by: Mika Westerberg Signed-off-by: Linus Walleij --- drivers/pinctrl/intel/pinctrl-intel.c | 33 +++++---------------------------- 1 file changed, 5 insertions(+), 28 deletions(-) diff --git a/drivers/pinctrl/intel/pinctrl-intel.c b/drivers/pinctrl/intel/pinctrl-intel.c index 257cab129692..63387a40b973 100644 --- a/drivers/pinctrl/intel/pinctrl-intel.c +++ b/drivers/pinctrl/intel/pinctrl-intel.c @@ -86,6 +86,7 @@ struct intel_pinctrl_context { * @communities: All communities in this pin controller * @ncommunities: Number of communities in this pin controller * @context: Configuration saved over system sleep + * @irq: pinctrl/GPIO chip irq number */ struct intel_pinctrl { struct device *dev; @@ -97,6 +98,7 @@ struct intel_pinctrl { struct intel_community *communities; size_t ncommunities; struct intel_pinctrl_context context; + int irq; }; #define pin_to_padno(c, p) ((p) - (c)->pin_base) @@ -793,38 +795,12 @@ static int intel_gpio_irq_wake(struct irq_data *d, unsigned int on) { struct gpio_chip *gc = irq_data_get_irq_chip_data(d); struct intel_pinctrl *pctrl = gpiochip_get_data(gc); - const struct intel_community *community; unsigned pin = irqd_to_hwirq(d); - unsigned padno, gpp, gpp_offset; - unsigned long flags; - u32 gpe_en; - - community = intel_get_community(pctrl, pin); - if (!community) - return -EINVAL; - - raw_spin_lock_irqsave(&pctrl->lock, flags); - padno = pin_to_padno(community, pin); - gpp = padno / community->gpp_size; - gpp_offset = padno % community->gpp_size; - - /* Clear the existing wake status */ - writel(BIT(gpp_offset), community->regs + GPI_GPE_STS + gpp * 4); - - /* - * The controller will generate wake when GPE of the corresponding - * pad is enabled and it is not routed to SCI (GPIROUTSCI is not - * set). - */ - gpe_en = readl(community->regs + GPI_GPE_EN + gpp * 4); if (on) - gpe_en |= BIT(gpp_offset); + enable_irq_wake(pctrl->irq); else - gpe_en &= ~BIT(gpp_offset); - writel(gpe_en, community->regs + GPI_GPE_EN + gpp * 4); - - raw_spin_unlock_irqrestore(&pctrl->lock, flags); + disable_irq_wake(pctrl->irq); dev_dbg(pctrl->dev, "%sable wake for pin %u\n", on ? "en" : "dis", pin); return 0; @@ -905,6 +881,7 @@ static int intel_gpio_probe(struct intel_pinctrl *pctrl, int irq) pctrl->chip.label = dev_name(pctrl->dev); pctrl->chip.parent = pctrl->dev; pctrl->chip.base = -1; + pctrl->irq = irq; ret = gpiochip_add_data(&pctrl->chip, pctrl); if (ret) { -- cgit 1.4.1 From 6bcf3f63394b9c4f133e4499349d786d7f531473 Mon Sep 17 00:00:00 2001 From: John Crispin Date: Mon, 12 Sep 2016 11:36:55 +0200 Subject: pinctrl: qcom: fix masking of pinmux functions The following commit introduced a regression by not properly masking the calculated value. Fixes: 47a01ee9a6c3 ("pinctrl: qcom: Clear all function selection bits") Signed-off-by: John Crispin Reviewed-by: Bjorn Andersson Reviewed-by: Stephen Boyd Signed-off-by: Linus Walleij --- drivers/pinctrl/qcom/pinctrl-msm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c index 51c42d746883..775c88303017 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm.c +++ b/drivers/pinctrl/qcom/pinctrl-msm.c @@ -156,7 +156,7 @@ static int msm_pinmux_set_mux(struct pinctrl_dev *pctldev, spin_lock_irqsave(&pctrl->lock, flags); val = readl(pctrl->regs + g->ctl_reg); - val &= mask; + val &= ~mask; val |= i << g->mux_bit; writel(val, pctrl->regs + g->ctl_reg); -- cgit 1.4.1