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2023-07-19arm64: dts: mediatek: mt8192: Fix CPUs capacity-dmips-mhzNícolas F. R. A. Prado
[ Upstream commit a4366b5695c984b8a3fc8b31de9e758c8f6d1aed ] The capacity-dmips-mhz parameter was miscalculated: this SoC runs the first (Cortex-A55) cluster at a maximum of 2000MHz and the second (Cortex-A76) cluster at a maximum of 2200MHz. In order to calculate the right capacity-dmips-mhz, the following test was performed: 1. CPUFREQ governor was set to 'performance' on both clusters 2. Ran dhrystone with 500000000 iterations for 10 times on each cluster 3. Calculated the mean result for each cluster 4. Calculated DMIPS/MHz: dmips_mhz = dmips_per_second / cpu_mhz 5. Scaled results to 1024: result_c0 = dmips_mhz_c0 / dmips_mhz_c1 * 1024 The mean results for this SoC are: Cluster 0 (LITTLE): 12016411 Dhry/s Cluster 1 (BIG): 31702034 Dhry/s The calculated scaled results are: Cluster 0: 426.953226899238 (rounded to 427) Cluster 1: 1024 Fixes: 48489980e27e ("arm64: dts: Add Mediatek SoC MT8192 and evaluation board dts and Makefile") Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20230602183515.3778780-1-nfraprado@collabora.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com> Signed-off-by: Sasha Levin <sashal@kernel.org>
2023-07-19arm64: dts: mediatek: Add cpufreq nodes for MT8192Allen-KH Cheng
[ Upstream commit 9d498cce9298a71e3896e2d1aee24a1a4c531d81 ] Add the cpufreq nodes for MT8192 SoC. Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com> Tested-by: Chen-Yu Tsai <wenst@chromium.org> Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Tested-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Tested-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20230317061944.15434-1-allen-kh.cheng@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com> Stable-dep-of: a4366b5695c9 ("arm64: dts: mediatek: mt8192: Fix CPUs capacity-dmips-mhz") Signed-off-by: Sasha Levin <sashal@kernel.org>
2023-07-19arm64: dts: mediatek: mt8183: Add mediatek,broken-save-restore-fw to kukuiDouglas Anderson
[ Upstream commit 42127f578ebde652d1373e0233356fbd351675c4 ] Firmware shipped on mt8183 Chromebooks is affected by the GICR save/restore issue as described by the patch ("dt-bindings: interrupt-controller: arm,gic-v3: Add quirk for Mediatek SoCs w/ broken FW"). Add the quirk property. Fixes: cd894e274b74 ("arm64: dts: mt8183: Add krane-sku176 board") Reviewed-by: Julius Werner <jwerner@chromium.org> Signed-off-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20230515131353.v2.3.I525a2ed4260046d43c885ee1275e91707743df1c@changeid Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com> Signed-off-by: Sasha Levin <sashal@kernel.org>
2023-05-11arm64: dts: mediatek: mt8192-asurada: Fix voltage constraint for VgpuAngeloGioacchino Del Regno
[ Upstream commit ff4c868ba8df9dcd144ab4943a50adca1cf33ba2 ] The MT8192 SoC specifies a maximum voltage for the GPU's digital supply of 0.88V and the GPU OPPs are declaring a maximum voltage of 0.80V. In order to keep the GPU voltage in the safe range, change the maximum voltage for mt6315@7's vbuck1 to 0.80V as sending, for any mistake, 1.193V would be catastrophic. Fixes: 3183cb62b033 ("arm64: dts: mediatek: asurada: Add SPMI regulators") Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Chen-yu Tsai <wenst@chromium.org> Tested-by: Chen-Yu Tsai <wenst@chromium.org> Link: https://lore.kernel.org/r/20230301095523.428461-12-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com> Signed-off-by: Sasha Levin <sashal@kernel.org>
2023-03-10arm64: dts: mediatek: mt7986: Fix watchdog compatibleAllen-KH Cheng
[ Upstream commit 70d24df30d06e5c822ba94751166ef55d0e28a89 ] MT7986's watchdog embeds a reset controller and needs only the mediatek,mt7986-wdt compatible string as the MT6589 one is there for watchdogs that don't have any reset controller capability. Fixes: 50137c150f5f ("arm64: dts: mediatek: add basic mt7986 support") Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Link: https://lore.kernel.org/r/20221108033209.22751-4-allen-kh.cheng@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com> Signed-off-by: Sasha Levin <sashal@kernel.org>
2023-03-10arm64: dts: mediatek: mt8195: Fix watchdog compatibleAngeloGioacchino Del Regno
[ Upstream commit 02938f460cde0d360dde48056c4d1c0a4bd49230 ] MT8195's watchdog embeds a reset controller and needs only the mediatek,mt8195-wdt compatible string as the MT6589 one is there for watchdogs that don't have any reset controller capability. Fixes: 37f2582883be ("arm64: dts: Add mediatek SoC mt8195 and evaluation board") Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Co-developed-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com> Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Link: https://lore.kernel.org/r/20221108033209.22751-3-allen-kh.cheng@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com> Signed-off-by: Sasha Levin <sashal@kernel.org>
2023-03-10arm64: dts: mediatek: mt8186: Fix watchdog compatibleAngeloGioacchino Del Regno
[ Upstream commit e5e961628d696237ddc3d53d9d5ac11f43e0bf67 ] MT8186's watchdog embeds a reset controller and needs only the mediatek,mt8186-wdt compatible string as the MT6589 one is there for watchdogs that don't have any reset controller capability. Fixes: 2e78620b1350 ("arm64: dts: Add MediaTek MT8186 dts and evaluation board and Makefile") Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Co-developed-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com> Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Link: https://lore.kernel.org/r/20221108033209.22751-2-allen-kh.cheng@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com> Signed-off-by: Sasha Levin <sashal@kernel.org>
2023-03-10arm64: dts: mediatek: mt7622: Add missing pwm-cells to pwm nodeAngeloGioacchino Del Regno
[ Upstream commit 22925af785fa3470efdf566339616d801119d348 ] Specify #pwm-cells on pwm@11006000 to make it actually usable. Fixes: ae457b7679c4 ("arm64: dts: mt7622: add SoC and peripheral related device nodes") Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20221128112028.58021-2-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com> Signed-off-by: Sasha Levin <sashal@kernel.org>
2023-03-10arm64: dts: mt8186: Fix CPU map for single-cluster SoCAngeloGioacchino Del Regno
[ Upstream commit 1c473804b0c8a68c6ef2cf519b38ec6725ca4aa5 ] MT8186 features the ARM DynamIQ technology and combines both two Cortex-A76 (big) and six Cortex-A55 (LITTLE) CPUs in one cluster: fix the CPU map to reflect that. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Fixes: 2e78620b1350 ("arm64: dts: Add MediaTek MT8186 dts and evaluation board and Makefile") Link: https://lore.kernel.org/r/20230126103526.417039-4-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com> Signed-off-by: Sasha Levin <sashal@kernel.org>
2023-03-10arm64: dts: mt8192: Fix CPU map for single-cluster SoCAngeloGioacchino Del Regno
[ Upstream commit 160ce54d635455ffb5e9b42c5ba9cb9aaa98cdb2 ] MT8192 features the ARM DynamIQ technology and combines both four Cortex-A76 (big) and four Cortex-A55 (LITTLE) CPUs in one cluster: fix the CPU map to reflect that. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Fixes: 48489980e27e ("arm64: dts: Add Mediatek SoC MT8192 and evaluation board dts and Makefile") Link: https://lore.kernel.org/r/20230126103526.417039-3-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com> Signed-off-by: Sasha Levin <sashal@kernel.org>
2023-03-10arm64: dts: mt8195: Fix CPU map for single-cluster SoCAngeloGioacchino Del Regno
[ Upstream commit cc4f0b13a887b483faa45084616998a21b63889d ] MT8195 features the ARM DynamIQ technology and combines both four Cortex-A78 (big) and four Cortex-A55 (LITTLE) CPUs in one cluster: fix the CPU map to reflect that. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Fixes: 37f2582883be ("arm64: dts: Add mediatek SoC mt8195 and evaluation board") Link: https://lore.kernel.org/r/20230126103526.417039-2-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com> Signed-off-by: Sasha Levin <sashal@kernel.org>
2023-03-10arm64: dts: mediatek: mt8192: Mark scp_adsp clock as brokenChen-Yu Tsai
[ Upstream commit 089cd717e6ef03cf9cf7865777d67775de41339b ] The scp_adsp clock controller is under the SCP_ADSP power domain. This power domain is currently not supported nor defined. Mark the clock controller as broken for now, to avoid the system from trying to access it, and causing the CPU or bus to stall. Fixes: 5d2b897bc6f5 ("arm64: dts: mediatek: Add mt8192 clock controllers") Signed-off-by: Chen-Yu Tsai <wenst@chromium.org> Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Tested-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Link: https://lore.kernel.org/r/20221229101202.1655924-1-wenst@chromium.org Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com> Signed-off-by: Sasha Levin <sashal@kernel.org>
2023-03-10arm64: dts: mediatek: mt8186: Fix systimer 13 MHz clock descriptionChen-Yu Tsai
[ Upstream commit b391efba57ff085233d5ead5e01817bf4b71d999 ] The systimer block derives its 13 MHz clock by dividing the main 26 MHz oscillator clock by 2 internally. The 13 MHz clock is not a separate oscillator. Fix this by making the 13 MHz clock a divide-by-2 fixed factor clock, taking its input from the main 26 MHz oscillator. Fixes: 2e78620b1350 ("arm64: dts: Add MediaTek MT8186 dts and evaluation board and Makefile") Signed-off-by: Chen-Yu Tsai <wenst@chromium.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20221201084229.3464449-5-wenst@chromium.org Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com> Signed-off-by: Sasha Levin <sashal@kernel.org>
2023-03-10arm64: dts: mediatek: mt8195: Fix systimer 13 MHz clock descriptionChen-Yu Tsai
[ Upstream commit 0f1c806b65d136a5fe0b88adad5ff1cb451fc401 ] The systimer block derives its 13 MHz clock by dividing the main 26 MHz oscillator clock by 2 internally, not through the TOPCKGEN clock controller. On the MT8195 this divider is set either by power-on-reset or by the bootloader. The bootloader may then make the divider unconfigurable to, but can be read out by, the operating system. Making the systimer block take the 26 MHz clock directly requires changing the implementations. As an ABI compatible fix, change the input clock of the systimer block a fixed factor divide-by-2 clock that takes the 26 MHz oscillator as its input. Fixes: 37f2582883be ("arm64: dts: Add mediatek SoC mt8195 and evaluation board") Signed-off-by: Chen-Yu Tsai <wenst@chromium.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20221201084229.3464449-4-wenst@chromium.org Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com> Signed-off-by: Sasha Levin <sashal@kernel.org>
2023-03-10arm64: dts: mediatek: mt8192: Fix systimer 13 MHz clock descriptionChen-Yu Tsai
[ Upstream commit f19f68e56b0c6631984a9f5023035d4bd09612bb ] The systimer block derives its 13 MHz clock by dividing the main 26 MHz oscillator clock by 2 internally, not through the TOPCKGEN clock controller. On the MT8192 this divider is fixed to /2 and is not configurable. Making the systimer block take the 26 MHz clock directly requires changing the implementations. As an ABI compatible fix, change the input clock of the systimer block a fixed factor divide-by-2 clock that takes the 26 MHz oscillator as its input. Fixes: 48489980e27e ("arm64: dts: Add Mediatek SoC MT8192 and evaluation board dts and Makefile") Signed-off-by: Chen-Yu Tsai <wenst@chromium.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20221201084229.3464449-3-wenst@chromium.org Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com> Signed-off-by: Sasha Levin <sashal@kernel.org>
2023-03-10arm64: dts: mediatek: mt8183: Fix systimer 13 MHz clock descriptionChen-Yu Tsai
[ Upstream commit ce8a06b5bac75ccce99c0cf91b96b767d64f28a7 ] The systimer block derives its 13 MHz clock by dividing the main 26 MHz oscillator clock by 2 internally, not through the TOPCKGEN clock controller. On the MT8183 this divider is set either by power-on-reset or by the bootloader. The bootloader may then make the divider unconfigurable to, but can be read out by, the operating system. Making the systimer block take the 26 MHz clock directly requires changing the implementations. As an ABI compatible fix, change the input clock of the systimer block a fixed factor divide-by-2 clock that takes the 26 MHz oscillator as its input. Fixes: 5bc8e2875ffb ("arm64: dts: mt8183: add systimer0 device node") Signed-off-by: Chen-Yu Tsai <wenst@chromium.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20221201084229.3464449-2-wenst@chromium.org Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com> Signed-off-by: Sasha Levin <sashal@kernel.org>
2023-03-10arm64: dts: mediatek: mt8195: Add power domain to U3PHY1 T-PHYAngeloGioacchino Del Regno
[ Upstream commit a9f6721a3c92764582ed12296292fda4a7f2dd25 ] Assign power domain to the U3PHY1 T-PHY in otder to keep this PHY alive after unused PD shutdown and to be able to completely cut and restore power to it, for example, to save some power during system suspend/sleep. Fixes: 2b515194bf0c ("arm64: dts: mt8195: Add power domains controller") Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20221214131117.108008-2-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com> Signed-off-by: Sasha Levin <sashal@kernel.org>
2023-02-14arm64: dts: mediatek: mt8195: Fix vdosys* compatible stringsChen-Yu Tsai
[ Upstream commit 97801cfcf9565247bcc53b67ea47fa87b1704375 ] When vdosys1 was initially added, it was incorrectly assumed to be compatible with vdosys0, and thus both had the same mt8195-mmsys compatible attached. This has since been corrected in commit b237efd47df7 ("dt-bindings: arm: mediatek: mmsys: change compatible for MT8195") and commit 82219cfbef18 ("dt-bindings: arm: mediatek: mmsys: add vdosys1 compatible for MT8195"). The device tree needs to be fixed as well, otherwise the vdosys1 block fails to work, and causes its dependent power domain controller to not work either. Change the compatible string of vdosys1 to "mediatek,mt8195-vdosys1". While at it, also add the new "mediatek,mt8195-vdosys0" compatible to vdosys0. Fixes: 6aa5b46d1755 ("arm64: dts: mt8195: Add vdosys and vppsys clock nodes") Signed-off-by: Chen-Yu Tsai <wenst@chromium.org> Tested-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Acked-by: Matthias Brugger <matthias.bgg@gmail.com> Link: https://lore.kernel.org/r/20230202104014.2931517-1-wenst@chromium.org Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Sasha Levin <sashal@kernel.org>
2023-01-07arm64: dts: mediatek: mt8195-demo: fix the memory size of node secmonMacpaul Lin
commit e4a4175201014c0222f6bab1895a17b3d1b92f08 upstream. The size of device tree node secmon (bl31_secmon_reserved) was incorrect. It should be increased to 2MiB (0x200000). The origin setting will cause some abnormal behavior due to trusted-firmware-a and related firmware didn't load correctly. The incorrect behavior may vary because of different software stacks. For example, it will cause build error in some Yocto project because it will check if there was enough memory to load trusted-firmware-a to the reserved memory. When mt8195-demo.dts sent to the upstream, at that time the size of BL31 was small. Because supported functions and modules in BL31 are basic sets when the board was under early development stage. Now BL31 includes more firmwares of coprocessors and maturer functions so the size has grown bigger in real applications. According to the value reported by customers, we think reserved 2MiB for BL31 might be enough for maybe the following 2 or 3 years. Cc: stable@vger.kernel.org # v5.19 Fixes: 6147314aeedc ("arm64: dts: mediatek: Add device-tree for MT8195 Demo board") Signed-off-by: Macpaul Lin <macpaul.lin@mediatek.com> Reviewed-by: Miles Chen <miles.chen@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20221111095540.28881-1-macpaul.lin@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2022-12-31arm64: dts: mt8183: Fix Mali GPU clockChen-Yu Tsai
[ Upstream commit ad2631b5645a1d0ca9bf6fecf71f77e3b0071ee5 ] The actual clock feeding into the Mali GPU on the MT8183 is from the clock gate in the MFGCFG block, not CLK_TOP_MFGPLL_CK from the TOPCKGEN block, which itself is simply a pass-through placeholder for the MFGPLL in the APMIXEDSYS block. Fix the hardware description with the correct clock reference. Fixes: a8168cebf1bc ("arm64: dts: mt8183: Add node for the Mali GPU") Signed-off-by: Chen-Yu Tsai <wenst@chromium.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Tested-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Link: https://lore.kernel.org/r/20220927101128.44758-2-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com> Signed-off-by: Sasha Levin <sashal@kernel.org>
2022-12-31arm64: dts: mt7986: move wed_pcie nodeFrank Wunderlich
[ Upstream commit 99cce13b82a9366cfdd230ba6ddb48ba30d2741f ] Move the wed_pcie node to have node aligned by address. Fixes: 00b9903996b3 ("arm64: dts: mediatek: mt7986: add support for Wireless Ethernet Dispatch") Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20221118190126.100895-2-linux@fw-web.de Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com> Signed-off-by: Sasha Levin <sashal@kernel.org>
2022-12-31arm64: dts: mediatek: mt6797: Fix 26M oscillator unit nameAngeloGioacchino Del Regno
[ Upstream commit 5f535cc583759c9c60d4cc9b8d221762e2d75387 ] Update its unit name to oscillator-26m and remove the unneeded unit address to fix a unit_address_vs_reg warning. Fixes: 464c510f60c6 ("arm64: dts: mediatek: add mt6797 support") Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20221013152212.416661-9-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com> Signed-off-by: Sasha Levin <sashal@kernel.org>
2022-12-31arm64: dts: mediatek: pumpkin-common: Fix devicetree warningsAngeloGioacchino Del Regno
[ Upstream commit 509438336ce75c8b4e6ce8e8d507dc77d0783bdd ] Fix the pinctrl submodes and optee node to remove unneeded unit address, fixing all unit_address_vs_reg warnings. Fixes: 9983822c8cf9 ("arm64: dts: mediatek: add pumpkin board dts") Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20221013152212.416661-8-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com> Signed-off-by: Sasha Levin <sashal@kernel.org>
2022-12-31arm64: dts: mt2712-evb: Fix usb vbus regulators unit namesAngeloGioacchino Del Regno
[ Upstream commit ec1ae39a8d25cfb067b5459fac7c5b7b9bce6f6a ] Update the names to regulator-usb-p{0-3}-vbus to fix unit_address_vs_reg warnings for those. Fixes: 1724f4cc5133 ("arm64: dts: Add USB3 related nodes for MT2712") Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20221013152212.416661-7-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com> Signed-off-by: Sasha Levin <sashal@kernel.org>
2022-12-31arm64: dts: mt2712-evb: Fix vproc fixed regulators unit namesAngeloGioacchino Del Regno
[ Upstream commit 377063156893bf6c088309ac799fe5c6dce2822d ] Update the names to regulator-vproc-buck{0,1} to fix unit_addres_vs_reg warnings for those. Fixes: f75dd8bdd344 ("arm64: dts: mediatek: add mt2712 cpufreq related device nodes") Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20221013152212.416661-6-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com> Signed-off-by: Sasha Levin <sashal@kernel.org>
2022-12-31arm64: dts: mt2712e: Fix unit address for pinctrl nodeAngeloGioacchino Del Regno
[ Upstream commit 1d4516f53a611b362db7ba7a8889923d469f57e1 ] The unit address for the pinctrl node is (0x)1000b000 and not (0x)10005000, which is the syscfg_pctl_a address instead. This fixes the following warning: arch/arm64/boot/dts/mediatek/mt2712e.dtsi:264.40-267.4: Warning (unique_unit_address): /syscfg_pctl_a@10005000: duplicate unit-address (also used in node /pinctrl@10005000) Fixes: f0c64340b748 ("arm64: dts: mt2712: add pintcrl device node.") Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20221013152212.416661-5-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com> Signed-off-by: Sasha Levin <sashal@kernel.org>
2022-12-31arm64: dts: mt2712e: Fix unit_address_vs_reg warning for oscillatorsAngeloGioacchino Del Regno
[ Upstream commit e4495a0a8b3d84816c9a46edf3ce060bbf267475 ] Rename the fixed-clock oscillators to remove the unit address. This solves unit_address_vs_reg warnings. Fixes: 5d4839709c8e ("arm64: dts: mt2712: Add clock controller device nodes") Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20221013152212.416661-4-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com> Signed-off-by: Sasha Levin <sashal@kernel.org>
2022-12-31arm64: dts: mt6779: Fix devicetree build warningsAngeloGioacchino Del Regno
[ Upstream commit 4d759c524c15dc4151e40b9e3f368147fda7b789 ] Rename fixed-clock oscillators to oscillator-26m and oscillator-32k and remove the unit address to fix the unit_address_vs_reg warning; fix the unit address for interrupt and intpol controllers by removing a leading zero in their unit address. This commit fixes the following warnings: (unit_address_vs_reg): /oscillator@0: node has a unit name, but no reg or ranges property (unit_address_vs_reg): /oscillator@1: node has a unit name, but no reg or ranges property (simple_bus_reg): /soc/interrupt-controller@0c000000: simple-bus unit address format error, expected "c000000" (simple_bus_reg): /soc/intpol-controller@0c53a650: simple-bus unit address format error, expected "c53a650" Fixes: 4c7a6260775d ("arm64: dts: add dts nodes for MT6779") Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20221013152212.416661-3-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com> Signed-off-by: Sasha Levin <sashal@kernel.org>
2022-12-31arm64: dts: mt7896a: Fix unit_address_vs_reg warning for oscillatorAngeloGioacchino Del Regno
[ Upstream commit 7898d047b1eb2bec2622668cd70181442a580c6d ] Rename the oscillator fixed-clock to oscillator-40m and remove the unit address to fix warnings. arch/arm64/boot/dts/mediatek/mt7986a.dtsi:17.23-22.4: Warning (unit_address_vs_reg): /oscillator@0: node has a unit name, but no reg or ranges property Fixes: 1f9986b258c2 ("arm64: dts: mediatek: add clock support for mt7986a") Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20221013152212.416661-2-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com> Signed-off-by: Sasha Levin <sashal@kernel.org>
2022-12-31arm64: dts: mediatek: mt8195: Fix CPUs capacity-dmips-mhzAngeloGioacchino Del Regno
[ Upstream commit 513c43328b189874fdfee3ae99cac81e5502e7f7 ] The capacity-dmips-mhz parameter was miscalculated: this SoC runs the first (Cortex-A55) cluster at a maximum of 2000MHz and the second (Cortex-A78) cluster at a maximum of 3000MHz. In order to calculate the right capacity-dmips-mhz, the following test was performed: 1. CPUFREQ governor was set to 'performance' on both clusters 2. Ran dhrystone with 500000000 iterations for 10 times on each cluster 3. Calculate the mean result for each cluster 4. Calculate DMIPS/MHz: dmips_mhz = dmips_per_second / cpu_mhz 5. Scale results to 1024: result_c0 = (dmips_mhz_c0 - min_dmips_mhz(c0, c1)) / (max_dmips_mhz(c0, c1) - min_dmips_mhz(c0, c1)) * 1024 The mean results for this SoC are: Cluster 0 (LITTLE): 11990400 Dhry/s Cluster 1 (BIG): 59809036 Dhry/s The calculated scaled results are: Cluster 0: 307,934312801831 (rounded to 308) Cluster 1: 1024 Fixes: 37f2582883be ("arm64: dts: Add mediatek SoC mt8195 and evaluation board") Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20221005093404.33102-1-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com> Signed-off-by: Sasha Levin <sashal@kernel.org>
2022-12-31arm64: dts: mt7986: fix trng node nameFrank Wunderlich
[ Upstream commit 07ce611c705217507c2a036bba8695cbd82c9e36 ] Binding requires node name to be rng not trng: trng@1020f000: $nodename:0: 'trng@1020f000' does not match '^rng@[0-9a-f]+$' Fixes: 50137c150f5f ("arm64: dts: mediatek: add basic mt7986 support") Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20221027151022.5541-1-linux@fw-web.de Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com> Signed-off-by: Sasha Levin <sashal@kernel.org>
2022-10-06Merge tag 'arm-dt-6.1' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/socLinus Torvalds
Pull ARM devicetree updates from Arnd Bergmann: "Most of the changes fall into one of three categories: adding support for additional devices on existing machines, cleaning up issues found by the ongoing conversion to machine-readable bindings, and addressing minor mistakes in the existing DT data. Across SoC vendors, Qualcomm and Freescale stick out as getting the most updates, which corresponds to their dominance in the mobile phone and embedded industrial markets, respectively. There are 636 non-merge changeset in this branch, which is a little lower than most times, but more importantly we only add 36 machine files, which is about half of what we had the past few releases. Eight new SoCs are added, but all of them are variations of already supported SoC families, and most of them come with one reference board design from the SoC vendor: - Mediatek MT8186 is a Chromebook/Tablet type SoC, similar to the MT65xx series of phone SoCs, with two Cortex-A76 and six Cortex-A55 cores. - TI AM62A is another member of the K3 family with Cortex-A53 cores, this one is targetted at Video/Vision processing for industrial and automotive applications. - NXP i.MX8DXL is another chip for this market in the ever-growing i.MX8 family, this one again with two Cortex-A35 cores. - Renesas R-Car H3Ne-1.7G (R8A779MB) and R-Car V3H2 (R8A77980A) are minor updates of R8A77951 and R8A77980, respectively. - Qualcomm IPQ8064-v2.0, IPQ8062 and IPQ8065 are all variants of the IPQ8064 chip, with minimally different features. The AMD Pensando Elba and Apple M1 Ultra SoC support was getting close this time, but in the end did not make the cut. The new machines based on existing SoC support are fairly uneventful: - Sony Xperia 1 IV is a fairly recent phone based on Qualcomm Snapdragon 8 Gen 1. - Three Samsung phones based on Snapdragon 410: Galaxy E5, E7 and Grand Max. These are added for both 32-bit and 64-bit kernels, as they originally shipped running 32-bit code. - Two new servers using AST2600 BMCs: AMD DaytonaX and Ampere Mt. Mitchell - Three new machines based on Rockchips RK3399 and RK3566: Anberic RG353P and RG503, Pine64 Pinephone Pro, Open AI Lab - Multiple NXP i.MX6/i.MX8 based boards: Kontron SL/BL i.MX8MM OSM-S, i.MX8MM Gateworks GW7904, MSC SM2S-IMX8PLUS SoM and carrier board - Two development boards in the Microchip AT91 family: SAMA5D3-EDS and lan966x-pcb8290. - Minor variants of existing boards using Amlogic, Broadcom, Marvell, Rockchips, Freescale Layerscape and Socionext Uniphier SoCs" * tag 'arm-dt-6.1' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (617 commits) Revert "ARM: dts: BCM5301X: Add basic PCI controller properties" ARM: dts: s5pv210: correct double "pins" in pinmux node ARM: dts: exynos: fix polarity of VBUS GPIO of Origen arm64: dts: exynos: fix polarity of "enable" line of NFC chip in TM2 arm64: dts: uniphier: Add L2 cache node arm64: dts: uniphier: Remove compatible "snps,dw-pcie" from pcie node arm64: dts: uniphier: Fix opp-table node name for LD20 arm64: dts: uniphier: Add USB-device support for PXs3 reference board arm64: dts: uniphier: Add ahci controller nodes for PXs3 arm64: dts: uniphier: Use GIC interrupt definitions arm64: dts: uniphier: Rename gpio-hog nodes arm64: dts: uniphier: Rename usb-glue node for USB3 to usb-controller arm64: dts: uniphier: Rename usb-phy node for USB2 to usb-controller arm64: dts: uniphier: Rename pvtctl node to thermal-sensor ARM: dts: uniphier: Remove compatible "snps,dw-pcie-ep" from pcie-ep node ARM: dts: uniphier: Move interrupt-parent property to each child node in uniphier-support-card ARM: dts: uniphier: Add ahci controller nodes for PXs2 ARM: dts: uniphier: Add ahci controller nodes for Pro4 ARM: dts: uniphier: Use GIC interrupt definitions ARM: dts: uniphier: Rename gpio-hog node ...
2022-09-30arm64: dts: mediatek: mt2712e: Update the name of property 'clk_csr'Jianguo Zhang
Update the name of property 'clk_csr' as 'snps,clk-csr' to align with the property name in the binding file. Signed-off-by: Jianguo Zhang <jianguo.zhang@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2022-09-22arm64: dts: mediatek: mt7986: add support for Wireless Ethernet DispatchLorenzo Bianconi
Introduce wed0 and wed1 nodes in order to enable offloading forwarding between ethernet and wireless devices on the mt7986 chipset. Co-developed-by: Bo Jiao <Bo.Jiao@mediatek.com> Signed-off-by: Bo Jiao <Bo.Jiao@mediatek.com> Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org> Signed-off-by: Paolo Abeni <pabeni@redhat.com>
2022-09-15arm64: dts: mediatek: mt6795: Add CPUX system timer nodeAngeloGioacchino Del Regno
Add a node for mt6795-systimer: this is necessary to start the System Timer(s) for all cores, finally making CNTVCT_EL0 usable. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20220729093536.27623-1-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2022-09-14arm64: dts: mt7986: add built-in Wi-Fi device nodesPeter Chiu
This enables built-in 802.11ax Wi-Fi support. Reviewed-by: Sam Shih <sam.shih@mediatek.com> Reviewed-by: Ryder Lee <ryder.lee@mediatek.com> Signed-off-by: Peter Chiu <chui-hao.chiu@mediatek.com> Link: https://lore.kernel.org/r/20220901130552.26234-1-chui-hao.chiu@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2022-09-13arm64: dts: mediatek: cherry: Enable MT6315 regulators on SPMI busAngeloGioacchino Del Regno
All machines in the Cherry platform use MT6315 over SPMI: add the two instances, providing Vbcpu and Vgpu regulators. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Tested-by: Chen-Yu Tsai <wenst@chromium.org> Link: https://lore.kernel.org/r/20220902081156.38526-8-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2022-09-13arm64: dts: mediatek: cherry: Enable Elantech eKTH3000 i2c trackpadAngeloGioacchino Del Regno
The Cherry platform uses an Elantech touchpad/trackpad: enable probing it at address 0x15 on I2C1. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Tested-by: Chen-Yu Tsai <wenst@chromium.org> Link: https://lore.kernel.org/r/20220902081156.38526-7-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2022-09-13arm64: dts: mediatek: cherry: Enable secondary SD/MMC controllerAngeloGioacchino Del Regno
As of now, all of the boards based on the cherry platform have a usable secondary SD/MMC controller, usually for SD cards: enable it to allow both booting from it and generally accessing external storage. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20220902081156.38526-6-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2022-09-13arm64: dts: mediatek: cherry: Add keyboard mapping for the top rowAngeloGioacchino Del Regno
Chromebooks' embedded keyboards differ from standard layouts for the top row, as this one doesn't have the standard function keys but shortcuts instead: map these keys to achieve the functionality that is pictured on the printouts. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Tested-by: Chen-Yu Tsai <wenst@chromium.org> Link: https://lore.kernel.org/r/20220902081156.38526-5-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2022-09-13arm64: dts: mediatek: cherry: Add Google Security Chip (GSC) TPMAngeloGioacchino Del Regno
Add support for the Cr50 Google Security Chip (GSC) found on this platform on I2C3 to support TPM and to also use it as an entropy source for the kernel. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20220902081156.38526-4-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2022-09-13arm64: dts: mediatek: cherry: Wire up the ChromeOS Embedded ControllerAngeloGioacchino Del Regno
Wire up the ChromeOS Embedded Controller on SPI0 and its communication channel via SCP RPMSG along with all of the offered functionality, including Keyboard, Smart Battery Metrics (SBS), keyboard backlight, I2C tunnel, regulators and Type-C connector management. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20220902081156.38526-3-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2022-09-13arm64: dts: mediatek: cherry: Enable the System Companion ProcessorAngeloGioacchino Del Regno
MT8195 features a SCP like some other older SoCs, and Cherry uses it for various tasks. Add the required pin configuration and DMA pool and enable the node. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20220902081156.38526-2-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2022-08-31arm64: dts: mediatek: Fix build warnings of mt8173 vcodec nodesTinghan Shen
Correct the phandle of power domain node referenced by vcodec nodes. arch/arm64/boot/dts/mediatek/mt8173.dtsi:1450.35-1471.5: Warning (power_domains_property): /soc/vcodec@18002000: Missing property '#power-domain-cells' in node /soc/syscon@10006000 or bad phandle (referred from power-domains[0]) arch/arm64/boot/dts/mediatek/mt8173.dtsi:1502.35-1522.5: Warning (power_domains_property): /soc/vcodec@19002000: Missing property '#power-domain-cells' in node /soc/syscon@10006000 or bad phandle (referred from power-domains[0]) Fixes: d3dfd4688574 ("arm64: dts: mediatek: Update mt81xx scpsys node to align with dt-bindings") Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com> Link: https://lore.kernel.org/r/20220831065100.27722-1-tinghan.shen@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2022-08-30arm64: dts: mediatek: Add missing xHCI clocks for mt8192 and mt8195Nícolas F. R. A. Prado
The MediaTek xHCI dt-binding expects a specific order for the clocks, but the mt8192 and mt8195 devicetrees were skipping some of the middle clocks. These clocks are wired to the controller hardware but aren't controllable. Add the missing clocks as handles to fixed clocks, so that the clock order is respected and the dtbs_check warnings are gone. Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20220708194314.56922-1-nfraprado@collabora.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2022-08-29arm64: dts: mt8192: Add dsi nodeAllen-KH Cheng
Add dsi node for mt8192 SoC. Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com> Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Tested-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Tested-by: Chen-Yu Tsai <wenst@chromium.org> Link: https://lore.kernel.org/r/20220712114046.15574-6-allen-kh.cheng@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2022-08-29arm64: dts: mt8192: Add display nodesAllen-KH Cheng
Add display nodes and gce info for mt8192 SoC. GCE (Global Command Engine) properties to the display nodes in order to enable the usage of the CMDQ (Command Queue), which is required for operating the display. Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Tested-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Tested-by: Chen-Yu Tsai <wenst@chromium.org> Link: https://lore.kernel.org/r/20220712114046.15574-5-allen-kh.cheng@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2022-08-29arm64: dts: mediatek: Add mmsys #reset-cells property for mt8192Allen-KH Cheng
To support reset of mmsys, we include mt8192-resets.h and add property of #reset-cells in mmsys. Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com> Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Tested-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Tested-by: Chen-Yu Tsai <wenst@chromium.org> Link: https://lore.kernel.org/r/20220712114046.15574-4-allen-kh.cheng@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2022-08-29arm64: dts: mt8192: Add mipi_tx nodeAllen-KH Cheng
Add mipi_tx node for mt8192 SoC. Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Tested-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Tested-by: Chen-Yu Tsai <wenst@chromium.org> Link: https://lore.kernel.org/r/20220712114046.15574-3-allen-kh.cheng@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2022-08-29arm64: dts: mt8192: Add pwm nodeAllen-KH Cheng
Add pwm node for mt8192 SoC. Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Tested-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Tested-by: Chen-Yu Tsai <wenst@chromium.org> Link: https://lore.kernel.org/r/20220712114046.15574-2-allen-kh.cheng@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
generated by cgit-pink 1.4.1 (git 2.36.1) at 2024-10-16 16:28:46 +0000