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2011-11-15ARM: msm: convert SMP platforms to CONFIG_MULTI_IRQ_HANDLERMarc Zyngier
Convert the SMP msm platforms to be using the gic_handle_irq function as their primary interrupt handler. Tested-by: David Brown <davidb@codeaurora.org> Acked-by: David Brown <davidb@codeaurora.org> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2011-11-09Merge branch 'msm-fix' of git://codeaurora.org/quic/kernel/davidb/linux-msm ↵Olof Johansson
into fixes
2011-11-01msm: boards: Fix fallout from removal of machine_desc in fixupStephen Boyd
After 0744a3ee (ARM: platform fixups: remove mdesc argument to fixup function, 2010-12-20) the fixup functions introduced in 9e775ad (ARM: 7012/1: Set proper TEXT_OFFSET for newer MSMs, 2011-08-12) cause warnings like: arch/arm/mach-msm/board-msm8x60.c:85: warning: initialization from incompatible pointer type Fix them by removing the machine_desc argument from the fixup functions. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: David Brown <davidb@codeaurora.org>
2011-10-31Merge branch 'dt/gic' into next/dtArnd Bergmann
Conflicts: arch/arm/include/asm/localtimer.h arch/arm/mach-msm/board-msm8x60.c arch/arm/mach-omap2/board-generic.c
2011-10-23Merge branch 'ppi-irq-core-for-rmk' of ↵Russell King
git://github.com/mzyngier/arm-platforms into devel-stable
2011-10-23ARM: gic: consolidate PPI handlingMarc Zyngier
PPI handling is a bit of an odd beast. It uses its own low level handling code and is hardwired to the local timers (hence lacking a registration interface). Instead, switch the low handling to the normal SPI handling code. PPIs are handled by the handle_percpu_devid_irq flow. This also allows the removal of some duplicated code. Cc: Kukjin Kim <kgene.kim@samsung.com> Cc: David Brown <davidb@codeaurora.org> Cc: Bryan Huntsman <bryanh@codeaurora.org> Cc: Tony Lindgren <tony@atomide.com> Cc: Paul Mundt <lethal@linux-sh.org> Cc: Magnus Damm <magnus.damm@gmail.com> Cc: Thomas Gleixner <tglx@linutronix.de> Acked-by: David Brown <davidb@codeaurora.org> Tested-by: David Brown <davidb@codeaurora.org> Tested-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2011-08-29ARM: msm: Add devicetree support for msm8660-surfDavid Brown
Adds support for booting via device tree with a simple serial console. Change-Id: I7f175b8db21928cd13e0fb49f3eed74966a2696f Signed-off-by: David Brown <davidb@codeaurora.org> Acked-by: Arnd Bergmann <arnd@arndb.de>
2011-08-13ARM: 7012/1: Set proper TEXT_OFFSET for newer MSMsStephen Boyd
MSMs post 8x50 have 2Mb at the beginning of RAM reserved for shared memory. Since the kernel hasn't typically been told this RAM exists, PHYS_OFFSET has been set to 0xN0200000 and the memory atags passed to the kernel have matched. This doesn't play nicely with things such as AUTO_ZRELADDR, which doesn't work at all, and dynamic phys to virt, which requires an MSM specific workaround. Work around these issues by telling the kernel RAM starts at 0xN0000000 (it actually does) and fixup the atags from the bootloader (if necessary) to say the same. In addition, make sure to set TEXT_OFFSET at least 2Mb beyond the start of RAM so that the kernel doesn't end up being decompressed into shared memory. After doing this, AUTO_ZRELADDR should work on MSM with no problems and ARM_PATCH_PHYS_VIRT_16BIT should no longer be necessary. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org> Acked-by: David Brown <davidb@codeaurora.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-03-29arm: Cleanup the irq namespaceThomas Gleixner
Convert to the new function names. Automated with coccinelle. Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2011-01-28msm: clock: Remove unused code and definitionsStephen Boyd
This code is dead or otherwise useless so just remove it. Reviewed-by: Saravana Kannan <skannan@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: David Brown <davidb@codeaurora.org>
2010-12-14ARM: GIC: consolidate gic_cpu_base_addr to common GIC codeRussell King
Every architecture using the GIC has a gic_cpu_base_addr pointer for GIC 0 for their entry assembly code to use to decode the cause of the current interrupt. Move this into the common GIC code. Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Tested-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2010-12-14ARM: GIC: provide a single initialization function for boot CPURussell King
Provide gic_init() which initializes the GIC distributor and current CPU's GIC interface for the boot (or single) CPU. Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Tested-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2010-10-08msm: add MSM8x60 FFA supportGregory Bean
The MSM8X60 FFA contains different components than the MSM8X60 SURF, and therefore requires a different ARCH type and machine ID. Signed-off-by: Gregory Bean <gbean@codeaurora.org> Signed-off-by: Daniel Walker <dwalker@codeaurora.org>
2010-10-08msm: MSM8X60 simulator board supportSteve Muckle
Board configuration for MSM8X60 simulation. Signed-off-by: Steve Muckle <smuckle@codeaurora.org> Signed-off-by: Daniel Walker <dwalker@codeaurora.org>
2010-10-08msm: add msm8x60_surf machineSteve Muckle
Signed-off-by: Steve Muckle <smuckle@codeaurora.org> Signed-off-by: Daniel Walker <dwalker@codeaurora.org>
2010-10-08msm: 8x60: setup correct handlers for private interruptsAbhijeet Dharmapurikar
Private Peripheral interrupts could be edge triggered or level triggered depending on the platform. Initialize handlers for these in board file. Signed-off-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org> Signed-off-by: Daniel Walker <dwalker@codeaurora.org>
2010-10-08msm: 8x60: gic initialization fixup for RUMISteve Muckle
On RUMI platform STIs are not enabled by default, contrary to the GIC spec. The bits for STIs in the enable/enable clear registers are also RW instead of RO. STIs need to be enabled at initialization time. Signed-off-by: Steve Muckle <smuckle@codeaurora.org> Signed-off-by: Daniel Walker <dwalker@codeaurora.org>
2010-10-08msm: MSM8X60 RUMI3 board supportSteve Muckle
Board configuration for MSM8X60 emulation on RUMI3. Signed-off-by: Steve Muckle <smuckle@codeaurora.org> Signed-off-by: Daniel Walker <dwalker@codeaurora.org>
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