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2022-01-13Merge branch 'remotes/lorenzo/pci/mvebu'Bjorn Helgaas
- Implement pci_remap_iospace() for ARM so mvebu can use devm_pci_remap_iospace() instead of the previous ARM-specific pci_ioremap_io() interface (Pali Rohár) - Use the standard pci_host_probe() instead of the device-specific mvebu_pci_host_probe() (Pali Rohár) - Replace all uses of ARM-specific pci_ioremap_io() with the ARM implementation of the standard pci_remap_iospace() interface and remove pci_ioremap_io() (Pali Rohár) - Skip initializing invalid Root Ports (Pali Rohár) - Check for errors from pci_bridge_emul_init() (Pali Rohár) - Ignore any bridges at non-zero function numbers (Pali Rohár) - Return ~0 data for invalid config read size (Pali Rohár) - Disallow mapping interrupts on emulated bridges (Pali Rohár) - Clear Root Port Memory & I/O Space Enable and Bus Master Enable at initialization (Pali Rohár) - Make type bits in Root Port I/O Base register read-only (Pali Rohár) - Disable Root Port windows when base/limit set to invalid values (Pali Rohár) - Set controller to Root Complex mode (Pali Rohár) - Set Root Port Class Code to PCI Bridge (Pali Rohár) - Update emulated Root Port secondary bus numbers to better reflect the actual topology (Pali Rohár) - Add PCI_BRIDGE_CTL_BUS_RESET support to emulated Root Ports so pci_reset_secondary_bus() can reset connected devices (Pali Rohár) - Add PCI_EXP_DEVCTL Error Reporting Enable support to emulated Root Ports (Pali Rohár) - Add PCI_EXP_RTSTA PME Status bit support to emulated Root Ports (Pali Rohár) - Add DEVCAP2, DEVCTL2 and LNKCTL2 support to emulated Root Ports on Armada XP and newer devices (Pali Rohár) - Export mvebu-mbus.c symbols to allow pci-mvebu.c to be a module (Pali Rohár) - Add support for compiling as a module (Pali Rohár) * remotes/lorenzo/pci/mvebu: PCI: mvebu: Add support for compiling driver as module bus: mvebu-mbus: Export symbols for public API window functions PCI: mvebu: Fix support for DEVCAP2, DEVCTL2 and LNKCTL2 registers on emulated bridge PCI: mvebu: Fix support for PCI_EXP_RTSTA on emulated bridge PCI: mvebu: Fix support for PCI_EXP_DEVCTL on emulated bridge PCI: mvebu: Fix support for PCI_BRIDGE_CTL_BUS_RESET on emulated bridge PCI: mvebu: Fix configuring secondary bus of PCIe Root Port via emulated bridge PCI: mvebu: Set PCI Bridge Class Code to PCI Bridge PCI: mvebu: Setup PCIe controller to Root Complex mode PCI: mvebu: Propagate errors when updating PCI_IO_BASE and PCI_MEM_BASE registers PCI: mvebu: Do not modify PCI IO type bits in conf_write PCI: mvebu: Fix support for bus mastering and PCI_COMMAND on emulated bridge PCI: mvebu: Disallow mapping interrupts on emulated bridges PCI: mvebu: Handle invalid size of read config request PCI: mvebu: Check that PCI bridge specified in DT has function number zero PCI: mvebu: Check for errors from pci_bridge_emul_init() call PCI: mvebu: Check for valid ports arm: ioremap: Remove unused ARM-specific function pci_ioremap_io() arm: ioremap: Replace pci_ioremap_io() usage by pci_remap_iospace() PCI: mvebu: Remove custom mvebu_pci_host_probe() function PCI: mvebu: Replace pci_ioremap_io() usage by devm_pci_remap_iospace() arm: ioremap: Implement standard PCI function pci_remap_iospace()
2022-01-13Merge branch 'pci/host/mt7621'Bjorn Helgaas
- Declare mt7621_pci_ops static (Sergio Paracuellos) - Give pcibios_root_bridge_prepare() access to host bridge windows (Sergio Paracuellos) - Move MIPS I/O coherency unit setup from driver to pcibios_root_bridge_prepare() (Sergio Paracuellos) - Add missing MODULE_LICENSE() (Sergio Paracuellos) - Allow COMPILE_TEST for all arches (Sergio Paracuellos) * pci/host/mt7621: PCI: mt7621: Allow COMPILE_TEST for all arches PCI: mt7621: Add missing MODULE_LICENSE() PCI: mt7621: Move MIPS setup to pcibios_root_bridge_prepare() PCI: Let pcibios_root_bridge_prepare() access bridge->windows PCI: mt7621: Declare mt7621_pci_ops static
2022-01-13Merge branch 'remotes/lorenzo/pci/mediatek-gen3'Bjorn Helgaas
- Disable Mediatek DVFSRC voltage request since lack of DVFSRC to respond to the request causes failure to exit L1 PM Substate (Jianjun Wang) * remotes/lorenzo/pci/mediatek-gen3: PCI: mediatek-gen3: Disable DVFSRC voltage request
2022-01-13Merge branch 'remotes/lorenzo/pci/mediatek'Bjorn Helgaas
- Assert PERST# for 100ms to allow power and clock to stabilize (qizhong cheng) * remotes/lorenzo/pci/mediatek: PCI: mediatek: Assert PERST# for 100ms for power and clock to stabilize
2022-01-13Merge branch 'remotes/lorenzo/pci/keystone'Bjorn Helgaas
- Add register offset for ti,syscon-pcie-id and ti,syscon-pcie-mode DT properties (Kishon Vijay Abraham I) * remotes/lorenzo/pci/keystone: PCI: keystone: Use phandle argument from "ti,syscon-pcie-id"/"ti,syscon-pcie-mode" dt-bindings: PCI: ti,am65: Fix "ti,syscon-pcie-id"/"ti,syscon-pcie-mode" to take argument
2022-01-13Merge branch 'pci/host/hv'Bjorn Helgaas
- Add hv-internal interfaces to encapsulate arch IRQ dependencies (Sunil Muthuswamy) - Add arm64 Hyper-V vPCI support (Sunil Muthuswamy) * pci/host/hv: PCI: hv: Add arm64 Hyper-V vPCI support PCI: hv: Make the code arch neutral by adding arch specific interfaces
2022-01-13Merge branch 'remotes/lorenzo/pci/endpoint'Bjorn Helgaas
- Return failure from pci_epc_set_msi() if no interrupts are available (Li Chen) * remotes/lorenzo/pci/endpoint: PCI: endpoint: Return -EINVAL when interrupts num is smaller than 1
2022-01-13Merge branch 'remotes/lorenzo/pci/dwc'Bjorn Helgaas
- Don't ioremap NULL when DT lacks ATU resource (Tim Harvey) - Drop redundant qcom-ep error message for platform_get_irq_byname() failure (Krzysztof Wilczyński) - Add i.MX8MM support (Richard Zhu) - Use DWC common ops instead of layerscape-specific link-up functions (Hou Zhiqiang) * remotes/lorenzo/pci/dwc: PCI: layerscape: Change to use the DWC common link-up check function PCI: imx: Add the imx8mm pcie support dt-bindings: imx6q-pcie: Add PHY phandles and name properties PCI: qcom-ep: Remove surplus dev_err() when using platform_get_irq_byname() PCI: dwc: Do not remap invalid res
2022-01-13Merge branch 'pci/host/brcmstb'Bjorn Helgaas
- Declare bitmap correctly for use by bitmap interfaces (Christophe JAILLET) - Clean up computation of legacy and non-legacy MSI bitmasks (Florian Fainelli) - Update suspend/resume/remove error handling to warn about errors and not fail the operation (Jim Quinlan) - Correct the "pcie" and "msi" interrupt descriptions in DT binding (Jim Quinlan) - Add DT bindings for endpoint voltage regulators (Jim Quinlan) - Split brcm_pcie_setup() into two functions (Jim Quinlan) - Add mechanism for turning on voltage regulators for connected devices (Jim Quinlan) - Turn voltage regulators for connected devices on/off when bus is added or removed (Jim Quinlan) - When suspending, don't turn off voltage regulators for wakeup devices (Jim Quinlan) * pci/host/brcmstb: PCI: brcmstb: Do not turn off WOL regulators on suspend PCI: brcmstb: Add control of subdevice voltage regulators PCI: brcmstb: Add mechanism to turn on subdev regulators PCI: brcmstb: Split brcm_pcie_setup() into two funcs dt-bindings: PCI: Add bindings for Brcmstb EP voltage regulators dt-bindings: PCI: Correct brcmstb interrupts, interrupt-map. PCI: brcmstb: Fix function return value handling PCI: brcmstb: Do not use __GENMASK PCI: brcmstb: Declare 'used' as bitmap, not unsigned long
2022-01-13Merge branch 'remotes/lorenzo/pci/apple'Bjorn Helgaas
- Enable clock gating to save power (Hector Martin) - Fix REFCLK1 enable/poll logic (Hector Martin) * remotes/lorenzo/pci/apple: PCI: apple: Fix REFCLK1 enable/poll logic PCI: apple: Enable clock gating
2022-01-13Merge branch 'remotes/lorenzo/pci/aardvark'Bjorn Helgaas
- Add bridge emulation definitions for PCIe DEVCAP2, DEVCTL2, DEVSTA2, LNKCAP2, LNKCTL2, LNKSTA2, SLTCAP2, SLTCTL2, SLTSTA2 (Pali Rohár) - Add aardvark support for DEVCAP2, DEVCTL2, LNKCAP2 and LNKCTL2 registers (Pali Rohár) - Clear all MSIs at setup to avoid spurious interrupts (Pali Rohár) - Disable bus mastering when unbinding host controller driver (Pali Rohár) - Mask all interrupts when unbinding host controller driver (Pali Rohár) - Fix memory leak in host controller unbind (Pali Rohár) - Assert PERST# when unbinding host controller driver (Pali Rohár) - Disable link training when unbinding host controller driver (Pali Rohár) - Disable common PHY when unbinding host controller driver (Pali Rohár) - Fix resource type checking to check only IORESOURCE_MEM, not IORESOURCE_MEM_64, which is a flavor of IORESOURCE_MEM (Pali Rohár) * remotes/lorenzo/pci/aardvark: PCI: aardvark: Fix checking for MEM resource type PCI: aardvark: Disable common PHY when unbinding driver PCI: aardvark: Disable link training when unbinding driver PCI: aardvark: Assert PERST# when unbinding driver PCI: aardvark: Fix memory leak in driver unbind PCI: aardvark: Mask all interrupts when unbinding driver PCI: aardvark: Disable bus mastering when unbinding driver PCI: aardvark: Comment actions in driver remove method PCI: aardvark: Clear all MSIs at setup PCI: aardvark: Add support for DEVCAP2, DEVCTL2, LNKCAP2 and LNKCTL2 registers on emulated bridge PCI: pci-bridge-emul: Add definitions for missing capabilities registers PCI: pci-bridge-emul: Add description for class_revision field
2022-01-13Merge branch 'pci/virtualization'Bjorn Helgaas
- Add function 1 DMA alias quirk for Marvell 88SE9125 SATA controller so it can work with an IOMMU (Yifeng Li) * pci/virtualization: PCI: Add function 1 DMA alias quirk for Marvell 88SE9125 SATA controller
2022-01-13Merge branch 'pci/switchtec'Bjorn Helgaas
- Add Gen4 automotive device IDs (Kelvin Cao) - Declare state_names[] as static so it's not allocated and initialized for every call (Kelvin Cao) * pci/switchtec: PCI/switchtec: Declare local state_names[] as static PCI/switchtec: Add Gen4 automotive device IDs
2022-01-13Merge branch 'pci/resource'Bjorn Helgaas
- Always write Intel I210 ROM BAR on update to work around device defect (Bjorn Helgaas) * pci/resource: PCI: Work around Intel I210 ROM BAR overlap defect
2022-01-13Merge branch 'pci/p2pdma'Bjorn Helgaas
- Add Logan Gunthorpe as P2PDMA maintainer (Bjorn Helgaas) - Optimize by using percpu_ref_tryget_live_rcu() inside RCU critical section (Christophe JAILLET) * pci/p2pdma: PCI/P2PDMA: Use percpu_ref_tryget_live_rcu() inside RCU critical section MAINTAINERS: Add Logan Gunthorpe as P2PDMA maintainer
2022-01-13Merge branch 'pci/legacy-pm-removal'Bjorn Helgaas
- Convert amd64-agp, sis-agp, via-agp from legacy PCI power management to generic power management (Vaibhav Gupta) * pci/legacy-pm-removal: via-agp: convert to generic power management sis-agp: convert to generic power management amd64-agp: convert to generic power management
2022-01-13Merge branch 'pci/hotplug'Bjorn Helgaas
- Fix infinite loop in pciehp IRQ handler on power fault (Lukas Wunner) - Removed commented-out ibmphp functions (Vihas Mak) - Fix pciehp lockdep errors on Thunderbolt undock (Hans de Goede) * pci/hotplug: PCI: pciehp: Use down_read/write_nested(reset_lock) to fix lockdep errors PCI: ibmphp: Remove commented-out functions PCI: pciehp: Fix infinite loop in IRQ handler upon power fault
2022-01-13Merge branch 'pci/enumeration'Bjorn Helgaas
- Use pci_find_vsec_capability() instead of open-coding it (Andy Shevchenko) - Convert pci_dev_present() stub from macro to static inline to avoid 'unused variable' errors (Hans de Goede) - Convert sysfs slot attributes from default_attrs to default_groups (Greg Kroah-Hartman) - Use DWORD accesses for LTR, L1 SS to avoid BayHub OZ711LV2 erratum (Rajat Jain) - Remove unnecessary initialization of static variables (Longji Guo) * pci/enumeration: x86/PCI: Remove initialization of static variables to false PCI: Use DWORD accesses for LTR, L1 SS to avoid erratum PCI/sysfs: Use default_groups in kobj_type for slot attrs PCI: Convert pci_dev_present() stub to static inline PCI: Use pci_find_vsec_capability() when looking for TBT devices
2022-01-13Merge branch 'pci/aspm'Bjorn Helgaas
- Calculate link L0s and L1 exit latencies when needed instead of caching them (Saheed O. Bolarinwa) - Calculate device L0s and L1 acceptable exit latencies when needed instead of caching them (Saheed O. Bolarinwa) - Remove struct aspm_latency since it's no longer needed (Saheed O. Bolarinwa) * pci/aspm: PCI/ASPM: Remove struct aspm_latency PCI/ASPM: Stop caching device L0s, L1 acceptable exit latencies PCI/ASPM: Stop caching link L0s, L1 exit latencies PCI/ASPM: Move pci_function_0() upward
2022-01-12PCI: mt7621: Allow COMPILE_TEST for all archesSergio Paracuellos
Since all MIPS-specific code has been removed from driver, allow it to be enabled for COMPILE_TEST on all architectures. Mark it as tristate and remove MIPS the MIPS dependency. Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2022-01-12PCI: mt7621: Add missing MODULE_LICENSE()Sergio Paracuellos
The MT7621 PCIe host controller driver can be built as a module, but it lacks a MODULE_LICENSE(), which causes a build error: ERROR: modpost: missing MODULE_LICENSE() in drivers/pci/controller/pcie-mt7621.o Add MODULE_LICENSE() to the driver. Fixes: 2bdd5238e756 ("PCI: mt7621: Add MediaTek MT7621 PCIe host controller driver") Link: https://lore.kernel.org/r/20211207104924.21327-5-sergio.paracuellos@gmail.com Signed-off-by: Yanteng Si <siyanteng@loongson.cn> Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Krzysztof Wilczyński <kw@linux.com>
2022-01-12PCI: mt7621: Move MIPS setup to pcibios_root_bridge_prepare()Sergio Paracuellos
On the MIPS ralink mt7621 platform, we need to set up I/O coherency units based on the host bridge apertures. To remove this arch dependency from the driver itself, move the coherency setup from the driver to pcibios_root_bridge_prepare(). [bhelgaas: squash add/remove into one patch, commit log] Link: https://lore.kernel.org/r/20211207104924.21327-3-sergio.paracuellos@gmail.com Link: https://lore.kernel.org/r/20211207104924.21327-4-sergio.paracuellos@gmail.com Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Guenter Roeck <linux@roeck-us.net> # arch/mips Acked-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de> # arch/mips
2022-01-12PCI: Let pcibios_root_bridge_prepare() access bridge->windowsSergio Paracuellos
When pci_register_host_bridge() is called, bridge->windows are already available. However these windows are being moved temporarily from there. To let pcibios_root_bridge_prepare() have access to these windows, move the windows movement after calling this function. This is useful for the MIPS ralink mt7621 platform so it can set up I/O coherence units and avoid custom MIPS code in the mt7621 PCIe controller driver. Link: https://lore.kernel.org/r/20211207104924.21327-2-sergio.paracuellos@gmail.com Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
2022-01-12PCI: mt7621: Declare mt7621_pci_ops staticSergio Paracuellos
Sparse complains about mt7621_pci_ops symbol is not declared and asks if it should be declared as static instead. Sparse is right. Hence declare symbol as static. Link: https://lore.kernel.org/r/20211117152952.12271-1-sergio.paracuellos@gmail.com Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Krzysztof Wilczyński <kw@linux.com>
2022-01-12PCI: brcmstb: Do not turn off WOL regulators on suspendJim Quinlan
If any downstream device can be a wakeup device, do not turn off the regulators as the device will need them on. Link: https://lore.kernel.org/r/20220106160332.2143-8-jim2101024@gmail.com Signed-off-by: Jim Quinlan <jim2101024@gmail.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2022-01-12PCI: brcmstb: Add control of subdevice voltage regulatorsJim Quinlan
This Broadcom STB PCIe RC driver has one port and connects directly to one device, be it a switch or an endpoint. We want to be able to leverage the recently added mechanism that allocates and turns on/off subdevice regulators. All that needs to be done is to put the regulator DT nodes in the bridge below host and to set the pci_ops methods add_bus and remove_bus. Note that the pci_subdev_regulators_add_bus() method is wrapped for two reasons: 1. To achieve link up after the voltage regulators are turned on. 2. If, in the case of an unsuccessful link up, to redirect any PCIe accesses to subdevices, e.g. the scan for DEV/ID. This redirection is needed because the Broadcom PCIe HW will issue a CPU abort if such an access is made when the link is down. [bhelgaas: fold in https://lore.kernel.org/r/20220112013100.48029-1-jim2101024@gmail.com] Link: https://lore.kernel.org/r/20220106160332.2143-7-jim2101024@gmail.com Signed-off-by: Jim Quinlan <jim2101024@gmail.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2022-01-12PCI: brcmstb: Add mechanism to turn on subdev regulatorsJim Quinlan
Add a mechanism to identify standard PCIe regulators in the DT, allocate them, and turn them on before the rest of the bus is scanned during pci_host_probe(). The allocated structure that contains the regulators is stored in the port driver dev.driver_data field. Here is a point-by-point of how and when this mechanism is activated: If: -- PCIe RC driver sets pci_ops {add,remove)_bus to pci_subdev_regulators_{add,remove}_bus during its probe. -- There is a DT node "RB" under the host bridge DT node. -- During the RC driver's pci_host_probe() the add_bus callback is invoked where (bus->parent && pci_is_root_bus(bus->parent) is true Then: -- A struct subdev_regulators structure will be allocated and assigned to bus->dev.driver_data. -- regulator_bulk_{get,enable} will be invoked on &bus->dev and the former will search for and process any vpcie{12v,3v3,3v3aux}-supply properties that reside in node "RB". -- The regulators will be turned off/on for any unbind/bind operations. -- The regulators will be turned off/on for any suspend/resumes, but only if the RC driver handles this on its own. This will appear in a later commit for the pcie-brcmstb.c driver. The unabridged reason for doing this is as follows. We would like the Broadcom STB PCIe root complex driver (and others) to be able to turn off/on regulators[1] that provide power to endpoint[2] devices. Typically, the drivers of these endpoint devices are stock Linux drivers that are not aware that these regulator(s) exist and must be turned on for the driver to be probed. The simple solution of course is to turn these regulators on at boot and keep them on. However, this solution does not satisfy at least three of our usage modes: 1. For example, one customer uses multiple PCIe controllers, but wants the ability to, by script invoking and unbind, turn any or all of them and their subdevices off to save power, e.g. when in battery mode. 2. Another example is when a watchdog script discovers that an endpoint device is in an unresponsive state and would like to unbind, power toggle, and re-bind just the PCIe endpoint and controller. 3. Of course we also want power turned off during suspend mode. However, some endpoint devices may be able to "wake" during suspend and we need to recognise this case and veto the nominal act of turning off its regulator. Such is the case with Wake-on-LAN and Wake-on-WLAN support where the PCIe endpoint device needs to be kept powered on in order to receive network packets and wake the system. In all of these cases it is advantageous for the PCIe controller to govern the turning off/on the regulators needed by the endpoint device. The first two cases can be done by simply unbinding and binding the PCIe controller, if the controller has control of these regulators. [1] These regulators typically govern the actual power supply to the endpoint chip. Sometimes they may be the official PCIe socket power -- such as 3.3v or aux-3.3v. Sometimes they are truly the regulator(s) that supply power to the EP chip. [2] The 99% configuration of our boards is a single endpoint device attached to the PCIe controller. I use the term endpoint but it could possibly mean a switch as well. Link: https://lore.kernel.org/r/20220106160332.2143-6-jim2101024@gmail.com Signed-off-by: Jim Quinlan <jim2101024@gmail.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2022-01-12PCI: brcmstb: Split brcm_pcie_setup() into two funcsJim Quinlan
We need to take some code in brcm_pcie_setup() and put it in a new function brcm_pcie_linkup(). In future commits the brcm_pcie_linkup() function will be called indirectly by pci_host_probe() as opposed to the host driver invoking it directly. Some code that was executed after the PCIe linkup is now placed so that it executes prior to linkup, since this code has to run prior to the invocation of pci_host_probe(). Link: https://lore.kernel.org/r/20220106160332.2143-5-jim2101024@gmail.com Signed-off-by: Jim Quinlan <jim2101024@gmail.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2022-01-12dt-bindings: PCI: Add bindings for Brcmstb EP voltage regulatorsJim Quinlan
Add bindings for Brcmstb EP voltage regulators. A new mechanism is to be added to the Linux PCI subsystem that will allocate and turn on/off regulators. These are standard regulators -- vpcie12v, vpcie3v3, and vpcie3v3aux -- placed in the DT in the bridge node under the host bridge device. The use of a regulator property in the PCIe EP subnode such as "vpcie12v-supply" depends on a pending pullreq to the pci-bus.yaml file at https://github.com/devicetree-org/dt-schema/pull/63 Link: https://lore.kernel.org/r/20220106160332.2143-4-jim2101024@gmail.com Signed-off-by: Jim Quinlan <jim2101024@gmail.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Rob Herring <robh@kernel.org> Acked-by: Florian Fainelli <f.fainelli@gmail.com>
2022-01-12dt-bindings: PCI: Correct brcmstb interrupts, interrupt-map.Jim Quinlan
The "pcie" and "msi" interrupts were given the same interrupt when they are actually different. Interrupt-map only had the INTA entry; add the INTB, INTC, and INTD entries. Link: https://lore.kernel.org/r/20220106160332.2143-3-jim2101024@gmail.com Signed-off-by: Jim Quinlan <jim2101024@gmail.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Florian Fainelli <f.fainelli@gmail.com> Acked-by: Rob Herring <robh@kernel.org>
2022-01-12PCI: brcmstb: Fix function return value handlingJim Quinlan
Do at least a dev_err() on some calls to reset_control_rearm() and brcm_phy_stop(). In some cases it may not make sense to return this error value "above" as doing so will cause more trouble than is warranted. Link: https://lore.kernel.org/r/20220106160332.2143-2-jim2101024@gmail.com Signed-off-by: Jim Quinlan <jim2101024@gmail.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Florian Fainelli <f.fainelli@gmail.com>
2022-01-12PCI: brcmstb: Do not use __GENMASKFlorian Fainelli
Define the legacy MSI interrupt bitmask as well as the non-legacy interrupt bitmask using GENMASK and then use them in brcm_msi_set_regs() in place of __GENMASK(). Link: https://lore.kernel.org/r/20211122190459.3189616-1-f.fainelli@gmail.com Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
2022-01-12PCI: brcmstb: Declare 'used' as bitmap, not unsigned longChristophe JAILLET
The 'used' field of 'struct brcm_msi' is used as a bitmap. Declare it with DECLARE_BITMAP() and adjust users accordingly. This fixes a harmless Coverity warning about array vs singleton usage. This bitmap can be used for either legacy or MSI interrupts, which require a size of BRCM_INT_PCI_MSI_LEGACY_NR or BRCM_INT_PCI_MSI_NR respectively. Add a BUILD_BUG_ON() to ensure it is large enough. Suggested-by: Krzysztof Wilczynski <kw@linux.com> Addresses-Coverity: "Out-of-bounds access (ARRAY_VS_SINGLETON)" Link: https://lore.kernel.org/r/e6d9da2112aab2939d1507b90962d07bfd735b4c.1636273671.git.christophe.jaillet@wanadoo.fr Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
2022-01-12PCI: hv: Add arm64 Hyper-V vPCI supportSunil Muthuswamy
Add arm64 Hyper-V vPCI support by implementing the arch specific interfaces. Introduce an IRQ domain and chip specific to Hyper-v vPCI that is based on SPIs. The IRQ domain parents itself to the arch GIC IRQ domain for basic vector management. [bhelgaas: squash in fix from Yang Li <yang.lee@linux.alibaba.com>: https://lore.kernel.org/r/20220112003324.62755-1-yang.lee@linux.alibaba.com] Link: https://lore.kernel.org/r/1641411156-31705-3-git-send-email-sunilmut@linux.microsoft.com Signed-off-by: Sunil Muthuswamy <sunilmut@microsoft.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Marc Zyngier <maz@kernel.org> Reviewed-by: Michael Kelley <mikelley@microsoft.com>
2022-01-12PCI: hv: Make the code arch neutral by adding arch specific interfacesSunil Muthuswamy
Encapsulate arch dependencies in Hyper-V vPCI through a set of arch-dependent interfaces. Adding these arch specific interfaces will allow for an implementation for other architectures, such as arm64. There are no functional changes expected from this patch. Link: https://lore.kernel.org/r/1641411156-31705-2-git-send-email-sunilmut@linux.microsoft.com Signed-off-by: Sunil Muthuswamy <sunilmut@microsoft.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Boqun Feng <boqun.feng@gmail.com> Reviewed-by: Marc Zyngier <maz@kernel.org> Reviewed-by: Michael Kelley <mikelley@microsoft.com>
2022-01-12PCI: pciehp: Use down_read/write_nested(reset_lock) to fix lockdep errorsHans de Goede
Use down_read_nested() and down_write_nested() when taking the ctrl->reset_lock rw-sem, passing the number of PCIe hotplug controllers in the path to the PCI root bus as lock subclass parameter. This fixes the following false-positive lockdep report when unplugging a Lenovo X1C8 from a Lenovo 2nd gen TB3 dock: pcieport 0000:06:01.0: pciehp: Slot(1): Link Down pcieport 0000:06:01.0: pciehp: Slot(1): Card not present ============================================ WARNING: possible recursive locking detected 5.16.0-rc2+ #621 Not tainted -------------------------------------------- irq/124-pciehp/86 is trying to acquire lock: ffff8e5ac4299ef8 (&ctrl->reset_lock){.+.+}-{3:3}, at: pciehp_check_presence+0x23/0x80 but task is already holding lock: ffff8e5ac4298af8 (&ctrl->reset_lock){.+.+}-{3:3}, at: pciehp_ist+0xf3/0x180 other info that might help us debug this: Possible unsafe locking scenario: CPU0 ---- lock(&ctrl->reset_lock); lock(&ctrl->reset_lock); *** DEADLOCK *** May be due to missing lock nesting notation 3 locks held by irq/124-pciehp/86: #0: ffff8e5ac4298af8 (&ctrl->reset_lock){.+.+}-{3:3}, at: pciehp_ist+0xf3/0x180 #1: ffffffffa3b024e8 (pci_rescan_remove_lock){+.+.}-{3:3}, at: pciehp_unconfigure_device+0x31/0x110 #2: ffff8e5ac1ee2248 (&dev->mutex){....}-{3:3}, at: device_release_driver+0x1c/0x40 stack backtrace: CPU: 4 PID: 86 Comm: irq/124-pciehp Not tainted 5.16.0-rc2+ #621 Hardware name: LENOVO 20U90SIT19/20U90SIT19, BIOS N2WET30W (1.20 ) 08/26/2021 Call Trace: <TASK> dump_stack_lvl+0x59/0x73 __lock_acquire.cold+0xc5/0x2c6 lock_acquire+0xb5/0x2b0 down_read+0x3e/0x50 pciehp_check_presence+0x23/0x80 pciehp_runtime_resume+0x5c/0xa0 device_for_each_child+0x45/0x70 pcie_port_device_runtime_resume+0x20/0x30 pci_pm_runtime_resume+0xa7/0xc0 __rpm_callback+0x41/0x110 rpm_callback+0x59/0x70 rpm_resume+0x512/0x7b0 __pm_runtime_resume+0x4a/0x90 __device_release_driver+0x28/0x240 device_release_driver+0x26/0x40 pci_stop_bus_device+0x68/0x90 pci_stop_bus_device+0x2c/0x90 pci_stop_and_remove_bus_device+0xe/0x20 pciehp_unconfigure_device+0x6c/0x110 pciehp_disable_slot+0x5b/0xe0 pciehp_handle_presence_or_link_change+0xc3/0x2f0 pciehp_ist+0x179/0x180 This lockdep warning is triggered because with Thunderbolt, hotplug ports are nested. When removing multiple devices in a daisy-chain, each hotplug port's reset_lock may be acquired recursively. It's never the same lock, so the lockdep splat is a false positive. Because locks at the same hierarchy level are never acquired recursively, a per-level lockdep class is sufficient to fix the lockdep warning. The choice to use one lockdep subclass per pcie-hotplug controller in the path to the root-bus was made to conserve class keys because their number is limited and the complexity grows quadratically with number of keys according to Documentation/locking/lockdep-design.rst. Link: https://lore.kernel.org/linux-pci/20190402021933.GA2966@mit.edu/ Link: https://lore.kernel.org/linux-pci/de684a28-9038-8fc6-27ca-3f6f2f6400d7@redhat.com/ Link: https://lore.kernel.org/r/20211217141709.379663-1-hdegoede@redhat.com Link: https://bugzilla.kernel.org/show_bug.cgi?id=208855 Reported-by: "Theodore Ts'o" <tytso@mit.edu> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Lukas Wunner <lukas@wunner.de> Cc: stable@vger.kernel.org
2022-01-11x86/PCI: Remove initialization of static variables to falseLongji Guo
Remove the initialization of pci_ignore_seg to false which is pointless. Link: https://lore.kernel.org/r/20211203080758.962-1-guolongji@uniontech.com Signed-off-by: Longji Guo <guolongji@uniontech.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2022-01-11PCI: Use DWORD accesses for LTR, L1 SS to avoid erratumRajat Jain
Some devices have an erratum such that they only support DWORD accesses to some registers. E.g., this Bayhub O2 device ([VID:DID] = [0x1217:0x8621]) only supports DWORD accesses to LTR latency registers and L1 PM substates control registers: https://github.com/rajatxjain/public_shared/blob/main/OZ711LV2_appnote.pdf The L1 PM substate control registers are DWORD sized, and hence their access in the kernel is already DWORD sized, so we don't need to do anything for them. However, the LTR registers being WORD sized, are in need of a solution. Convert the WORD sized accesses to these registers into DWORD sized accesses while saving and restoring them. Link: https://lore.kernel.org/r/20211222012105.3438916-1-rajatja@google.com Signed-off-by: Rajat Jain <rajatja@google.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2022-01-11PCI: Work around Intel I210 ROM BAR overlap defectBjorn Helgaas
Per PCIe r5, sec 7.5.1.2.4, a device must not claim accesses to its Expansion ROM unless both the Memory Space Enable and the Expansion ROM Enable bit are set. But apparently some Intel I210 NICs don't work correctly if the ROM BAR overlaps another BAR, even if the Expansion ROM is disabled. Michael reported that on a Kontron SMARC-sAL28 ARM64 system with U-Boot v2021.01-rc3, the ROM BAR overlaps BAR 3, and networking doesn't work at all: BAR 0: 0x40000000 (32-bit, non-prefetchable) [size=1M] BAR 3: 0x40200000 (32-bit, non-prefetchable) [size=16K] ROM: 0x40200000 (disabled) [size=1M] NETDEV WATCHDOG: enP2p1s0 (igb): transmit queue 0 timed out Hardware name: Kontron SMARC-sAL28 (Single PHY) on SMARC Eval 2.0 carrier (DT) igb 0002:01:00.0 enP2p1s0: Reset adapter Previously, pci_std_update_resource() wrote the assigned ROM address to the BAR only when the ROM was enabled. This meant that the I210 ROM BAR could be left with an address assigned by firmware, which might overlap with other BARs. Quirk these I210 devices so pci_std_update_resource() always writes the assigned address to the ROM BAR, whether or not the ROM is enabled. Link: https://lore.kernel.org/r/20211223163754.GA1267351@bhelgaas Link: https://lore.kernel.org/r/20201230185317.30915-1-michael@walle.cc Link: https://bugzilla.kernel.org/show_bug.cgi?id=211105 Reported-by: Michael Walle <michael@walle.cc> Tested-by: Michael Walle <michael@walle.cc> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2022-01-07PCI: keystone: Use phandle argument from ↵Kishon Vijay Abraham I
"ti,syscon-pcie-id"/"ti,syscon-pcie-mode" Get "syscon" pcie_mode and pcie_id offset from the argument of "ti,syscon-pcie-id" and "ti,syscon-pcie-mode" phandle respectively. Previously a subnode to "syscon" node was added which has the exact memory mapped address of pcie_mode and pcie_id but now the offset of pcie_mode and pcie_id within "syscon" is now being passed as argument to "ti,syscon-pcie-id" and "ti,syscon-pcie-mode" phandle. If the offset is not provided in "ti,syscon-pcie-id"/"ti,syscon-pcie-mode", the full memory mapped address of pcie_ctrl is used in order to maintain old DT compatibility. Similar change for J721E is as discussed in [1] [1] -> http://lore.kernel.org/r/CAL_JsqKiUcO76bo1GoepWM1TusJWoty_BRy2hFSgtEVMqtrvvQ@mail.gmail.com Link: https://lore.kernel.org/r/20211126083119.16570-3-kishon@ti.com Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
2022-01-07dt-bindings: PCI: ti,am65: Fix "ti,syscon-pcie-id"/"ti,syscon-pcie-mode" to ↵Kishon Vijay Abraham I
take argument Fix binding documentation of "ti,syscon-pcie-id" and "ti,syscon-pcie-mode" to take phandle with argument. The argument is the register offset within "syscon" used to configure PCIe controller. Similar change for j721e is discussed in [1] [1] -> http://lore.kernel.org/r/CAL_JsqKiUcO76bo1GoepWM1TusJWoty_BRy2hFSgtEVMqtrvvQ@mail.gmail.com Link: https://lore.kernel.org/r/20211126083119.16570-2-kishon@ti.com Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Rob Herring <robh@kernel.org>
2022-01-07PCI: endpoint: Return -EINVAL when interrupts num is smaller than 1Li Chen
In pci_epc_set_msi() we should return immediately if there are no interrupts to configure; update the code to return early. Link: https://lore.kernel.org/r/CH2PR19MB402491B9E503694DBCAC6005A07C9@CH2PR19MB4024.namprd19.prod.outlook.com Signed-off-by: Li Chen <lchen@ambarella.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Kishon Vijay Abraham I <kishon@ti.com>
2022-01-07PCI: mediatek: Assert PERST# for 100ms for power and clock to stabilizeqizhong cheng
Described in PCIe CEM specification sections 2.2 (PERST# Signal) and 2.2.1 (Initial Power-Up (G3 to S0)). The deassertion of PERST# should be delayed 100ms (TPVPERL) for the power and clock to become stable. Link: https://lore.kernel.org/r/20211227133110.14500-1-qizhong.cheng@mediatek.com Signed-off-by: qizhong cheng <qizhong.cheng@mediatek.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Pali Rohár <pali@kernel.org>
2022-01-06PCI: mvebu: Add support for compiling driver as modulePali Rohár
Now when driver uses devm_pci_remap_iospace() function, it is possible implement ->remove() callback for unbinding device from driver. Implement mvebu_pcie_remove() callback with proper cleanup phase, drop driver's suppress_bind_attrs flag and switch type of CONFIG_PCI_MVEBU option from bool to tristate. This allows to compile pci-mvebu.c driver as loadable module pci-mvebu.ko with ability to unload it. Link: https://lore.kernel.org/r/20211126144307.7568-3-pali@kernel.org Signed-off-by: Pali Rohár <pali@kernel.org> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
2022-01-06bus: mvebu-mbus: Export symbols for public API window functionsPali Rohár
This would allow to compile pci-mvebu.c driver as module. Link: https://lore.kernel.org/r/20211126144307.7568-2-pali@kernel.org Signed-off-by: Pali Rohár <pali@kernel.org> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
2022-01-05PCI: layerscape: Change to use the DWC common link-up check functionHou Zhiqiang
The current Layerscape PCIe driver directly uses the physical layer LTSSM code to check the link-up state, which treats the > L0 states as link-up. This is not correct, since there is not explicit map between link-up state and LTSSM. So this patch changes to use the DWC common link-up check function. Link: https://lore.kernel.org/r/20211224094000.8513-1-Zhiqiang.Hou@nxp.com Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Rob Herring <robh@kernel.org>
2022-01-04PCI: mvebu: Fix support for DEVCAP2, DEVCTL2 and LNKCTL2 registers on ↵Pali Rohár
emulated bridge Armada XP and new hardware supports access to DEVCAP2, DEVCTL2 and LNKCTL2 configuration registers of PCIe core via PCIE_CAP_PCIEXP. So export them via emulated software root bridge. Pre-XP hardware does not support these registers and returns zeros. Link: https://lore.kernel.org/r/20211125124605.25915-16-pali@kernel.org Fixes: 1f08673eef12 ("PCI: mvebu: Convert to PCI emulated bridge config space") Signed-off-by: Pali Rohár <pali@kernel.org> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
2022-01-04PCI: mvebu: Fix support for PCI_EXP_RTSTA on emulated bridgePali Rohár
PME Status bit in Root Status Register (PCIE_RC_RTSTA_OFF) is read-only and can be cleared only by writing 0b to the Interrupt Cause RW0C register (PCIE_INT_CAUSE_OFF). Link: https://lore.kernel.org/r/20211125124605.25915-15-pali@kernel.org Fixes: 1f08673eef12 ("PCI: mvebu: Convert to PCI emulated bridge config space") Signed-off-by: Pali Rohár <pali@kernel.org> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
2022-01-04PCI: mvebu: Fix support for PCI_EXP_DEVCTL on emulated bridgePali Rohár
Comment in Armada 370 functional specification is misleading. PCI_EXP_DEVCTL_*RE bits are supported and configures receiving of error interrupts. Link: https://lore.kernel.org/r/20211125124605.25915-14-pali@kernel.org Fixes: 1f08673eef12 ("PCI: mvebu: Convert to PCI emulated bridge config space") Signed-off-by: Pali Rohár <pali@kernel.org> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
2022-01-04PCI: mvebu: Fix support for PCI_BRIDGE_CTL_BUS_RESET on emulated bridgePali Rohár
Hardware supports PCIe Hot Reset via PCIE_CTRL_OFF register. Use it for implementing PCI_BRIDGE_CTL_BUS_RESET bit of PCI_BRIDGE_CONTROL register on emulated bridge. With this change the function pci_reset_secondary_bus() starts working and can reset connected PCIe card. Link: https://lore.kernel.org/r/20211125124605.25915-13-pali@kernel.org Fixes: 1f08673eef12 ("PCI: mvebu: Convert to PCI emulated bridge config space") Signed-off-by: Pali Rohár <pali@kernel.org> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
generated by cgit-pink 1.4.1 (git 2.36.1) at 2024-10-13 00:22:11 +0000