diff options
Diffstat (limited to 'drivers/scsi/qla2xxx')
| -rw-r--r-- | drivers/scsi/qla2xxx/qla_attr.c | 33 | ||||
| -rw-r--r-- | drivers/scsi/qla2xxx/qla_dbg.c | 1114 | ||||
| -rw-r--r-- | drivers/scsi/qla2xxx/qla_dbg.h | 38 | ||||
| -rw-r--r-- | drivers/scsi/qla2xxx/qla_def.h | 22 | ||||
| -rw-r--r-- | drivers/scsi/qla2xxx/qla_fw.h | 36 | ||||
| -rw-r--r-- | drivers/scsi/qla2xxx/qla_gbl.h | 6 | ||||
| -rw-r--r-- | drivers/scsi/qla2xxx/qla_gs.c | 82 | ||||
| -rw-r--r-- | drivers/scsi/qla2xxx/qla_init.c | 136 | ||||
| -rw-r--r-- | drivers/scsi/qla2xxx/qla_inline.h | 4 | ||||
| -rw-r--r-- | drivers/scsi/qla2xxx/qla_iocb.c | 10 | ||||
| -rw-r--r-- | drivers/scsi/qla2xxx/qla_isr.c | 55 | ||||
| -rw-r--r-- | drivers/scsi/qla2xxx/qla_mbx.c | 58 | ||||
| -rw-r--r-- | drivers/scsi/qla2xxx/qla_os.c | 380 | ||||
| -rw-r--r-- | drivers/scsi/qla2xxx/qla_sup.c | 35 | ||||
| -rw-r--r-- | drivers/scsi/qla2xxx/qla_version.h | 2 |
15 files changed, 1503 insertions, 508 deletions
diff --git a/drivers/scsi/qla2xxx/qla_attr.c b/drivers/scsi/qla2xxx/qla_attr.c index 3eb2208675ae..1612f9200a52 100644 --- a/drivers/scsi/qla2xxx/qla_attr.c +++ b/drivers/scsi/qla2xxx/qla_attr.c @@ -98,7 +98,7 @@ qla2x00_sysfs_read_nvram(struct kobject *kobj, /* Read NVRAM. */ spin_lock_irqsave(&ha->hardware_lock, flags); - ha->isp_ops.read_nvram(ha, (uint8_t *)buf, ha->nvram_base, + ha->isp_ops->read_nvram(ha, (uint8_t *)buf, ha->nvram_base, ha->nvram_size); spin_unlock_irqrestore(&ha->hardware_lock, flags); @@ -119,7 +119,7 @@ qla2x00_sysfs_write_nvram(struct kobject *kobj, return 0; /* Checksum NVRAM. */ - if (IS_QLA24XX(ha) || IS_QLA54XX(ha)) { + if (IS_FWI2_CAPABLE(ha)) { uint32_t *iter; uint32_t chksum; @@ -143,7 +143,7 @@ qla2x00_sysfs_write_nvram(struct kobject *kobj, /* Write NVRAM. */ spin_lock_irqsave(&ha->hardware_lock, flags); - ha->isp_ops.write_nvram(ha, (uint8_t *)buf, ha->nvram_base, count); + ha->isp_ops->write_nvram(ha, (uint8_t *)buf, ha->nvram_base, count); spin_unlock_irqrestore(&ha->hardware_lock, flags); set_bit(ISP_ABORT_NEEDED, &ha->dpc_flags); @@ -206,7 +206,7 @@ static struct bin_attribute sysfs_optrom_attr = { .name = "optrom", .mode = S_IRUSR | S_IWUSR, }, - .size = OPTROM_SIZE_24XX, + .size = 0, .read = qla2x00_sysfs_read_optrom, .write = qla2x00_sysfs_write_optrom, }; @@ -252,7 +252,7 @@ qla2x00_sysfs_write_optrom_ctl(struct kobject *kobj, } memset(ha->optrom_buffer, 0, ha->optrom_size); - ha->isp_ops.read_optrom(ha, ha->optrom_buffer, 0, + ha->isp_ops->read_optrom(ha, ha->optrom_buffer, 0, ha->optrom_size); break; case 2: @@ -275,7 +275,7 @@ qla2x00_sysfs_write_optrom_ctl(struct kobject *kobj, if (ha->optrom_state != QLA_SWRITING) break; - ha->isp_ops.write_optrom(ha, ha->optrom_buffer, 0, + ha->isp_ops->write_optrom(ha, ha->optrom_buffer, 0, ha->optrom_size); break; } @@ -305,7 +305,8 @@ qla2x00_sysfs_read_vpd(struct kobject *kobj, /* Read NVRAM. */ spin_lock_irqsave(&ha->hardware_lock, flags); - ha->isp_ops.read_nvram(ha, (uint8_t *)buf, ha->vpd_base, ha->vpd_size); + ha->isp_ops->read_nvram(ha, (uint8_t *)buf, ha->vpd_base, + ha->vpd_size); spin_unlock_irqrestore(&ha->hardware_lock, flags); return ha->vpd_size; @@ -325,7 +326,7 @@ qla2x00_sysfs_write_vpd(struct kobject *kobj, /* Write NVRAM. */ spin_lock_irqsave(&ha->hardware_lock, flags); - ha->isp_ops.write_nvram(ha, (uint8_t *)buf, ha->vpd_base, count); + ha->isp_ops->write_nvram(ha, (uint8_t *)buf, ha->vpd_base, count); spin_unlock_irqrestore(&ha->hardware_lock, flags); return count; @@ -410,7 +411,7 @@ qla2x00_alloc_sysfs_attr(scsi_qla_host_t *ha) int ret; for (iter = bin_file_entries; iter->name; iter++) { - if (iter->is4GBp_only && (!IS_QLA24XX(ha) && !IS_QLA54XX(ha))) + if (iter->is4GBp_only && !IS_FWI2_CAPABLE(ha)) continue; ret = sysfs_create_bin_file(&host->shost_gendev.kobj, @@ -429,7 +430,7 @@ qla2x00_free_sysfs_attr(scsi_qla_host_t *ha) struct sysfs_entry *iter; for (iter = bin_file_entries; iter->name; iter++) { - if (iter->is4GBp_only && (!IS_QLA24XX(ha) && !IS_QLA54XX(ha))) + if (iter->is4GBp_only && !IS_FWI2_CAPABLE(ha)) continue; sysfs_remove_bin_file(&host->shost_gendev.kobj, @@ -437,7 +438,7 @@ qla2x00_free_sysfs_attr(scsi_qla_host_t *ha) } if (ha->beacon_blink_led == 1) - ha->isp_ops.beacon_off(ha); + ha->isp_ops->beacon_off(ha); } /* Scsi_Host attributes. */ @@ -455,7 +456,7 @@ qla2x00_fw_version_show(struct class_device *cdev, char *buf) char fw_str[30]; return snprintf(buf, PAGE_SIZE, "%s\n", - ha->isp_ops.fw_version_str(ha, fw_str)); + ha->isp_ops->fw_version_str(ha, fw_str)); } static ssize_t @@ -507,7 +508,7 @@ qla2x00_pci_info_show(struct class_device *cdev, char *buf) char pci_info[30]; return snprintf(buf, PAGE_SIZE, "%s\n", - ha->isp_ops.pci_info_str(ha, pci_info)); + ha->isp_ops->pci_info_str(ha, pci_info)); } static ssize_t @@ -652,9 +653,9 @@ qla2x00_beacon_store(struct class_device *cdev, const char *buf, return -EINVAL; if (val) - rval = ha->isp_ops.beacon_on(ha); + rval = ha->isp_ops->beacon_on(ha); else - rval = ha->isp_ops.beacon_off(ha); + rval = ha->isp_ops->beacon_off(ha); if (rval != QLA_SUCCESS) count = 0; @@ -898,7 +899,7 @@ qla2x00_get_fc_host_stats(struct Scsi_Host *shost) pfc_host_stat = &ha->fc_host_stat; memset(pfc_host_stat, -1, sizeof(struct fc_host_statistics)); - if (IS_QLA24XX(ha) || IS_QLA54XX(ha)) { + if (IS_FWI2_CAPABLE(ha)) { rval = qla24xx_get_isp_stats(ha, (uint32_t *)&stat_buf, sizeof(stat_buf) / 4, mb_stat); } else if (atomic_read(&ha->loop_state) == LOOP_READY && diff --git a/drivers/scsi/qla2xxx/qla_dbg.c b/drivers/scsi/qla2xxx/qla_dbg.c index 996c47a63074..563d18f4ff50 100644 --- a/drivers/scsi/qla2xxx/qla_dbg.c +++ b/drivers/scsi/qla2xxx/qla_dbg.c @@ -37,6 +37,121 @@ qla2xxx_copy_queues(scsi_qla_host_t *ha, void *ptr) return ptr + (ha->response_q_length * sizeof(response_t)); } +static int +qla2xxx_dump_memory(scsi_qla_host_t *ha, uint32_t *code_ram, + uint32_t cram_size, uint32_t *ext_mem, void **nxt) +{ + int rval; + uint32_t cnt, stat, timer, risc_address, ext_mem_cnt; + uint16_t mb[4]; + struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; + + rval = QLA_SUCCESS; + risc_address = ext_mem_cnt = 0; + memset(mb, 0, sizeof(mb)); + + /* Code RAM. */ + risc_address = 0x20000; + WRT_REG_WORD(®->mailbox0, MBC_READ_RAM_EXTENDED); + clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags); + + for (cnt = 0; cnt < cram_size / 4 && rval == QLA_SUCCESS; + cnt++, risc_address++) { + WRT_REG_WORD(®->mailbox1, LSW(risc_address)); + WRT_REG_WORD(®->mailbox8, MSW(risc_address)); + RD_REG_WORD(®->mailbox8); + WRT_REG_DWORD(®->hccr, HCCRX_SET_HOST_INT); + + for (timer = 6000000; timer; timer--) { + /* Check for pending interrupts. */ + stat = RD_REG_DWORD(®->host_status); + if (stat & HSRX_RISC_INT) { + stat &= 0xff; + + if (stat == 0x1 || stat == 0x2 || + stat == 0x10 || stat == 0x11) { + set_bit(MBX_INTERRUPT, + &ha->mbx_cmd_flags); + + mb[0] = RD_REG_WORD(®->mailbox0); + mb[2] = RD_REG_WORD(®->mailbox2); + mb[3] = RD_REG_WORD(®->mailbox3); + + WRT_REG_DWORD(®->hccr, + HCCRX_CLR_RISC_INT); + RD_REG_DWORD(®->hccr); + break; + } + + /* Clear this intr; it wasn't a mailbox intr */ + WRT_REG_DWORD(®->hccr, HCCRX_CLR_RISC_INT); + RD_REG_DWORD(®->hccr); + } + udelay(5); + } + + if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) { + rval = mb[0] & MBS_MASK; + code_ram[cnt] = htonl((mb[3] << 16) | mb[2]); + } else { + rval = QLA_FUNCTION_FAILED; + } + } + + if (rval == QLA_SUCCESS) { + /* External Memory. */ + risc_address = 0x100000; + ext_mem_cnt = ha->fw_memory_size - 0x100000 + 1; + WRT_REG_WORD(®->mailbox0, MBC_READ_RAM_EXTENDED); + clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags); + } + for (cnt = 0; cnt < ext_mem_cnt && rval == QLA_SUCCESS; + cnt++, risc_address++) { + WRT_REG_WORD(®->mailbox1, LSW(risc_address)); + WRT_REG_WORD(®->mailbox8, MSW(risc_address)); + RD_REG_WORD(®->mailbox8); + WRT_REG_DWORD(®->hccr, HCCRX_SET_HOST_INT); + + for (timer = 6000000; timer; timer--) { + /* Check for pending interrupts. */ + stat = RD_REG_DWORD(®->host_status); + if (stat & HSRX_RISC_INT) { + stat &= 0xff; + + if (stat == 0x1 || stat == 0x2 || + stat == 0x10 || stat == 0x11) { + set_bit(MBX_INTERRUPT, + &ha->mbx_cmd_flags); + + mb[0] = RD_REG_WORD(®->mailbox0); + mb[2] = RD_REG_WORD(®->mailbox2); + mb[3] = RD_REG_WORD(®->mailbox3); + + WRT_REG_DWORD(®->hccr, + HCCRX_CLR_RISC_INT); + RD_REG_DWORD(®->hccr); + break; + } + + /* Clear this intr; it wasn't a mailbox intr */ + WRT_REG_DWORD(®->hccr, HCCRX_CLR_RISC_INT); + RD_REG_DWORD(®->hccr); + } + udelay(5); + } + + if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) { + rval = mb[0] & MBS_MASK; + ext_mem[cnt] = htonl((mb[3] << 16) | mb[2]); + } else { + rval = QLA_FUNCTION_FAILED; + } + } + + *nxt = rval == QLA_SUCCESS ? &ext_mem[cnt]: NULL; + return rval; +} + /** * qla2300_fw_dump() - Dumps binary data from the 2300 firmware. * @ha: HA context @@ -633,11 +748,10 @@ void qla24xx_fw_dump(scsi_qla_host_t *ha, int hardware_locked) { int rval; - uint32_t cnt, timer; + uint32_t cnt; uint32_t risc_address; - uint16_t mb[4], wd; + uint16_t mb0, wd; - uint32_t stat; struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; uint32_t __iomem *dmp_reg; uint32_t *iter_reg; @@ -645,10 +759,9 @@ qla24xx_fw_dump(scsi_qla_host_t *ha, int hardware_locked) unsigned long flags; struct qla24xx_fw_dump *fw; uint32_t ext_mem_cnt; - void *eft; + void *nxt; risc_address = ext_mem_cnt = 0; - memset(mb, 0, sizeof(mb)); flags = 0; if (!hardware_locked) @@ -701,250 +814,236 @@ qla24xx_fw_dump(scsi_qla_host_t *ha, int hardware_locked) /* Shadow registers. */ WRT_REG_DWORD(®->iobase_addr, 0x0F70); RD_REG_DWORD(®->iobase_addr); - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xF0); - WRT_REG_DWORD(dmp_reg, 0xB0000000); - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xFC); - fw->shadow_reg[0] = htonl(RD_REG_DWORD(dmp_reg)); - - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xF0); - WRT_REG_DWORD(dmp_reg, 0xB0100000); - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xFC); - fw->shadow_reg[1] = htonl(RD_REG_DWORD(dmp_reg)); - - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xF0); - WRT_REG_DWORD(dmp_reg, 0xB0200000); - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xFC); - fw->shadow_reg[2] = htonl(RD_REG_DWORD(dmp_reg)); - - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xF0); - WRT_REG_DWORD(dmp_reg, 0xB0300000); - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xFC); - fw->shadow_reg[3] = htonl(RD_REG_DWORD(dmp_reg)); - - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xF0); - WRT_REG_DWORD(dmp_reg, 0xB0400000); - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xFC); - fw->shadow_reg[4] = htonl(RD_REG_DWORD(dmp_reg)); - - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xF0); - WRT_REG_DWORD(dmp_reg, 0xB0500000); - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xFC); - fw->shadow_reg[5] = htonl(RD_REG_DWORD(dmp_reg)); - - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xF0); - WRT_REG_DWORD(dmp_reg, 0xB0600000); - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xFC); - fw->shadow_reg[6] = htonl(RD_REG_DWORD(dmp_reg)); + WRT_REG_DWORD(®->iobase_select, 0xB0000000); + fw->shadow_reg[0] = htonl(RD_REG_DWORD(®->iobase_sdata)); + + WRT_REG_DWORD(®->iobase_select, 0xB0100000); + fw->shadow_reg[1] = htonl(RD_REG_DWORD(®->iobase_sdata)); + + WRT_REG_DWORD(®->iobase_select, 0xB0200000); + fw->shadow_reg[2] = htonl(RD_REG_DWORD(®->iobase_sdata)); + + WRT_REG_DWORD(®->iobase_select, 0xB0300000); + fw->shadow_reg[3] = htonl(RD_REG_DWORD(®->iobase_sdata)); + + WRT_REG_DWORD(®->iobase_select, 0xB0400000); + fw->shadow_reg[4] = htonl(RD_REG_DWORD(®->iobase_sdata)); + + WRT_REG_DWORD(®->iobase_select, 0xB0500000); + fw->shadow_reg[5] = htonl(RD_REG_DWORD(®->iobase_sdata)); + + WRT_REG_DWORD(®->iobase_select, 0xB0600000); + fw->shadow_reg[6] = htonl(RD_REG_DWORD(®->iobase_sdata)); /* Mailbox registers. */ - mbx_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80); + mbx_reg = ®->mailbox0; for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++) fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg++)); /* Transfer sequence registers. */ iter_reg = fw->xseq_gp_reg; WRT_REG_DWORD(®->iobase_addr, 0xBF00); - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); + dmp_reg = ®->iobase_window; for (cnt = 0; cnt < 16; cnt++) *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); WRT_REG_DWORD(®->iobase_addr, 0xBF10); - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); + dmp_reg = ®->iobase_window; for (cnt = 0; cnt < 16; cnt++) *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); WRT_REG_DWORD(®->iobase_addr, 0xBF20); - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); + dmp_reg = ®->iobase_window; for (cnt = 0; cnt < 16; cnt++) *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); WRT_REG_DWORD(®->iobase_addr, 0xBF30); - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); + dmp_reg = ®->iobase_window; for (cnt = 0; cnt < 16; cnt++) *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); WRT_REG_DWORD(®->iobase_addr, 0xBF40); - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); + dmp_reg = ®->iobase_window; for (cnt = 0; cnt < 16; cnt++) *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); WRT_REG_DWORD(®->iobase_addr, 0xBF50); - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); + dmp_reg = ®->iobase_window; for (cnt = 0; cnt < 16; cnt++) *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); WRT_REG_DWORD(®->iobase_addr, 0xBF60); - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); + dmp_reg = ®->iobase_window; for (cnt = 0; cnt < 16; cnt++) *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); WRT_REG_DWORD(®->iobase_addr, 0xBF70); - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); + dmp_reg = ®->iobase_window; for (cnt = 0; cnt < 16; cnt++) *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); WRT_REG_DWORD(®->iobase_addr, 0xBFE0); - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); + dmp_reg = ®->iobase_window; for (cnt = 0; cnt < sizeof(fw->xseq_0_reg) / 4; cnt++) fw->xseq_0_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++)); WRT_REG_DWORD(®->iobase_addr, 0xBFF0); - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); + dmp_reg = ®->iobase_window; for (cnt = 0; cnt < sizeof(fw->xseq_1_reg) / 4; cnt++) fw->xseq_1_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++)); /* Receive sequence registers. */ iter_reg = fw->rseq_gp_reg; WRT_REG_DWORD(®->iobase_addr, 0xFF00); - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); + dmp_reg = ®->iobase_window; for (cnt = 0; cnt < 16; cnt++) *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); WRT_REG_DWORD(®->iobase_addr, 0xFF10); - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); + dmp_reg = ®->iobase_window; for (cnt = 0; cnt < 16; cnt++) *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); WRT_REG_DWORD(®->iobase_addr, 0xFF20); - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); + dmp_reg = ®->iobase_window; for (cnt = 0; cnt < 16; cnt++) *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); WRT_REG_DWORD(®->iobase_addr, 0xFF30); - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); + dmp_reg = ®->iobase_window; for (cnt = 0; cnt < 16; cnt++) *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); WRT_REG_DWORD(®->iobase_addr, 0xFF40); - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); + dmp_reg = ®->iobase_window; for (cnt = 0; cnt < 16; cnt++) *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); WRT_REG_DWORD(®->iobase_addr, 0xFF50); - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); + dmp_reg = ®->iobase_window; for (cnt = 0; cnt < 16; cnt++) *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); WRT_REG_DWORD(®->iobase_addr, 0xFF60); - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); + dmp_reg = ®->iobase_window; for (cnt = 0; cnt < 16; cnt++) *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); WRT_REG_DWORD(®->iobase_addr, 0xFF70); - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); + dmp_reg = ®->iobase_window; for (cnt = 0; cnt < 16; cnt++) *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); WRT_REG_DWORD(®->iobase_addr, 0xFFD0); - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); + dmp_reg = ®->iobase_window; for (cnt = 0; cnt < sizeof(fw->rseq_0_reg) / 4; cnt++) fw->rseq_0_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++)); WRT_REG_DWORD(®->iobase_addr, 0xFFE0); - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); + dmp_reg = ®->iobase_window; for (cnt = 0; cnt < sizeof(fw->rseq_1_reg) / 4; cnt++) fw->rseq_1_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++)); WRT_REG_DWORD(®->iobase_addr, 0xFFF0); - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); + dmp_reg = ®->iobase_window; for (cnt = 0; cnt < sizeof(fw->rseq_2_reg) / 4; cnt++) fw->rseq_2_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++)); /* Command DMA registers. */ WRT_REG_DWORD(®->iobase_addr, 0x7100); - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); + dmp_reg = ®->iobase_window; for (cnt = 0; cnt < sizeof(fw->cmd_dma_reg) / 4; cnt++) fw->cmd_dma_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++)); /* Queues. */ iter_reg = fw->req0_dma_reg; WRT_REG_DWORD(®->iobase_addr, 0x7200); - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); + dmp_reg = ®->iobase_window; for (cnt = 0; cnt < 8; cnt++) *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xE4); + dmp_reg = ®->iobase_q; for (cnt = 0; cnt < 7; cnt++) *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); iter_reg = fw->resp0_dma_reg; WRT_REG_DWORD(®->iobase_addr, 0x7300); - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); + dmp_reg = ®->iobase_window; for (cnt = 0; cnt < 8; cnt++) *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xE4); + dmp_reg = ®->iobase_q; for (cnt = 0; cnt < 7; cnt++) *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); iter_reg = fw->req1_dma_reg; WRT_REG_DWORD(®->iobase_addr, 0x7400); - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); + dmp_reg = ®->iobase_window; for (cnt = 0; cnt < 8; cnt++) *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xE4); + dmp_reg = ®->iobase_q; for (cnt = 0; cnt < 7; cnt++) *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); /* Transmit DMA registers. */ iter_reg = fw->xmt0_dma_reg; WRT_REG_DWORD(®->iobase_addr, 0x7600); - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); + dmp_reg = ®->iobase_window; for (cnt = 0; cnt < 16; cnt++) *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); WRT_REG_DWORD(®->iobase_addr, 0x7610); - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); + dmp_reg = ®->iobase_window; for (cnt = 0; cnt < 16; cnt++) *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); iter_reg = fw->xmt1_dma_reg; WRT_REG_DWORD(®->iobase_addr, 0x7620); - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); + dmp_reg = ®->iobase_window; for (cnt = 0; cnt < 16; cnt++) *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); WRT_REG_DWORD(®->iobase_addr, 0x7630); - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); + dmp_reg = ®->iobase_window; for (cnt = 0; cnt < 16; cnt++) *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); iter_reg = fw->xmt2_dma_reg; WRT_REG_DWORD(®->iobase_addr, 0x7640); - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); + dmp_reg = ®->iobase_window; for (cnt = 0; cnt < 16; cnt++) *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); WRT_REG_DWORD(®->iobase_addr, 0x7650); - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); + dmp_reg = ®->iobase_window; for (cnt = 0; cnt < 16; cnt++) *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); iter_reg = fw->xmt3_dma_reg; WRT_REG_DWORD(®->iobase_addr, 0x7660); - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); + dmp_reg = ®->iobase_window; for (cnt = 0; cnt < 16; cnt++) *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); WRT_REG_DWORD(®->iobase_addr, 0x7670); - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); + dmp_reg = ®->iobase_window; for (cnt = 0; cnt < 16; cnt++) *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); iter_reg = fw->xmt4_dma_reg; WRT_REG_DWORD(®->iobase_addr, 0x7680); - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); + dmp_reg = ®->iobase_window; for (cnt = 0; cnt < 16; cnt++) *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); WRT_REG_DWORD(®->iobase_addr, 0x7690); - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); + dmp_reg = ®->iobase_window; for (cnt = 0; cnt < 16; cnt++) *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); WRT_REG_DWORD(®->iobase_addr, 0x76A0); - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); + dmp_reg = ®->iobase_window; for (cnt = 0; cnt < sizeof(fw->xmt_data_dma_reg) / 4; cnt++) fw->xmt_data_dma_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++)); @@ -952,221 +1051,221 @@ qla24xx_fw_dump(scsi_qla_host_t *ha, int hardware_locked) /* Receive DMA registers. */ iter_reg = fw->rcvt0_data_dma_reg; WRT_REG_DWORD(®->iobase_addr, 0x7700); - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); + dmp_reg = ®->iobase_window; for (cnt = 0; cnt < 16; cnt++) *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); WRT_REG_DWORD(®->iobase_addr, 0x7710); - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); + dmp_reg = ®->iobase_window; for (cnt = 0; cnt < 16; cnt++) *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); iter_reg = fw->rcvt1_data_dma_reg; WRT_REG_DWORD(®->iobase_addr, 0x7720); - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); + dmp_reg = ®->iobase_window; for (cnt = 0; cnt < 16; cnt++) *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); WRT_REG_DWORD(®->iobase_addr, 0x7730); - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); + dmp_reg = ®->iobase_window; for (cnt = 0; cnt < 16; cnt++) *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); /* RISC registers. */ iter_reg = fw->risc_gp_reg; WRT_REG_DWORD(®->iobase_addr, 0x0F00); - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); + dmp_reg = ®->iobase_window; for (cnt = 0; cnt < 16; cnt++) *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); WRT_REG_DWORD(®->iobase_addr, 0x0F10); - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); + dmp_reg = ®->iobase_window; for (cnt = 0; cnt < 16; cnt++) *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); WRT_REG_DWORD(®->iobase_addr, 0x0F20); - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); + dmp_reg = ®->iobase_window; for (cnt = 0; cnt < 16; cnt++) *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); WRT_REG_DWORD(®->iobase_addr, 0x0F30); - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); + dmp_reg = ®->iobase_window; for (cnt = 0; cnt < 16; cnt++) *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); WRT_REG_DWORD(®->iobase_addr, 0x0F40); - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); + dmp_reg = ®->iobase_window; for (cnt = 0; cnt < 16; cnt++) *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); WRT_REG_DWORD(®->iobase_addr, 0x0F50); - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); + dmp_reg = ®->iobase_window; for (cnt = 0; cnt < 16; cnt++) *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); WRT_REG_DWORD(®->iobase_addr, 0x0F60); - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); + dmp_reg = ®->iobase_window; for (cnt = 0; cnt < 16; cnt++) *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); WRT_REG_DWORD(®->iobase_addr, 0x0F70); - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); + dmp_reg = ®->iobase_window; for (cnt = 0; cnt < 16; cnt++) *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); /* Local memory controller registers. */ iter_reg = fw->lmc_reg; WRT_REG_DWORD(®->iobase_addr, 0x3000); - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); + dmp_reg = ®->iobase_window; for (cnt = 0; cnt < 16; cnt++) *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); WRT_REG_DWORD(®->iobase_addr, 0x3010); - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); + dmp_reg = ®->iobase_window; for (cnt = 0; cnt < 16; cnt++) *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); WRT_REG_DWORD(®->iobase_addr, 0x3020); - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); + dmp_reg = ®->iobase_window; for (cnt = 0; cnt < 16; cnt++) *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); WRT_REG_DWORD(®->iobase_addr, 0x3030); - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); + dmp_reg = ®->iobase_window; for (cnt = 0; cnt < 16; cnt++) *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); WRT_REG_DWORD(®->iobase_addr, 0x3040); - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); + dmp_reg = ®->iobase_window; for (cnt = 0; cnt < 16; cnt++) *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); WRT_REG_DWORD(®->iobase_addr, 0x3050); - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); + dmp_reg = ®->iobase_window; for (cnt = 0; cnt < 16; cnt++) *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); WRT_REG_DWORD(®->iobase_addr, 0x3060); - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); + dmp_reg = ®->iobase_window; for (cnt = 0; cnt < 16; cnt++) *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); /* Fibre Protocol Module registers. */ iter_reg = fw->fpm_hdw_reg; WRT_REG_DWORD(®->iobase_addr, 0x4000); - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); + dmp_reg = ®->iobase_window; for (cnt = 0; cnt < 16; cnt++) *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); WRT_REG_DWORD(®->iobase_addr, 0x4010); - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); + dmp_reg = ®->iobase_window; for (cnt = 0; cnt < 16; cnt++) *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); WRT_REG_DWORD(®->iobase_addr, 0x4020); - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); + dmp_reg = ®->iobase_window; for (cnt = 0; cnt < 16; cnt++) *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); WRT_REG_DWORD(®->iobase_addr, 0x4030); - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); + dmp_reg = ®->iobase_window; for (cnt = 0; cnt < 16; cnt++) *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); WRT_REG_DWORD(®->iobase_addr, 0x4040); - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); + dmp_reg = ®->iobase_window; for (cnt = 0; cnt < 16; cnt++) *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); WRT_REG_DWORD(®->iobase_addr, 0x4050); - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); + dmp_reg = ®->iobase_window; for (cnt = 0; cnt < 16; cnt++) *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); WRT_REG_DWORD(®->iobase_addr, 0x4060); - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); + dmp_reg = ®->iobase_window; for (cnt = 0; cnt < 16; cnt++) *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); WRT_REG_DWORD(®->iobase_addr, 0x4070); - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); + dmp_reg = ®->iobase_window; for (cnt = 0; cnt < 16; cnt++) *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); WRT_REG_DWORD(®->iobase_addr, 0x4080); - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); + dmp_reg = ®->iobase_window; for (cnt = 0; cnt < 16; cnt++) *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); WRT_REG_DWORD(®->iobase_addr, 0x4090); - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); + dmp_reg = ®->iobase_window; for (cnt = 0; cnt < 16; cnt++) *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); WRT_REG_DWORD(®->iobase_addr, 0x40A0); - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); + dmp_reg = ®->iobase_window; for (cnt = 0; cnt < 16; cnt++) *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); WRT_REG_DWORD(®->iobase_addr, 0x40B0); - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); + dmp_reg = ®->iobase_window; for (cnt = 0; cnt < 16; cnt++) *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); /* Frame Buffer registers. */ iter_reg = fw->fb_hdw_reg; WRT_REG_DWORD(®->iobase_addr, 0x6000); - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); + dmp_reg = ®->iobase_window; for (cnt = 0; cnt < 16; cnt++) *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); WRT_REG_DWORD(®->iobase_addr, 0x6010); - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); + dmp_reg = ®->iobase_window; for (cnt = 0; cnt < 16; cnt++) *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); WRT_REG_DWORD(®->iobase_addr, 0x6020); - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); + dmp_reg = ®->iobase_window; for (cnt = 0; cnt < 16; cnt++) *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); WRT_REG_DWORD(®->iobase_addr, 0x6030); - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); + dmp_reg = ®->iobase_window; for (cnt = 0; cnt < 16; cnt++) *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); WRT_REG_DWORD(®->iobase_addr, 0x6040); - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); + dmp_reg = ®->iobase_window; for (cnt = 0; cnt < 16; cnt++) *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); WRT_REG_DWORD(®->iobase_addr, 0x6100); - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); + dmp_reg = ®->iobase_window; for (cnt = 0; cnt < 16; cnt++) *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); WRT_REG_DWORD(®->iobase_addr, 0x6130); - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); + dmp_reg = ®->iobase_window; for (cnt = 0; cnt < 16; cnt++) *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); WRT_REG_DWORD(®->iobase_addr, 0x6150); - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); + dmp_reg = ®->iobase_window; for (cnt = 0; cnt < 16; cnt++) *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); WRT_REG_DWORD(®->iobase_addr, 0x6170); - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); + dmp_reg = ®->iobase_window; for (cnt = 0; cnt < 16; cnt++) *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); WRT_REG_DWORD(®->iobase_addr, 0x6190); - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); + dmp_reg = ®->iobase_window; for (cnt = 0; cnt < 16; cnt++) *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); WRT_REG_DWORD(®->iobase_addr, 0x61B0); - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); + dmp_reg = ®->iobase_window; for (cnt = 0; cnt < 16; cnt++) *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); @@ -1187,10 +1286,10 @@ qla24xx_fw_dump(scsi_qla_host_t *ha, int hardware_locked) udelay(100); /* Wait for firmware to complete NVRAM accesses. */ - mb[0] = (uint32_t) RD_REG_WORD(®->mailbox0); - for (cnt = 10000 ; cnt && mb[0]; cnt--) { + mb0 = (uint32_t) RD_REG_WORD(®->mailbox0); + for (cnt = 10000 ; cnt && mb0; cnt--) { udelay(5); - mb[0] = (uint32_t) RD_REG_WORD(®->mailbox0); + mb0 = (uint32_t) RD_REG_WORD(®->mailbox0); barrier(); } @@ -1214,110 +1313,717 @@ qla24xx_fw_dump(scsi_qla_host_t *ha, int hardware_locked) rval = QLA_FUNCTION_TIMEOUT; } - /* Memory. */ + if (rval == QLA_SUCCESS) + rval = qla2xxx_dump_memory(ha, fw->code_ram, + sizeof(fw->code_ram), fw->ext_mem, &nxt); + if (rval == QLA_SUCCESS) { - /* Code RAM. */ - risc_address = 0x20000; - WRT_REG_WORD(®->mailbox0, MBC_READ_RAM_EXTENDED); - clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags); + nxt = qla2xxx_copy_queues(ha, nxt); + if (ha->eft) + memcpy(nxt, ha->eft, ntohl(ha->fw_dump->eft_size)); } - for (cnt = 0; cnt < sizeof(fw->code_ram) / 4 && rval == QLA_SUCCESS; - cnt++, risc_address++) { - WRT_REG_WORD(®->mailbox1, LSW(risc_address)); - WRT_REG_WORD(®->mailbox8, MSW(risc_address)); - RD_REG_WORD(®->mailbox8); - WRT_REG_DWORD(®->hccr, HCCRX_SET_HOST_INT); - for (timer = 6000000; timer; timer--) { - /* Check for pending interrupts. */ - stat = RD_REG_DWORD(®->host_status); - if (stat & HSRX_RISC_INT) { - stat &= 0xff; + if (rval != QLA_SUCCESS) { + qla_printk(KERN_WARNING, ha, + "Failed to dump firmware (%x)!!!\n", rval); + ha->fw_dumped = 0; - if (stat == 0x1 || stat == 0x2 || - stat == 0x10 || stat == 0x11) { - set_bit(MBX_INTERRUPT, - &ha->mbx_cmd_flags); + } else { + qla_printk(KERN_INFO, ha, + "Firmware dump saved to temp buffer (%ld/%p).\n", + ha->host_no, ha->fw_dump); + ha->fw_dumped = 1; + } - mb[0] = RD_REG_WORD(®->mailbox0); - mb[2] = RD_REG_WORD(®->mailbox2); - mb[3] = RD_REG_WORD(®->mailbox3); +qla24xx_fw_dump_failed: + if (!hardware_locked) + spin_unlock_irqrestore(&ha->hardware_lock, flags); +} - WRT_REG_DWORD(®->hccr, - HCCRX_CLR_RISC_INT); - RD_REG_DWORD(®->hccr); - break; - } +void +qla25xx_fw_dump(scsi_qla_host_t *ha, int hardware_locked) +{ + int rval; + uint32_t cnt; + uint32_t risc_address; + uint16_t mb0, wd; - /* Clear this intr; it wasn't a mailbox intr */ - WRT_REG_DWORD(®->hccr, HCCRX_CLR_RISC_INT); - RD_REG_DWORD(®->hccr); - } - udelay(5); - } + struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; + uint32_t __iomem *dmp_reg; + uint32_t *iter_reg; + uint16_t __iomem *mbx_reg; + unsigned long flags; + struct qla25xx_fw_dump *fw; + uint32_t ext_mem_cnt; + void *nxt; - if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) { - rval = mb[0] & MBS_MASK; - fw->code_ram[cnt] = htonl((mb[3] << 16) | mb[2]); - } else { - rval = QLA_FUNCTION_FAILED; + risc_address = ext_mem_cnt = 0; + flags = 0; + + if (!hardware_locked) + spin_lock_irqsave(&ha->hardware_lock, flags); + + if (!ha->fw_dump) { + qla_printk(KERN_WARNING, ha, + "No buffer available for dump!!!\n"); + goto qla25xx_fw_dump_failed; + } + + if (ha->fw_dumped) { + qla_printk(KERN_WARNING, ha, + "Firmware has been previously dumped (%p) -- ignoring " + "request...\n", ha->fw_dump); + goto qla25xx_fw_dump_failed; + } + fw = &ha->fw_dump->isp.isp25; + qla2xxx_prep_dump(ha, ha->fw_dump); + + rval = QLA_SUCCESS; + fw->host_status = htonl(RD_REG_DWORD(®->host_status)); + + /* Pause RISC. */ + if ((RD_REG_DWORD(®->hccr) & HCCRX_RISC_PAUSE) == 0) { + WRT_REG_DWORD(®->hccr, HCCRX_SET_RISC_RESET | + HCCRX_CLR_HOST_INT); + RD_REG_DWORD(®->hccr); /* PCI Posting. */ + WRT_REG_DWORD(®->hccr, HCCRX_SET_RISC_PAUSE); + for (cnt = 30000; + (RD_REG_DWORD(®->hccr) & HCCRX_RISC_PAUSE) == 0 && + rval == QLA_SUCCESS; cnt--) { + if (cnt) + udelay(100); + else + rval = QLA_FUNCTION_TIMEOUT; } } if (rval == QLA_SUCCESS) { - /* External Memory. */ - risc_address = 0x100000; - ext_mem_cnt = ha->fw_memory_size - 0x100000 + 1; - WRT_REG_WORD(®->mailbox0, MBC_READ_RAM_EXTENDED); - clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags); - } - for (cnt = 0; cnt < ext_mem_cnt && rval == QLA_SUCCESS; - cnt++, risc_address++) { - WRT_REG_WORD(®->mailbox1, LSW(risc_address)); - WRT_REG_WORD(®->mailbox8, MSW(risc_address)); - RD_REG_WORD(®->mailbox8); - WRT_REG_DWORD(®->hccr, HCCRX_SET_HOST_INT); + /* Host interface registers. */ + dmp_reg = (uint32_t __iomem *)(reg + 0); + for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++) + fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++)); - for (timer = 6000000; timer; timer--) { - /* Check for pending interrupts. */ - stat = RD_REG_DWORD(®->host_status); - if (stat & HSRX_RISC_INT) { - stat &= 0xff; + /* Disable interrupts. */ + WRT_REG_DWORD(®->ictrl, 0); + RD_REG_DWORD(®->ictrl); - if (stat == 0x1 || stat == 0x2 || - stat == 0x10 || stat == 0x11) { - set_bit(MBX_INTERRUPT, - &ha->mbx_cmd_flags); + /* Shadow registers. */ + WRT_REG_DWORD(®->iobase_addr, 0x0F70); + RD_REG_DWORD(®->iobase_addr); + WRT_REG_DWORD(®->iobase_select, 0xB0000000); + fw->shadow_reg[0] = htonl(RD_REG_DWORD(®->iobase_sdata)); - mb[0] = RD_REG_WORD(®->mailbox0); - mb[2] = RD_REG_WORD(®->mailbox2); - mb[3] = RD_REG_WORD(®->mailbox3); + WRT_REG_DWORD(®->iobase_select, 0xB0100000); + fw->shadow_reg[1] = htonl(RD_REG_DWORD(®->iobase_sdata)); - WRT_REG_DWORD(®->hccr, - HCCRX_CLR_RISC_INT); - RD_REG_DWORD(®->hccr); - break; - } + WRT_REG_DWORD(®->iobase_select, 0xB0200000); + fw->shadow_reg[2] = htonl(RD_REG_DWORD(®->iobase_sdata)); - /* Clear this intr; it wasn't a mailbox intr */ - WRT_REG_DWORD(®->hccr, HCCRX_CLR_RISC_INT); - RD_REG_DWORD(®->hccr); - } + WRT_REG_DWORD(®->iobase_select, 0xB0300000); + fw->shadow_reg[3] = htonl(RD_REG_DWORD(®->iobase_sdata)); + + WRT_REG_DWORD(®->iobase_select, 0xB0400000); + fw->shadow_reg[4] = htonl(RD_REG_DWORD(®->iobase_sdata)); + + WRT_REG_DWORD(®->iobase_select, 0xB0500000); + fw->shadow_reg[5] = htonl(RD_REG_DWORD(®->iobase_sdata)); + + WRT_REG_DWORD(®->iobase_select, 0xB0600000); + fw->shadow_reg[6] = htonl(RD_REG_DWORD(®->iobase_sdata)); + + WRT_REG_DWORD(®->iobase_select, 0xB0700000); + fw->shadow_reg[7] = htonl(RD_REG_DWORD(®->iobase_sdata)); + + WRT_REG_DWORD(®->iobase_select, 0xB0800000); + fw->shadow_reg[8] = htonl(RD_REG_DWORD(®->iobase_sdata)); + + WRT_REG_DWORD(®->iobase_select, 0xB0900000); + fw->shadow_reg[9] = htonl(RD_REG_DWORD(®->iobase_sdata)); + + WRT_REG_DWORD(®->iobase_select, 0xB0A00000); + fw->shadow_reg[10] = htonl(RD_REG_DWORD(®->iobase_sdata)); + + /* RISC I/O register. */ + WRT_REG_DWORD(®->iobase_addr, 0x0010); + RD_REG_DWORD(®->iobase_addr); + fw->risc_io_reg = htonl(RD_REG_DWORD(®->iobase_window)); + + /* Mailbox registers. */ + mbx_reg = ®->mailbox0; + for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++) + fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg++)); + + /* Transfer sequence registers. */ + iter_reg = fw->xseq_gp_reg; + WRT_REG_DWORD(®->iobase_addr, 0xBF00); + dmp_reg = ®->iobase_window; + for (cnt = 0; cnt < 16; cnt++) + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); + + WRT_REG_DWORD(®->iobase_addr, 0xBF10); + dmp_reg = ®->iobase_window; + for (cnt = 0; cnt < 16; cnt++) + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); + + WRT_REG_DWORD(®->iobase_addr, 0xBF20); + dmp_reg = ®->iobase_window; + for (cnt = 0; cnt < 16; cnt++) + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); + + WRT_REG_DWORD(®->iobase_addr, 0xBF30); + dmp_reg = ®->iobase_window; + for (cnt = 0; cnt < 16; cnt++) + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); + + WRT_REG_DWORD(®->iobase_addr, 0xBF40); + dmp_reg = ®->iobase_window; + for (cnt = 0; cnt < 16; cnt++) + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); + + WRT_REG_DWORD(®->iobase_addr, 0xBF50); + dmp_reg = ®->iobase_window; + for (cnt = 0; cnt < 16; cnt++) + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); + + WRT_REG_DWORD(®->iobase_addr, 0xBF60); + dmp_reg = ®->iobase_window; + for (cnt = 0; cnt < 16; cnt++) + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); + + WRT_REG_DWORD(®->iobase_addr, 0xBF70); + dmp_reg = ®->iobase_window; + for (cnt = 0; cnt < 16; cnt++) + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); + + iter_reg = fw->xseq_0_reg; + WRT_REG_DWORD(®->iobase_addr, 0xBFC0); + dmp_reg = ®->iobase_window; + for (cnt = 0; cnt < 16; cnt++) + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); + + WRT_REG_DWORD(®->iobase_addr, 0xBFD0); + dmp_reg = ®->iobase_window; + for (cnt = 0; cnt < 16; cnt++) + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); + + WRT_REG_DWORD(®->iobase_addr, 0xBFE0); + dmp_reg = ®->iobase_window; + for (cnt = 0; cnt < 16; cnt++) + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); + + WRT_REG_DWORD(®->iobase_addr, 0xBFF0); + dmp_reg = ®->iobase_window; + for (cnt = 0; cnt < sizeof(fw->xseq_1_reg) / 4; cnt++) + fw->xseq_1_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++)); + + /* Receive sequence registers. */ + iter_reg = fw->rseq_gp_reg; + WRT_REG_DWORD(®->iobase_addr, 0xFF00); + dmp_reg = ®->iobase_window; + for (cnt = 0; cnt < 16; cnt++) + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); + + WRT_REG_DWORD(®->iobase_addr, 0xFF10); + dmp_reg = ®->iobase_window; + for (cnt = 0; cnt < 16; cnt++) + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); + + WRT_REG_DWORD(®->iobase_addr, 0xFF20); + dmp_reg = ®->iobase_window; + for (cnt = 0; cnt < 16; cnt++) + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); + + WRT_REG_DWORD(®->iobase_addr, 0xFF30); + dmp_reg = ®->iobase_window; + for (cnt = 0; cnt < 16; cnt++) + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); + + WRT_REG_DWORD(®->iobase_addr, 0xFF40); + dmp_reg = ®->iobase_window; + for (cnt = 0; cnt < 16; cnt++) + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); + + WRT_REG_DWORD(®->iobase_addr, 0xFF50); + dmp_reg = ®->iobase_window; + for (cnt = 0; cnt < 16; cnt++) + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); + + WRT_REG_DWORD(®->iobase_addr, 0xFF60); + dmp_reg = ®->iobase_window; + for (cnt = 0; cnt < 16; cnt++) + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); + + WRT_REG_DWORD(®->iobase_addr, 0xFF70); + dmp_reg = ®->iobase_window; + for (cnt = 0; cnt < 16; cnt++) + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); + + iter_reg = fw->rseq_0_reg; + WRT_REG_DWORD(®->iobase_addr, 0xFFC0); + dmp_reg = ®->iobase_window; + for (cnt = 0; cnt < 16; cnt++) + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); + + WRT_REG_DWORD(®->iobase_addr, 0xFFD0); + dmp_reg = ®->iobase_window; + for (cnt = 0; cnt < 16; cnt++) + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); + + WRT_REG_DWORD(®->iobase_addr, 0xFFE0); + dmp_reg = ®->iobase_window; + for (cnt = 0; cnt < sizeof(fw->rseq_1_reg) / 4; cnt++) + fw->rseq_1_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++)); + + WRT_REG_DWORD(®->iobase_addr, 0xFFF0); + dmp_reg = ®->iobase_window; + for (cnt = 0; cnt < sizeof(fw->rseq_2_reg) / 4; cnt++) + fw->rseq_2_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++)); + + /* Auxiliary sequence registers. */ + iter_reg = fw->aseq_gp_reg; + WRT_REG_DWORD(®->iobase_addr, 0xB000); + dmp_reg = ®->iobase_window; + for (cnt = 0; cnt < 16; cnt++) + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); + + WRT_REG_DWORD(®->iobase_addr, 0xB010); + dmp_reg = ®->iobase_window; + for (cnt = 0; cnt < 16; cnt++) + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); + + WRT_REG_DWORD(®->iobase_addr, 0xB020); + dmp_reg = ®->iobase_window; + for (cnt = 0; cnt < 16; cnt++) + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); + + WRT_REG_DWORD(®->iobase_addr, 0xB030); + dmp_reg = ®->iobase_window; + for (cnt = 0; cnt < 16; cnt++) + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); + + WRT_REG_DWORD(®->iobase_addr, 0xB040); + dmp_reg = ®->iobase_window; + for (cnt = 0; cnt < 16; cnt++) + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); + + WRT_REG_DWORD(®->iobase_addr, 0xB050); + dmp_reg = ®->iobase_window; + for (cnt = 0; cnt < 16; cnt++) + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); + + WRT_REG_DWORD(®->iobase_addr, 0xB060); + dmp_reg = ®->iobase_window; + for (cnt = 0; cnt < 16; cnt++) + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); + + WRT_REG_DWORD(®->iobase_addr, 0xB070); + dmp_reg = ®->iobase_window; + for (cnt = 0; cnt < 16; cnt++) + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); + + iter_reg = fw->aseq_0_reg; + WRT_REG_DWORD(®->iobase_addr, 0xB0C0); + dmp_reg = ®->iobase_window; + for (cnt = 0; cnt < 16; cnt++) + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); + + WRT_REG_DWORD(®->iobase_addr, 0xB0D0); + dmp_reg = ®->iobase_window; + for (cnt = 0; cnt < 16; cnt++) + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); + + WRT_REG_DWORD(®->iobase_addr, 0xB0E0); + dmp_reg = ®->iobase_window; + for (cnt = 0; cnt < sizeof(fw->aseq_1_reg) / 4; cnt++) + fw->aseq_1_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++)); + + WRT_REG_DWORD(®->iobase_addr, 0xB0F0); + dmp_reg = ®->iobase_window; + for (cnt = 0; cnt < sizeof(fw->aseq_2_reg) / 4; cnt++) + fw->aseq_2_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++)); + + /* Command DMA registers. */ + WRT_REG_DWORD(®->iobase_addr, 0x7100); + dmp_reg = ®->iobase_window; + for (cnt = 0; cnt < sizeof(fw->cmd_dma_reg) / 4; cnt++) + fw->cmd_dma_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++)); + + /* Queues. */ + iter_reg = fw->req0_dma_reg; + WRT_REG_DWORD(®->iobase_addr, 0x7200); + dmp_reg = ®->iobase_window; + for (cnt = 0; cnt < 8; cnt++) + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); + + dmp_reg = ®->iobase_q; + for (cnt = 0; cnt < 7; cnt++) + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); + + iter_reg = fw->resp0_dma_reg; + WRT_REG_DWORD(®->iobase_addr, 0x7300); + dmp_reg = ®->iobase_window; + for (cnt = 0; cnt < 8; cnt++) + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); + + dmp_reg = ®->iobase_q; + for (cnt = 0; cnt < 7; cnt++) + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); + + iter_reg = fw->req1_dma_reg; + WRT_REG_DWORD(®->iobase_addr, 0x7400); + dmp_reg = ®->iobase_window; + for (cnt = 0; cnt < 8; cnt++) + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); + + dmp_reg = ®->iobase_q; + for (cnt = 0; cnt < 7; cnt++) + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); + + /* Transmit DMA registers. */ + iter_reg = fw->xmt0_dma_reg; + WRT_REG_DWORD(®->iobase_addr, 0x7600); + dmp_reg = ®->iobase_window; + for (cnt = 0; cnt < 16; cnt++) + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); + + WRT_REG_DWORD(®->iobase_addr, 0x7610); + dmp_reg = ®->iobase_window; + for (cnt = 0; cnt < 16; cnt++) + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); + + iter_reg = fw->xmt1_dma_reg; + WRT_REG_DWORD(®->iobase_addr, 0x7620); + dmp_reg = ®->iobase_window; + for (cnt = 0; cnt < 16; cnt++) + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); + + WRT_REG_DWORD(®->iobase_addr, 0x7630); + dmp_reg = ®->iobase_window; + for (cnt = 0; cnt < 16; cnt++) + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); + + iter_reg = fw->xmt2_dma_reg; + WRT_REG_DWORD(®->iobase_addr, 0x7640); + dmp_reg = ®->iobase_window; + for (cnt = 0; cnt < 16; cnt++) + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); + + WRT_REG_DWORD(®->iobase_addr, 0x7650); + dmp_reg = ®->iobase_window; + for (cnt = 0; cnt < 16; cnt++) + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); + + iter_reg = fw->xmt3_dma_reg; + WRT_REG_DWORD(®->iobase_addr, 0x7660); + dmp_reg = ®->iobase_window; + for (cnt = 0; cnt < 16; cnt++) + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); + + WRT_REG_DWORD(®->iobase_addr, 0x7670); + dmp_reg = ®->iobase_window; + for (cnt = 0; cnt < 16; cnt++) + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); + + iter_reg = fw->xmt4_dma_reg; + WRT_REG_DWORD(®->iobase_addr, 0x7680); + dmp_reg = ®->iobase_window; + for (cnt = 0; cnt < 16; cnt++) + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); + + WRT_REG_DWORD(®->iobase_addr, 0x7690); + dmp_reg = ®->iobase_window; + for (cnt = 0; cnt < 16; cnt++) + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); + + WRT_REG_DWORD(®->iobase_addr, 0x76A0); + dmp_reg = ®->iobase_window; + for (cnt = 0; cnt < sizeof(fw->xmt_data_dma_reg) / 4; cnt++) + fw->xmt_data_dma_reg[cnt] = + htonl(RD_REG_DWORD(dmp_reg++)); + + /* Receive DMA registers. */ + iter_reg = fw->rcvt0_data_dma_reg; + WRT_REG_DWORD(®->iobase_addr, 0x7700); + dmp_reg = ®->iobase_window; + for (cnt = 0; cnt < 16; cnt++) + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); + + WRT_REG_DWORD(®->iobase_addr, 0x7710); + dmp_reg = ®->iobase_window; + for (cnt = 0; cnt < 16; cnt++) + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); + + iter_reg = fw->rcvt1_data_dma_reg; + WRT_REG_DWORD(®->iobase_addr, 0x7720); + dmp_reg = ®->iobase_window; + for (cnt = 0; cnt < 16; cnt++) + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); + + WRT_REG_DWORD(®->iobase_addr, 0x7730); + dmp_reg = ®->iobase_window; + for (cnt = 0; cnt < 16; cnt++) + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); + + /* RISC registers. */ + iter_reg = fw->risc_gp_reg; + WRT_REG_DWORD(®->iobase_addr, 0x0F00); + dmp_reg = ®->iobase_window; + for (cnt = 0; cnt < 16; cnt++) + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); + + WRT_REG_DWORD(®->iobase_addr, 0x0F10); + dmp_reg = ®->iobase_window; + for (cnt = 0; cnt < 16; cnt++) + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); + + WRT_REG_DWORD(®->iobase_addr, 0x0F20); + dmp_reg = ®->iobase_window; + for (cnt = 0; cnt < 16; cnt++) + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); + + WRT_REG_DWORD(®->iobase_addr, 0x0F30); + dmp_reg = ®->iobase_window; + for (cnt = 0; cnt < 16; cnt++) + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); + + WRT_REG_DWORD(®->iobase_addr, 0x0F40); + dmp_reg = ®->iobase_window; + for (cnt = 0; cnt < 16; cnt++) + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); + + WRT_REG_DWORD(®->iobase_addr, 0x0F50); + dmp_reg = ®->iobase_window; + for (cnt = 0; cnt < 16; cnt++) + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); + + WRT_REG_DWORD(®->iobase_addr, 0x0F60); + dmp_reg = ®->iobase_window; + for (cnt = 0; cnt < 16; cnt++) + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); + + WRT_REG_DWORD(®->iobase_addr, 0x0F70); + dmp_reg = ®->iobase_window; + for (cnt = 0; cnt < 16; cnt++) + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); + + /* Local memory controller registers. */ + iter_reg = fw->lmc_reg; + WRT_REG_DWORD(®->iobase_addr, 0x3000); + dmp_reg = ®->iobase_window; + for (cnt = 0; cnt < 16; cnt++) + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); + + WRT_REG_DWORD(®->iobase_addr, 0x3010); + dmp_reg = ®->iobase_window; + for (cnt = 0; cnt < 16; cnt++) + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); + + WRT_REG_DWORD(®->iobase_addr, 0x3020); + dmp_reg = ®->iobase_window; + for (cnt = 0; cnt < 16; cnt++) + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); + + WRT_REG_DWORD(®->iobase_addr, 0x3030); + dmp_reg = ®->iobase_window; + for (cnt = 0; cnt < 16; cnt++) + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); + + WRT_REG_DWORD(®->iobase_addr, 0x3040); + dmp_reg = ®->iobase_window; + for (cnt = 0; cnt < 16; cnt++) + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); + + WRT_REG_DWORD(®->iobase_addr, 0x3050); + dmp_reg = ®->iobase_window; + for (cnt = 0; cnt < 16; cnt++) + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); + + WRT_REG_DWORD(®->iobase_addr, 0x3060); + dmp_reg = ®->iobase_window; + for (cnt = 0; cnt < 16; cnt++) + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); + + WRT_REG_DWORD(®->iobase_addr, 0x3070); + dmp_reg = ®->iobase_window; + for (cnt = 0; cnt < 16; cnt++) + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); + + /* Fibre Protocol Module registers. */ + iter_reg = fw->fpm_hdw_reg; + WRT_REG_DWORD(®->iobase_addr, 0x4000); + dmp_reg = ®->iobase_window; + for (cnt = 0; cnt < 16; cnt++) + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); + + WRT_REG_DWORD(®->iobase_addr, 0x4010); + dmp_reg = ®->iobase_window; + for (cnt = 0; cnt < 16; cnt++) + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); + + WRT_REG_DWORD(®->iobase_addr, 0x4020); + dmp_reg = ®->iobase_window; + for (cnt = 0; cnt < 16; cnt++) + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); + + WRT_REG_DWORD(®->iobase_addr, 0x4030); + dmp_reg = ®->iobase_window; + for (cnt = 0; cnt < 16; cnt++) + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); + + WRT_REG_DWORD(®->iobase_addr, 0x4040); + dmp_reg = ®->iobase_window; + for (cnt = 0; cnt < 16; cnt++) + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); + + WRT_REG_DWORD(®->iobase_addr, 0x4050); + dmp_reg = ®->iobase_window; + for (cnt = 0; cnt < 16; cnt++) + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); + + WRT_REG_DWORD(®->iobase_addr, 0x4060); + dmp_reg = ®->iobase_window; + for (cnt = 0; cnt < 16; cnt++) + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); + + WRT_REG_DWORD(®->iobase_addr, 0x4070); + dmp_reg = ®->iobase_window; + for (cnt = 0; cnt < 16; cnt++) + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); + + WRT_REG_DWORD(®->iobase_addr, 0x4080); + dmp_reg = ®->iobase_window; + for (cnt = 0; cnt < 16; cnt++) + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); + + WRT_REG_DWORD(®->iobase_addr, 0x4090); + dmp_reg = ®->iobase_window; + for (cnt = 0; cnt < 16; cnt++) + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); + + WRT_REG_DWORD(®->iobase_addr, 0x40A0); + dmp_reg = ®->iobase_window; + for (cnt = 0; cnt < 16; cnt++) + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); + + WRT_REG_DWORD(®->iobase_addr, 0x40B0); + dmp_reg = ®->iobase_window; + for (cnt = 0; cnt < 16; cnt++) + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); + + /* Frame Buffer registers. */ + iter_reg = fw->fb_hdw_reg; + WRT_REG_DWORD(®->iobase_addr, 0x6000); + dmp_reg = ®->iobase_window; + for (cnt = 0; cnt < 16; cnt++) + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); + + WRT_REG_DWORD(®->iobase_addr, 0x6010); + dmp_reg = ®->iobase_window; + for (cnt = 0; cnt < 16; cnt++) + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); + + WRT_REG_DWORD(®->iobase_addr, 0x6020); + dmp_reg = ®->iobase_window; + for (cnt = 0; cnt < 16; cnt++) + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); + + WRT_REG_DWORD(®->iobase_addr, 0x6030); + dmp_reg = ®->iobase_window; + for (cnt = 0; cnt < 16; cnt++) + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); + + WRT_REG_DWORD(®->iobase_addr, 0x6040); + dmp_reg = ®->iobase_window; + for (cnt = 0; cnt < 16; cnt++) + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); + + WRT_REG_DWORD(®->iobase_addr, 0x6100); + dmp_reg = ®->iobase_window; + for (cnt = 0; cnt < 16; cnt++) + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); + + WRT_REG_DWORD(®->iobase_addr, 0x6130); + dmp_reg = ®->iobase_window; + for (cnt = 0; cnt < 16; cnt++) + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); + + WRT_REG_DWORD(®->iobase_addr, 0x6150); + dmp_reg = ®->iobase_window; + for (cnt = 0; cnt < 16; cnt++) + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); + + WRT_REG_DWORD(®->iobase_addr, 0x6170); + dmp_reg = ®->iobase_window; + for (cnt = 0; cnt < 16; cnt++) + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); + + WRT_REG_DWORD(®->iobase_addr, 0x6190); + dmp_reg = ®->iobase_window; + for (cnt = 0; cnt < 16; cnt++) + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); + + WRT_REG_DWORD(®->iobase_addr, 0x61B0); + dmp_reg = ®->iobase_window; + for (cnt = 0; cnt < 16; cnt++) + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); + + WRT_REG_DWORD(®->iobase_addr, 0x6F00); + dmp_reg = ®->iobase_window; + for (cnt = 0; cnt < 16; cnt++) + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); + + /* Reset RISC. */ + WRT_REG_DWORD(®->ctrl_status, + CSRX_DMA_SHUTDOWN|MWB_4096_BYTES); + for (cnt = 0; cnt < 30000; cnt++) { + if ((RD_REG_DWORD(®->ctrl_status) & + CSRX_DMA_ACTIVE) == 0) + break; + + udelay(10); + } + + WRT_REG_DWORD(®->ctrl_status, + CSRX_ISP_SOFT_RESET|CSRX_DMA_SHUTDOWN|MWB_4096_BYTES); + pci_read_config_word(ha->pdev, PCI_COMMAND, &wd); + + udelay(100); + /* Wait for firmware to complete NVRAM accesses. */ + mb0 = (uint32_t) RD_REG_WORD(®->mailbox0); + for (cnt = 10000 ; cnt && mb0; cnt--) { udelay(5); + mb0 = (uint32_t) RD_REG_WORD(®->mailbox0); + barrier(); } - if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) { - rval = mb[0] & MBS_MASK; - fw->ext_mem[cnt] = htonl((mb[3] << 16) | mb[2]); - } else { - rval = QLA_FUNCTION_FAILED; + /* Wait for soft-reset to complete. */ + for (cnt = 0; cnt < 30000; cnt++) { + if ((RD_REG_DWORD(®->ctrl_status) & + CSRX_ISP_SOFT_RESET) == 0) + break; + + udelay(10); } + WRT_REG_DWORD(®->hccr, HCCRX_CLR_RISC_RESET); + RD_REG_DWORD(®->hccr); /* PCI Posting. */ } + for (cnt = 30000; RD_REG_WORD(®->mailbox0) != 0 && + rval == QLA_SUCCESS; cnt--) { + if (cnt) + udelay(100); + else + rval = QLA_FUNCTION_TIMEOUT; + } + + if (rval == QLA_SUCCESS) + rval = qla2xxx_dump_memory(ha, fw->code_ram, + sizeof(fw->code_ram), fw->ext_mem, &nxt); + if (rval == QLA_SUCCESS) { - eft = qla2xxx_copy_queues(ha, &fw->ext_mem[cnt]); + nxt = qla2xxx_copy_queues(ha, nxt); if (ha->eft) - memcpy(eft, ha->eft, ntohl(ha->fw_dump->eft_size)); + memcpy(nxt, ha->eft, ntohl(ha->fw_dump->eft_size)); } if (rval != QLA_SUCCESS) { @@ -1332,7 +2038,7 @@ qla24xx_fw_dump(scsi_qla_host_t *ha, int hardware_locked) ha->fw_dumped = 1; } -qla24xx_fw_dump_failed: +qla25xx_fw_dump_failed: if (!hardware_locked) spin_unlock_irqrestore(&ha->hardware_lock, flags); } diff --git a/drivers/scsi/qla2xxx/qla_dbg.h b/drivers/scsi/qla2xxx/qla_dbg.h index 49dffeb78512..cca4b0d8253e 100644 --- a/drivers/scsi/qla2xxx/qla_dbg.h +++ b/drivers/scsi/qla2xxx/qla_dbg.h @@ -213,6 +213,43 @@ struct qla24xx_fw_dump { uint32_t ext_mem[1]; }; +struct qla25xx_fw_dump { + uint32_t host_status; + uint32_t host_reg[32]; + uint32_t shadow_reg[11]; + uint32_t risc_io_reg; + uint16_t mailbox_reg[32]; + uint32_t xseq_gp_reg[128]; + uint32_t xseq_0_reg[48]; + uint32_t xseq_1_reg[16]; + uint32_t rseq_gp_reg[128]; + uint32_t rseq_0_reg[32]; + uint32_t rseq_1_reg[16]; + uint32_t rseq_2_reg[16]; + uint32_t aseq_gp_reg[128]; + uint32_t aseq_0_reg[32]; + uint32_t aseq_1_reg[16]; + uint32_t aseq_2_reg[16]; + uint32_t cmd_dma_reg[16]; + uint32_t req0_dma_reg[15]; + uint32_t resp0_dma_reg[15]; + uint32_t req1_dma_reg[15]; + uint32_t xmt0_dma_reg[32]; + uint32_t xmt1_dma_reg[32]; + uint32_t xmt2_dma_reg[32]; + uint32_t xmt3_dma_reg[32]; + uint32_t xmt4_dma_reg[32]; + uint32_t xmt_data_dma_reg[16]; + uint32_t rcvt0_data_dma_reg[32]; + uint32_t rcvt1_data_dma_reg[32]; + uint32_t risc_gp_reg[128]; + uint32_t lmc_reg[128]; + uint32_t fpm_hdw_reg[192]; + uint32_t fb_hdw_reg[192]; + uint32_t code_ram[0x2000]; + uint32_t ext_mem[1]; +}; + #define EFT_NUM_BUFFERS 4 #define EFT_BYTES_PER_BUFFER 0x4000 #define EFT_SIZE ((EFT_BYTES_PER_BUFFER) * (EFT_NUM_BUFFERS)) @@ -246,5 +283,6 @@ struct qla2xxx_fw_dump { struct qla2100_fw_dump isp21; struct qla2300_fw_dump isp23; struct qla24xx_fw_dump isp24; + struct qla25xx_fw_dump isp25; } isp; }; diff --git a/drivers/scsi/qla2xxx/qla_def.h b/drivers/scsi/qla2xxx/qla_def.h index a1ca590ba447..0c9f36c8a248 100644 --- a/drivers/scsi/qla2xxx/qla_def.h +++ b/drivers/scsi/qla2xxx/qla_def.h @@ -1711,6 +1711,14 @@ struct ct_fdmi_hba_attributes { #define FDMI_PORT_OS_DEVICE_NAME 5 #define FDMI_PORT_HOST_NAME 6 +#define FDMI_PORT_SPEED_1GB 0x1 +#define FDMI_PORT_SPEED_2GB 0x2 +#define FDMI_PORT_SPEED_10GB 0x4 +#define FDMI_PORT_SPEED_4GB 0x8 +#define FDMI_PORT_SPEED_8GB 0x10 +#define FDMI_PORT_SPEED_16GB 0x20 +#define FDMI_PORT_SPEED_UNKNOWN 0x8000 + struct ct_fdmi_port_attr { uint16_t type; uint16_t len; @@ -2201,6 +2209,7 @@ typedef struct scsi_qla_host { #define SWITCH_FOUND BIT_3 #define DFLG_NO_CABLE BIT_4 +#define PCI_DEVICE_ID_QLOGIC_ISP2532 0x2532 uint32_t device_type; #define DT_ISP2100 BIT_0 #define DT_ISP2200 BIT_1 @@ -2213,8 +2222,11 @@ typedef struct scsi_qla_host { #define DT_ISP2432 BIT_8 #define DT_ISP5422 BIT_9 #define DT_ISP5432 BIT_10 -#define DT_ISP_LAST (DT_ISP5432 << 1) +#define DT_ISP2532 BIT_11 +#define DT_ISP_LAST (DT_ISP2532 << 1) +#define DT_IIDMA BIT_26 +#define DT_FWI2 BIT_27 #define DT_ZIO_SUPPORTED BIT_28 #define DT_OEM_001 BIT_29 #define DT_ISP2200A BIT_30 @@ -2232,12 +2244,16 @@ typedef struct scsi_qla_host { #define IS_QLA2432(ha) (DT_MASK(ha) & DT_ISP2432) #define IS_QLA5422(ha) (DT_MASK(ha) & DT_ISP5422) #define IS_QLA5432(ha) (DT_MASK(ha) & DT_ISP5432) +#define IS_QLA2532(ha) (DT_MASK(ha) & DT_ISP2532) #define IS_QLA23XX(ha) (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA2322(ha) || \ IS_QLA6312(ha) || IS_QLA6322(ha)) #define IS_QLA24XX(ha) (IS_QLA2422(ha) || IS_QLA2432(ha)) #define IS_QLA54XX(ha) (IS_QLA5422(ha) || IS_QLA5432(ha)) +#define IS_QLA25XX(ha) (IS_QLA2532(ha)) +#define IS_IIDMA_CAPABLE(ha) ((ha)->device_type & DT_IIDMA) +#define IS_FWI2_CAPABLE(ha) ((ha)->device_type & DT_FWI2) #define IS_ZIO_SUPPORTED(ha) ((ha)->device_type & DT_ZIO_SUPPORTED) #define IS_OEM_001(ha) ((ha)->device_type & DT_OEM_001) #define HAS_EXTENDED_IDS(ha) ((ha)->device_type & DT_EXTENDED_IDS) @@ -2274,7 +2290,7 @@ typedef struct scsi_qla_host { uint16_t rsp_ring_index; /* Current index. */ uint16_t response_q_length; - struct isp_operations isp_ops; + struct isp_operations *isp_ops; /* Outstandings ISP commands. */ srb_t *outstanding_cmds[MAX_OUTSTANDING_COMMANDS]; @@ -2298,6 +2314,7 @@ typedef struct scsi_qla_host { #define PORT_SPEED_1GB 0x00 #define PORT_SPEED_2GB 0x01 #define PORT_SPEED_4GB 0x03 +#define PORT_SPEED_8GB 0x04 uint16_t link_data_rate; /* F/W operating speed */ uint8_t current_topology; @@ -2564,6 +2581,7 @@ typedef struct scsi_qla_host { #define OPTROM_SIZE_2300 0x20000 #define OPTROM_SIZE_2322 0x100000 #define OPTROM_SIZE_24XX 0x100000 +#define OPTROM_SIZE_25XX 0x200000 #include "qla_gbl.h" #include "qla_dbg.h" diff --git a/drivers/scsi/qla2xxx/qla_fw.h b/drivers/scsi/qla2xxx/qla_fw.h index 63a11fef5d1b..99fe49618d61 100644 --- a/drivers/scsi/qla2xxx/qla_fw.h +++ b/drivers/scsi/qla2xxx/qla_fw.h @@ -8,14 +8,17 @@ #define __QLA_FW_H #define MBS_CHECKSUM_ERROR 0x4010 +#define MBS_INVALID_PRODUCT_KEY 0x4020 /* * Firmware Options. */ #define FO1_ENABLE_PUREX BIT_10 #define FO1_DISABLE_LED_CTRL BIT_6 +#define FO1_ENABLE_8016 BIT_0 #define FO2_ENABLE_SEL_CLASS2 BIT_5 #define FO3_NO_ABTS_ON_LINKDOWN BIT_14 +#define FO3_HOLD_STS_IOCB BIT_12 /* * Port Database structure definition for ISP 24xx. @@ -341,7 +344,9 @@ struct init_cb_24xx { * BIT 10 = Reserved * BIT 11 = Enable FC-SP Security * BIT 12 = FC Tape Enable - * BIT 13-31 = Reserved + * BIT 13 = Reserved + * BIT 14 = Enable Target PRLI Control + * BIT 15-31 = Reserved */ uint32_t firmware_options_2; @@ -363,7 +368,8 @@ struct init_cb_24xx { * BIT 13 = Data Rate bit 0 * BIT 14 = Data Rate bit 1 * BIT 15 = Data Rate bit 2 - * BIT 16-31 = Reserved + * BIT 16 = Enable 75 ohm Termination Select + * BIT 17-31 = Reserved */ uint32_t firmware_options_3; @@ -435,6 +441,7 @@ struct cmd_type_7 { #define TMF_LUN_RESET BIT_12 #define TMF_CLEAR_TASK_SET BIT_10 #define TMF_ABORT_TASK_SET BIT_9 +#define TMF_DSD_LIST_ENABLE BIT_2 #define TMF_READ_DATA BIT_1 #define TMF_WRITE_DATA BIT_0 @@ -589,7 +596,7 @@ struct els_entry_24xx { #define EST_SOFI3 (1 << 4) #define EST_SOFI2 (3 << 4) - uint32_t rx_xchg_address[2]; /* Receive exchange address. */ + uint32_t rx_xchg_address; /* Receive exchange address. */ uint16_t rx_dsd_count; uint8_t opcode; @@ -650,6 +657,7 @@ struct logio_entry_24xx { uint16_t control_flags; /* Control flags. */ /* Modifiers. */ +#define LCF_INCLUDE_SNS BIT_10 /* Include SNS (FFFFFC) during LOGO. */ #define LCF_FCP2_OVERRIDE BIT_9 /* Set/Reset word 3 of PRLI. */ #define LCF_CLASS_2 BIT_8 /* Enable class 2 during PLOGI. */ #define LCF_FREE_NPORT BIT_7 /* Release NPORT handle after LOGO. */ @@ -779,6 +787,15 @@ struct device_reg_24xx { #define FA_RISC_CODE_ADDR 0x20000 #define FA_RISC_CODE_SEGMENTS 2 +#define FA_FW_AREA_ADDR 0x40000 +#define FA_VPD_NVRAM_ADDR 0x48000 +#define FA_FEATURE_ADDR 0x4C000 +#define FA_FLASH_DESCR_ADDR 0x50000 +#define FA_HW_EVENT_ADDR 0x54000 +#define FA_BOOT_LOG_ADDR 0x58000 +#define FA_FW_DUMP0_ADDR 0x60000 +#define FA_FW_DUMP1_ADDR 0x70000 + uint32_t flash_data; /* Flash/NVRAM BIOS data. */ uint32_t ctrl_status; /* Control/Status. */ @@ -859,10 +876,13 @@ struct device_reg_24xx { #define HCCRX_CLR_RISC_INT 0xA0000000 uint32_t gpiod; /* GPIO Data register. */ + /* LED update mask. */ #define GPDX_LED_UPDATE_MASK (BIT_20|BIT_19|BIT_18) /* Data update mask. */ #define GPDX_DATA_UPDATE_MASK (BIT_17|BIT_16) + /* Data update mask. */ +#define GPDX_DATA_UPDATE_2_MASK (BIT_28|BIT_27|BIT_26|BIT_17|BIT_16) /* LED control mask. */ #define GPDX_LED_COLOR_MASK (BIT_4|BIT_3|BIT_2) /* LED bit values. Color names as @@ -877,6 +897,8 @@ struct device_reg_24xx { uint32_t gpioe; /* GPIO Enable register. */ /* Enable update mask. */ #define GPEX_ENABLE_UPDATE_MASK (BIT_17|BIT_16) + /* Enable update mask. */ +#define GPEX_ENABLE_UPDATE_2_MASK (BIT_28|BIT_27|BIT_26|BIT_17|BIT_16) /* Enable. */ #define GPEX_ENABLE (BIT_1|BIT_0) @@ -916,6 +938,14 @@ struct device_reg_24xx { uint16_t mailbox29; uint16_t mailbox30; uint16_t mailbox31; + + uint32_t iobase_window; + uint32_t unused_4[8]; /* Gap. */ + uint32_t iobase_q; + uint32_t unused_5[2]; /* Gap. */ + uint32_t iobase_select; + uint32_t unused_6[2]; /* Gap. */ + uint32_t iobase_sdata; }; /* MID Support ***************************************************************/ diff --git a/drivers/scsi/qla2xxx/qla_gbl.h b/drivers/scsi/qla2xxx/qla_gbl.h index b44eff2803ce..aa1e41152283 100644 --- a/drivers/scsi/qla2xxx/qla_gbl.h +++ b/drivers/scsi/qla2xxx/qla_gbl.h @@ -17,6 +17,7 @@ extern int qla2x00_initialize_adapter(scsi_qla_host_t *); extern int qla2100_pci_config(struct scsi_qla_host *); extern int qla2300_pci_config(struct scsi_qla_host *); extern int qla24xx_pci_config(scsi_qla_host_t *); +extern int qla25xx_pci_config(scsi_qla_host_t *); extern void qla2x00_reset_chip(struct scsi_qla_host *); extern void qla24xx_reset_chip(struct scsi_qla_host *); extern int qla2x00_chip_diag(struct scsi_qla_host *); @@ -281,6 +282,10 @@ extern int qla2x00_write_nvram_data(scsi_qla_host_t *, uint8_t *, uint32_t, uint32_t); extern int qla24xx_write_nvram_data(scsi_qla_host_t *, uint8_t *, uint32_t, uint32_t); +extern uint8_t *qla25xx_read_nvram_data(scsi_qla_host_t *, uint8_t *, uint32_t, + uint32_t); +extern int qla25xx_write_nvram_data(scsi_qla_host_t *, uint8_t *, uint32_t, + uint32_t); extern int qla2x00_beacon_on(struct scsi_qla_host *); extern int qla2x00_beacon_off(struct scsi_qla_host *); @@ -307,6 +312,7 @@ extern int qla24xx_get_flash_version(scsi_qla_host_t *, void *); extern void qla2100_fw_dump(scsi_qla_host_t *, int); extern void qla2300_fw_dump(scsi_qla_host_t *, int); extern void qla24xx_fw_dump(scsi_qla_host_t *, int); +extern void qla25xx_fw_dump(scsi_qla_host_t *, int); extern void qla2x00_dump_regs(scsi_qla_host_t *); extern void qla2x00_dump_buffer(uint8_t *, uint32_t); extern void qla2x00_print_scsi_cmd(struct scsi_cmnd *); diff --git a/drivers/scsi/qla2xxx/qla_gs.c b/drivers/scsi/qla2xxx/qla_gs.c index a086b3f0df65..b06cbb8580d3 100644 --- a/drivers/scsi/qla2xxx/qla_gs.c +++ b/drivers/scsi/qla2xxx/qla_gs.c @@ -127,7 +127,7 @@ qla2x00_chk_ms_status(scsi_qla_host_t *ha, ms_iocb_entry_t *ms_pkt, DEBUG2_3(printk("scsi(%ld): %s failed, error status (%x).\n", ha->host_no, routine, ms_pkt->entry_status)); } else { - if (IS_QLA24XX(ha) || IS_QLA54XX(ha)) + if (IS_FWI2_CAPABLE(ha)) comp_status = le16_to_cpu( ((struct ct_entry_24xx *)ms_pkt)->comp_status); else @@ -180,7 +180,8 @@ qla2x00_ga_nxt(scsi_qla_host_t *ha, fc_port_t *fcport) /* Issue GA_NXT */ /* Prepare common MS IOCB */ - ms_pkt = ha->isp_ops.prep_ms_iocb(ha, GA_NXT_REQ_SIZE, GA_NXT_RSP_SIZE); + ms_pkt = ha->isp_ops->prep_ms_iocb(ha, GA_NXT_REQ_SIZE, + GA_NXT_RSP_SIZE); /* Prepare CT request */ ct_req = qla2x00_prep_ct_req(&ha->ct_sns->p.req, GA_NXT_CMD, @@ -266,7 +267,8 @@ qla2x00_gid_pt(scsi_qla_host_t *ha, sw_info_t *list) /* Issue GID_PT */ /* Prepare common MS IOCB */ - ms_pkt = ha->isp_ops.prep_ms_iocb(ha, GID_PT_REQ_SIZE, GID_PT_RSP_SIZE); + ms_pkt = ha->isp_ops->prep_ms_iocb(ha, GID_PT_REQ_SIZE, + GID_PT_RSP_SIZE); /* Prepare CT request */ ct_req = qla2x00_prep_ct_req(&ha->ct_sns->p.req, GID_PT_CMD, @@ -338,7 +340,7 @@ qla2x00_gpn_id(scsi_qla_host_t *ha, sw_info_t *list) for (i = 0; i < MAX_FIBRE_DEVICES; i++) { /* Issue GPN_ID */ /* Prepare common MS IOCB */ - ms_pkt = ha->isp_ops.prep_ms_iocb(ha, GPN_ID_REQ_SIZE, + ms_pkt = ha->isp_ops->prep_ms_iocb(ha, GPN_ID_REQ_SIZE, GPN_ID_RSP_SIZE); /* Prepare CT request */ @@ -399,7 +401,7 @@ qla2x00_gnn_id(scsi_qla_host_t *ha, sw_info_t *list) for (i = 0; i < MAX_FIBRE_DEVICES; i++) { /* Issue GNN_ID */ /* Prepare common MS IOCB */ - ms_pkt = ha->isp_ops.prep_ms_iocb(ha, GNN_ID_REQ_SIZE, + ms_pkt = ha->isp_ops->prep_ms_iocb(ha, GNN_ID_REQ_SIZE, GNN_ID_RSP_SIZE); /* Prepare CT request */ @@ -473,7 +475,8 @@ qla2x00_rft_id(scsi_qla_host_t *ha) /* Issue RFT_ID */ /* Prepare common MS IOCB */ - ms_pkt = ha->isp_ops.prep_ms_iocb(ha, RFT_ID_REQ_SIZE, RFT_ID_RSP_SIZE); + ms_pkt = ha->isp_ops->prep_ms_iocb(ha, RFT_ID_REQ_SIZE, + RFT_ID_RSP_SIZE); /* Prepare CT request */ ct_req = qla2x00_prep_ct_req(&ha->ct_sns->p.req, RFT_ID_CMD, @@ -528,7 +531,8 @@ qla2x00_rff_id(scsi_qla_host_t *ha) /* Issue RFF_ID */ /* Prepare common MS IOCB */ - ms_pkt = ha->isp_ops.prep_ms_iocb(ha, RFF_ID_REQ_SIZE, RFF_ID_RSP_SIZE); + ms_pkt = ha->isp_ops->prep_ms_iocb(ha, RFF_ID_REQ_SIZE, + RFF_ID_RSP_SIZE); /* Prepare CT request */ ct_req = qla2x00_prep_ct_req(&ha->ct_sns->p.req, RFF_ID_CMD, @@ -582,7 +586,8 @@ qla2x00_rnn_id(scsi_qla_host_t *ha) /* Issue RNN_ID */ /* Prepare common MS IOCB */ - ms_pkt = ha->isp_ops.prep_ms_iocb(ha, RNN_ID_REQ_SIZE, RNN_ID_RSP_SIZE); + ms_pkt = ha->isp_ops->prep_ms_iocb(ha, RNN_ID_REQ_SIZE, + RNN_ID_RSP_SIZE); /* Prepare CT request */ ct_req = qla2x00_prep_ct_req(&ha->ct_sns->p.req, RNN_ID_CMD, @@ -645,7 +650,7 @@ qla2x00_rsnn_nn(scsi_qla_host_t *ha) /* Issue RSNN_NN */ /* Prepare common MS IOCB */ /* Request size adjusted after CT preparation */ - ms_pkt = ha->isp_ops.prep_ms_iocb(ha, 0, RSNN_NN_RSP_SIZE); + ms_pkt = ha->isp_ops->prep_ms_iocb(ha, 0, RSNN_NN_RSP_SIZE); /* Prepare CT request */ ct_req = qla2x00_prep_ct_req(&ha->ct_sns->p.req, RSNN_NN_CMD, @@ -1102,7 +1107,7 @@ qla2x00_mgmt_svr_login(scsi_qla_host_t *ha) if (ha->flags.management_server_logged_in) return ret; - ha->isp_ops.fabric_login(ha, ha->mgmt_svr_loop_id, 0xff, 0xff, 0xfa, + ha->isp_ops->fabric_login(ha, ha->mgmt_svr_loop_id, 0xff, 0xff, 0xfa, mb, BIT_1); if (mb[0] != MBS_COMMAND_COMPLETE) { DEBUG2_13(printk("%s(%ld): Failed MANAGEMENT_SERVER login: " @@ -1198,7 +1203,7 @@ qla2x00_update_ms_fdmi_iocb(scsi_qla_host_t *ha, uint32_t req_size) ms_iocb_entry_t *ms_pkt = ha->ms_iocb; struct ct_entry_24xx *ct_pkt = (struct ct_entry_24xx *)ha->ms_iocb; - if (IS_QLA24XX(ha) || IS_QLA54XX(ha)) { + if (IS_FWI2_CAPABLE(ha)) { ct_pkt->cmd_byte_count = cpu_to_le32(req_size); ct_pkt->dseg_0_len = ct_pkt->cmd_byte_count; } else { @@ -1253,7 +1258,7 @@ qla2x00_fdmi_rhba(scsi_qla_host_t *ha) /* Issue RHBA */ /* Prepare common MS IOCB */ /* Request size adjusted after CT preparation */ - ms_pkt = ha->isp_ops.prep_ms_fdmi_iocb(ha, 0, RHBA_RSP_SIZE); + ms_pkt = ha->isp_ops->prep_ms_fdmi_iocb(ha, 0, RHBA_RSP_SIZE); /* Prepare CT request */ ct_req = qla2x00_prep_ct_fdmi_req(&ha->ct_sns->p.req, RHBA_CMD, @@ -1373,7 +1378,7 @@ qla2x00_fdmi_rhba(scsi_qla_host_t *ha) /* Firmware version */ eiter = (struct ct_fdmi_hba_attr *) (entries + size); eiter->type = __constant_cpu_to_be16(FDMI_HBA_FIRMWARE_VERSION); - ha->isp_ops.fw_version_str(ha, eiter->a.fw_version); + ha->isp_ops->fw_version_str(ha, eiter->a.fw_version); alen = strlen(eiter->a.fw_version); alen += (alen & 3) ? (4 - (alen & 3)) : 4; eiter->len = cpu_to_be16(4 + alen); @@ -1439,7 +1444,7 @@ qla2x00_fdmi_dhba(scsi_qla_host_t *ha) /* Issue RPA */ /* Prepare common MS IOCB */ - ms_pkt = ha->isp_ops.prep_ms_fdmi_iocb(ha, DHBA_REQ_SIZE, + ms_pkt = ha->isp_ops->prep_ms_fdmi_iocb(ha, DHBA_REQ_SIZE, DHBA_RSP_SIZE); /* Prepare CT request */ @@ -1497,7 +1502,7 @@ qla2x00_fdmi_rpa(scsi_qla_host_t *ha) /* Issue RPA */ /* Prepare common MS IOCB */ /* Request size adjusted after CT preparation */ - ms_pkt = ha->isp_ops.prep_ms_fdmi_iocb(ha, 0, RPA_RSP_SIZE); + ms_pkt = ha->isp_ops->prep_ms_fdmi_iocb(ha, 0, RPA_RSP_SIZE); /* Prepare CT request */ ct_req = qla2x00_prep_ct_fdmi_req(&ha->ct_sns->p.req, RPA_CMD, @@ -1527,12 +1532,20 @@ qla2x00_fdmi_rpa(scsi_qla_host_t *ha) eiter = (struct ct_fdmi_port_attr *) (entries + size); eiter->type = __constant_cpu_to_be16(FDMI_PORT_SUPPORT_SPEED); eiter->len = __constant_cpu_to_be16(4 + 4); - if (IS_QLA24XX(ha) || IS_QLA54XX(ha)) - eiter->a.sup_speed = __constant_cpu_to_be32(4); + if (IS_QLA25XX(ha)) + eiter->a.sup_speed = __constant_cpu_to_be32( + FDMI_PORT_SPEED_1GB|FDMI_PORT_SPEED_2GB| + FDMI_PORT_SPEED_4GB|FDMI_PORT_SPEED_8GB); + else if (IS_QLA24XX(ha) || IS_QLA54XX(ha)) + eiter->a.sup_speed = __constant_cpu_to_be32( + FDMI_PORT_SPEED_1GB|FDMI_PORT_SPEED_2GB| + FDMI_PORT_SPEED_4GB); else if (IS_QLA23XX(ha)) - eiter->a.sup_speed = __constant_cpu_to_be32(2); + eiter->a.sup_speed =__constant_cpu_to_be32( + FDMI_PORT_SPEED_1GB|FDMI_PORT_SPEED_2GB); else - eiter->a.sup_speed = __constant_cpu_to_be32(1); + eiter->a.sup_speed = __constant_cpu_to_be32( + FDMI_PORT_SPEED_1GB); size += 4 + 4; DEBUG13(printk("%s(%ld): SUPPORTED_SPEED=%x.\n", __func__, ha->host_no, @@ -1543,14 +1556,25 @@ qla2x00_fdmi_rpa(scsi_qla_host_t *ha) eiter->type = __constant_cpu_to_be16(FDMI_PORT_CURRENT_SPEED); eiter->len = __constant_cpu_to_be16(4 + 4); switch (ha->link_data_rate) { - case 0: - eiter->a.cur_speed = __constant_cpu_to_be32(1); + case PORT_SPEED_1GB: + eiter->a.cur_speed = + __constant_cpu_to_be32(FDMI_PORT_SPEED_1GB); + break; + case PORT_SPEED_2GB: + eiter->a.cur_speed = + __constant_cpu_to_be32(FDMI_PORT_SPEED_2GB); + break; + case PORT_SPEED_4GB: + eiter->a.cur_speed = + __constant_cpu_to_be32(FDMI_PORT_SPEED_4GB); break; - case 1: - eiter->a.cur_speed = __constant_cpu_to_be32(2); + case PORT_SPEED_8GB: + eiter->a.cur_speed = + __constant_cpu_to_be32(FDMI_PORT_SPEED_8GB); break; - case 3: - eiter->a.cur_speed = __constant_cpu_to_be32(4); + default: + eiter->a.cur_speed = + __constant_cpu_to_be32(FDMI_PORT_SPEED_UNKNOWN); break; } size += 4 + 4; @@ -1562,7 +1586,7 @@ qla2x00_fdmi_rpa(scsi_qla_host_t *ha) eiter = (struct ct_fdmi_port_attr *) (entries + size); eiter->type = __constant_cpu_to_be16(FDMI_PORT_MAX_FRAME_SIZE); eiter->len = __constant_cpu_to_be16(4 + 4); - max_frame_size = IS_QLA24XX(ha) || IS_QLA54XX(ha) ? + max_frame_size = IS_FWI2_CAPABLE(ha) ? (uint32_t) icb24->frame_payload_size: (uint32_t) ha->init_cb->frame_payload_size; eiter->a.max_frame_size = cpu_to_be32(max_frame_size); @@ -1678,7 +1702,7 @@ qla2x00_gfpn_id(scsi_qla_host_t *ha, sw_info_t *list) struct ct_sns_req *ct_req; struct ct_sns_rsp *ct_rsp; - if (!IS_QLA24XX(ha) && !IS_QLA54XX(ha)) + if (!IS_IIDMA_CAPABLE(ha)) return QLA_FUNCTION_FAILED; for (i = 0; i < MAX_FIBRE_DEVICES; i++) { @@ -1686,7 +1710,7 @@ qla2x00_gfpn_id(scsi_qla_host_t *ha, sw_info_t *list) memset(list[i].fabric_port_name, 0, WWN_SIZE); /* Prepare common MS IOCB */ - ms_pkt = ha->isp_ops.prep_ms_iocb(ha, GFPN_ID_REQ_SIZE, + ms_pkt = ha->isp_ops->prep_ms_iocb(ha, GFPN_ID_REQ_SIZE, GFPN_ID_RSP_SIZE); /* Prepare CT request */ @@ -1786,7 +1810,7 @@ qla2x00_gpsc(scsi_qla_host_t *ha, sw_info_t *list) struct ct_sns_req *ct_req; struct ct_sns_rsp *ct_rsp; - if (!IS_QLA24XX(ha) && !IS_QLA54XX(ha)) + if (!IS_IIDMA_CAPABLE(ha)) return QLA_FUNCTION_FAILED; if (!ha->flags.gpsc_supported) return QLA_FUNCTION_FAILED; diff --git a/drivers/scsi/qla2xxx/qla_init.c b/drivers/scsi/qla2xxx/qla_init.c index cc6ebb609e98..5ec798c2bf13 100644 --- a/drivers/scsi/qla2xxx/qla_init.c +++ b/drivers/scsi/qla2xxx/qla_init.c @@ -79,20 +79,20 @@ qla2x00_initialize_adapter(scsi_qla_host_t *ha) set_bit(REGISTER_FDMI_NEEDED, &ha->dpc_flags); qla_printk(KERN_INFO, ha, "Configuring PCI space...\n"); - rval = ha->isp_ops.pci_config(ha); + rval = ha->isp_ops->pci_config(ha); if (rval) { DEBUG2(printk("scsi(%ld): Unable to configure PCI space.\n", ha->host_no)); return (rval); } - ha->isp_ops.reset_chip(ha); + ha->isp_ops->reset_chip(ha); - ha->isp_ops.get_flash_version(ha, ha->request_ring); + ha->isp_ops->get_flash_version(ha, ha->request_ring); qla_printk(KERN_INFO, ha, "Configure NVRAM parameters...\n"); - ha->isp_ops.nvram_config(ha); + ha->isp_ops->nvram_config(ha); if (ha->flags.disable_serdes) { /* Mask HBA via NVRAM settings? */ @@ -108,7 +108,7 @@ qla2x00_initialize_adapter(scsi_qla_host_t *ha) qla_printk(KERN_INFO, ha, "Verifying loaded RISC code...\n"); if (qla2x00_isp_firmware(ha) != QLA_SUCCESS) { - rval = ha->isp_ops.chip_diag(ha); + rval = ha->isp_ops->chip_diag(ha); if (rval) return (rval); rval = qla2x00_setup_chip(ha); @@ -129,14 +129,13 @@ qla2x00_initialize_adapter(scsi_qla_host_t *ha) int qla2100_pci_config(scsi_qla_host_t *ha) { - int ret; uint16_t w; uint32_t d; unsigned long flags; struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; pci_set_master(ha->pdev); - ret = pci_set_mwi(ha->pdev); + pci_try_set_mwi(ha->pdev); pci_read_config_word(ha->pdev, PCI_COMMAND, &w); w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR); @@ -164,7 +163,6 @@ qla2100_pci_config(scsi_qla_host_t *ha) int qla2300_pci_config(scsi_qla_host_t *ha) { - int ret; uint16_t w; uint32_t d; unsigned long flags = 0; @@ -172,7 +170,7 @@ qla2300_pci_config(scsi_qla_host_t *ha) struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; pci_set_master(ha->pdev); - ret = pci_set_mwi(ha->pdev); + pci_try_set_mwi(ha->pdev); pci_read_config_word(ha->pdev, PCI_COMMAND, &w); w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR); @@ -250,15 +248,13 @@ qla2300_pci_config(scsi_qla_host_t *ha) int qla24xx_pci_config(scsi_qla_host_t *ha) { - int ret; uint16_t w; uint32_t d; unsigned long flags = 0; struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; - int pcix_cmd_reg, pcie_dctl_reg; pci_set_master(ha->pdev); - ret = pci_set_mwi(ha->pdev); + pci_try_set_mwi(ha->pdev); pci_read_config_word(ha->pdev, PCI_COMMAND, &w); w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR); @@ -268,28 +264,12 @@ qla24xx_pci_config(scsi_qla_host_t *ha) pci_write_config_byte(ha->pdev, PCI_LATENCY_TIMER, 0x80); /* PCI-X -- adjust Maximum Memory Read Byte Count (2048). */ - pcix_cmd_reg = pci_find_capability(ha->pdev, PCI_CAP_ID_PCIX); - if (pcix_cmd_reg) { - uint16_t pcix_cmd; - - pcix_cmd_reg += PCI_X_CMD; - pci_read_config_word(ha->pdev, pcix_cmd_reg, &pcix_cmd); - pcix_cmd &= ~PCI_X_CMD_MAX_READ; - pcix_cmd |= 0x0008; - pci_write_config_word(ha->pdev, pcix_cmd_reg, pcix_cmd); - } + if (pci_find_capability(ha->pdev, PCI_CAP_ID_PCIX)) + pcix_set_mmrbc(ha->pdev, 2048); /* PCIe -- adjust Maximum Read Request Size (2048). */ - pcie_dctl_reg = pci_find_capability(ha->pdev, PCI_CAP_ID_EXP); - if (pcie_dctl_reg) { - uint16_t pcie_dctl; - - pcie_dctl_reg += PCI_EXP_DEVCTL; - pci_read_config_word(ha->pdev, pcie_dctl_reg, &pcie_dctl); - pcie_dctl &= ~PCI_EXP_DEVCTL_READRQ; - pcie_dctl |= 0x4000; - pci_write_config_word(ha->pdev, pcie_dctl_reg, pcie_dctl); - } + if (pci_find_capability(ha->pdev, PCI_CAP_ID_EXP)) + pcie_set_readrq(ha->pdev, 2048); /* Reset expansion ROM address decode enable */ pci_read_config_dword(ha->pdev, PCI_ROM_ADDRESS, &d); @@ -307,6 +287,40 @@ qla24xx_pci_config(scsi_qla_host_t *ha) } /** + * qla25xx_pci_config() - Setup ISP25xx PCI configuration registers. + * @ha: HA context + * + * Returns 0 on success. + */ +int +qla25xx_pci_config(scsi_qla_host_t *ha) +{ + uint16_t w; + uint32_t d; + + pci_set_master(ha->pdev); + pci_try_set_mwi(ha->pdev); + + pci_read_config_word(ha->pdev, PCI_COMMAND, &w); + w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR); + w &= ~PCI_COMMAND_INTX_DISABLE; + pci_write_config_word(ha->pdev, PCI_COMMAND, w); + + /* PCIe -- adjust Maximum Read Request Size (2048). */ + if (pci_find_capability(ha->pdev, PCI_CAP_ID_EXP)) + pcie_set_readrq(ha->pdev, 2048); + + /* Reset expansion ROM address decode enable */ + pci_read_config_dword(ha->pdev, PCI_ROM_ADDRESS, &d); + d &= ~PCI_ROM_ADDRESS_ENABLE; + pci_write_config_dword(ha->pdev, PCI_ROM_ADDRESS, d); + + ha->chip_revision = ha->pdev->revision; + + return QLA_SUCCESS; +} + +/** * qla2x00_isp_firmware() - Choose firmware image. * @ha: HA context * @@ -351,7 +365,7 @@ qla2x00_reset_chip(scsi_qla_host_t *ha) uint32_t cnt; uint16_t cmd; - ha->isp_ops.disable_intrs(ha); + ha->isp_ops->disable_intrs(ha); spin_lock_irqsave(&ha->hardware_lock, flags); @@ -551,7 +565,7 @@ qla24xx_reset_risc(scsi_qla_host_t *ha) void qla24xx_reset_chip(scsi_qla_host_t *ha) { - ha->isp_ops.disable_intrs(ha); + ha->isp_ops->disable_intrs(ha); /* Perform RISC reset. */ qla24xx_reset_risc(ha); @@ -736,8 +750,10 @@ qla2x00_alloc_fw_dump(scsi_qla_host_t *ha) fixed_size = offsetof(struct qla2300_fw_dump, data_ram); mem_size = (ha->fw_memory_size - 0x11000 + 1) * sizeof(uint16_t); - } else if (IS_QLA24XX(ha) || IS_QLA54XX(ha)) { - fixed_size = offsetof(struct qla24xx_fw_dump, ext_mem); + } else if (IS_FWI2_CAPABLE(ha)) { + fixed_size = IS_QLA25XX(ha) ? + offsetof(struct qla25xx_fw_dump, ext_mem): + offsetof(struct qla24xx_fw_dump, ext_mem); mem_size = (ha->fw_memory_size - 0x100000 + 1) * sizeof(uint32_t); @@ -879,7 +895,7 @@ qla2x00_setup_chip(scsi_qla_host_t *ha) uint32_t srisc_address = 0; /* Load firmware sequences */ - rval = ha->isp_ops.load_risc(ha, &srisc_address); + rval = ha->isp_ops->load_risc(ha, &srisc_address); if (rval == QLA_SUCCESS) { DEBUG(printk("scsi(%ld): Verifying Checksum of loaded RISC " "code.\n", ha->host_no)); @@ -1130,12 +1146,12 @@ qla2x00_init_rings(scsi_qla_host_t *ha) /* Initialize response queue entries */ qla2x00_init_response_q_entries(ha); - ha->isp_ops.config_rings(ha); + ha->isp_ops->config_rings(ha); spin_unlock_irqrestore(&ha->hardware_lock, flags); /* Update any ISP specific firmware options before initialization. */ - ha->isp_ops.update_fw_options(ha); + ha->isp_ops->update_fw_options(ha); DEBUG(printk("scsi(%ld): Issue init firmware.\n", ha->host_no)); @@ -1459,7 +1475,7 @@ qla2x00_nvram_config(scsi_qla_host_t *ha) ha->nvram_base = 0x80; /* Get NVRAM data and calculate checksum. */ - ha->isp_ops.read_nvram(ha, ptr, ha->nvram_base, ha->nvram_size); + ha->isp_ops->read_nvram(ha, ptr, ha->nvram_base, ha->nvram_size); for (cnt = 0, chksum = 0; cnt < ha->nvram_size; cnt++) chksum += *ptr++; @@ -2119,7 +2135,7 @@ qla2x00_iidma_fcport(scsi_qla_host_t *ha, fc_port_t *fcport) int rval; uint16_t port_speed, mb[6]; - if (!IS_QLA24XX(ha)) + if (!IS_IIDMA_CAPABLE(ha)) return; switch (be16_to_cpu(fcport->fp_speed)) { @@ -2267,7 +2283,7 @@ qla2x00_configure_fabric(scsi_qla_host_t *ha) scsi_qla_host_t *pha = to_qla_parent(ha); /* If FL port exists, then SNS is present */ - if (IS_QLA24XX(ha) || IS_QLA54XX(ha)) + if (IS_FWI2_CAPABLE(ha)) loop_id = NPH_F_PORT; else loop_id = SNS_FL_PORT; @@ -2294,11 +2310,11 @@ qla2x00_configure_fabric(scsi_qla_host_t *ha) qla2x00_fdmi_register(ha); /* Ensure we are logged into the SNS. */ - if (IS_QLA24XX(ha) || IS_QLA54XX(ha)) + if (IS_FWI2_CAPABLE(ha)) loop_id = NPH_SNS; else loop_id = SIMPLE_NAME_SERVER; - ha->isp_ops.fabric_login(ha, loop_id, 0xff, 0xff, + ha->isp_ops->fabric_login(ha, loop_id, 0xff, 0xff, 0xfc, mb, BIT_1 | BIT_0); if (mb[0] != MBS_COMMAND_COMPLETE) { DEBUG2(qla_printk(KERN_INFO, ha, @@ -2355,7 +2371,7 @@ qla2x00_configure_fabric(scsi_qla_host_t *ha) (fcport->flags & FCF_TAPE_PRESENT) == 0 && fcport->port_type != FCT_INITIATOR && fcport->port_type != FCT_BROADCAST) { - ha->isp_ops.fabric_logout(ha, + ha->isp_ops->fabric_logout(ha, fcport->loop_id, fcport->d_id.b.domain, fcport->d_id.b.area, @@ -2664,7 +2680,7 @@ qla2x00_find_all_fabric_devs(scsi_qla_host_t *ha, struct list_head *new_fcports) (fcport->flags & FCF_TAPE_PRESENT) == 0 && fcport->port_type != FCT_INITIATOR && fcport->port_type != FCT_BROADCAST) { - ha->isp_ops.fabric_logout(ha, fcport->loop_id, + ha->isp_ops->fabric_logout(ha, fcport->loop_id, fcport->d_id.b.domain, fcport->d_id.b.area, fcport->d_id.b.al_pa); fcport->loop_id = FC_NO_LOOP_ID; @@ -2919,7 +2935,7 @@ qla2x00_fabric_dev_login(scsi_qla_host_t *ha, fc_port_t *fcport, opts |= BIT_1; rval = qla2x00_get_port_database(ha, fcport, opts); if (rval != QLA_SUCCESS) { - ha->isp_ops.fabric_logout(ha, fcport->loop_id, + ha->isp_ops->fabric_logout(ha, fcport->loop_id, fcport->d_id.b.domain, fcport->d_id.b.area, fcport->d_id.b.al_pa); qla2x00_mark_device_lost(ha, fcport, 1, 0); @@ -2964,7 +2980,7 @@ qla2x00_fabric_login(scsi_qla_host_t *ha, fc_port_t *fcport, fcport->d_id.b.area, fcport->d_id.b.al_pa)); /* Login fcport on switch. */ - ha->isp_ops.fabric_login(ha, fcport->loop_id, + ha->isp_ops->fabric_login(ha, fcport->loop_id, fcport->d_id.b.domain, fcport->d_id.b.area, fcport->d_id.b.al_pa, mb, BIT_0); if (mb[0] == MBS_PORT_ID_USED) { @@ -3032,7 +3048,7 @@ qla2x00_fabric_login(scsi_qla_host_t *ha, fc_port_t *fcport, * dead. */ *next_loopid = fcport->loop_id; - ha->isp_ops.fabric_logout(ha, fcport->loop_id, + ha->isp_ops->fabric_logout(ha, fcport->loop_id, fcport->d_id.b.domain, fcport->d_id.b.area, fcport->d_id.b.al_pa); qla2x00_mark_device_lost(ha, fcport, 1, 0); @@ -3050,7 +3066,7 @@ qla2x00_fabric_login(scsi_qla_host_t *ha, fc_port_t *fcport, fcport->d_id.b.al_pa, fcport->loop_id, jiffies)); *next_loopid = fcport->loop_id; - ha->isp_ops.fabric_logout(ha, fcport->loop_id, + ha->isp_ops->fabric_logout(ha, fcport->loop_id, fcport->d_id.b.domain, fcport->d_id.b.area, fcport->d_id.b.al_pa); fcport->loop_id = FC_NO_LOOP_ID; @@ -3206,7 +3222,7 @@ qla2x00_abort_isp(scsi_qla_host_t *ha) qla_printk(KERN_INFO, ha, "Performing ISP error recovery - ha= %p.\n", ha); - ha->isp_ops.reset_chip(ha); + ha->isp_ops->reset_chip(ha); atomic_set(&ha->loop_down_timer, LOOP_DOWN_TIME); if (atomic_read(&ha->loop_state) != LOOP_DOWN) { @@ -3232,9 +3248,9 @@ qla2x00_abort_isp(scsi_qla_host_t *ha) } spin_unlock_irqrestore(&ha->hardware_lock, flags); - ha->isp_ops.get_flash_version(ha, ha->request_ring); + ha->isp_ops->get_flash_version(ha, ha->request_ring); - ha->isp_ops.nvram_config(ha); + ha->isp_ops->nvram_config(ha); if (!qla2x00_restart_isp(ha)) { clear_bit(RESET_MARKER_NEEDED, &ha->dpc_flags); @@ -3249,7 +3265,7 @@ qla2x00_abort_isp(scsi_qla_host_t *ha) ha->flags.online = 1; - ha->isp_ops.enable_intrs(ha); + ha->isp_ops->enable_intrs(ha); ha->isp_abort_cnt = 0; clear_bit(ISP_ABORT_RETRY, &ha->dpc_flags); @@ -3274,7 +3290,7 @@ qla2x00_abort_isp(scsi_qla_host_t *ha) * The next call disables the board * completely. */ - ha->isp_ops.reset_adapter(ha); + ha->isp_ops->reset_adapter(ha); ha->flags.online = 0; clear_bit(ISP_ABORT_RETRY, &ha->dpc_flags); @@ -3331,7 +3347,7 @@ qla2x00_restart_isp(scsi_qla_host_t *ha) /* If firmware needs to be loaded */ if (qla2x00_isp_firmware(ha)) { ha->flags.online = 0; - if (!(status = ha->isp_ops.chip_diag(ha))) { + if (!(status = ha->isp_ops->chip_diag(ha))) { if (IS_QLA2100(ha) || IS_QLA2200(ha)) { status = qla2x00_setup_chip(ha); goto done; @@ -3423,7 +3439,7 @@ qla2x00_reset_adapter(scsi_qla_host_t *ha) struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; ha->flags.online = 0; - ha->isp_ops.disable_intrs(ha); + ha->isp_ops->disable_intrs(ha); spin_lock_irqsave(&ha->hardware_lock, flags); WRT_REG_WORD(®->hccr, HCCR_RESET_RISC); @@ -3440,7 +3456,7 @@ qla24xx_reset_adapter(scsi_qla_host_t *ha) struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; ha->flags.online = 0; - ha->isp_ops.disable_intrs(ha); + ha->isp_ops->disable_intrs(ha); spin_lock_irqsave(&ha->hardware_lock, flags); WRT_REG_DWORD(®->hccr, HCCRX_SET_RISC_RESET); @@ -3498,7 +3514,7 @@ qla24xx_nvram_config(scsi_qla_host_t *ha) /* Get NVRAM data and calculate checksum. */ dptr = (uint32_t *)nv; - ha->isp_ops.read_nvram(ha, (uint8_t *)dptr, ha->nvram_base, + ha->isp_ops->read_nvram(ha, (uint8_t *)dptr, ha->nvram_base, ha->nvram_size); for (cnt = 0, chksum = 0; cnt < ha->nvram_size >> 2; cnt++) chksum += le32_to_cpu(*dptr++); @@ -4012,7 +4028,7 @@ qla2x00_try_to_stop_firmware(scsi_qla_host_t *ha) { int ret, retries; - if (!IS_QLA24XX(ha) && !IS_QLA54XX(ha)) + if (!IS_FWI2_CAPABLE(ha)) return; if (!ha->fw_major_version) return; diff --git a/drivers/scsi/qla2xxx/qla_inline.h b/drivers/scsi/qla2xxx/qla_inline.h index d3023338628f..8e3b04464cff 100644 --- a/drivers/scsi/qla2xxx/qla_inline.h +++ b/drivers/scsi/qla2xxx/qla_inline.h @@ -104,7 +104,7 @@ static __inline__ void qla2x00_poll(scsi_qla_host_t *); static inline void qla2x00_poll(scsi_qla_host_t *ha) { - ha->isp_ops.intr_handler(0, ha); + ha->isp_ops->intr_handler(0, ha); } static __inline__ void qla2x00_check_fabric_devices(scsi_qla_host_t *); @@ -163,7 +163,7 @@ static inline int qla2x00_is_reserved_id(scsi_qla_host_t *, uint16_t); static inline int qla2x00_is_reserved_id(scsi_qla_host_t *ha, uint16_t loop_id) { - if (IS_QLA24XX(ha) || IS_QLA54XX(ha)) + if (IS_FWI2_CAPABLE(ha)) return (loop_id > NPH_LAST_HANDLE); return ((loop_id > ha->last_loop_id && loop_id < SNS_FIRST_LOOP_ID) || diff --git a/drivers/scsi/qla2xxx/qla_iocb.c b/drivers/scsi/qla2xxx/qla_iocb.c index c71863ff5489..3a5e78cb6b3f 100644 --- a/drivers/scsi/qla2xxx/qla_iocb.c +++ b/drivers/scsi/qla2xxx/qla_iocb.c @@ -326,7 +326,7 @@ qla2x00_start_scsi(srb_t *sp) tot_dsds = nseg; /* Calculate the number of request entries needed. */ - req_cnt = ha->isp_ops.calc_req_entries(tot_dsds); + req_cnt = ha->isp_ops->calc_req_entries(tot_dsds); if (ha->req_q_cnt < (req_cnt + 2)) { cnt = RD_REG_WORD_RELAXED(ISP_REQ_Q_OUT(ha, reg)); if (ha->req_ring_index < cnt) @@ -364,7 +364,7 @@ qla2x00_start_scsi(srb_t *sp) cmd_pkt->byte_count = cpu_to_le32((uint32_t)scsi_bufflen(cmd)); /* Build IOCB segments */ - ha->isp_ops.build_iocbs(sp, cmd_pkt, tot_dsds); + ha->isp_ops->build_iocbs(sp, cmd_pkt, tot_dsds); /* Set total data segment count. */ cmd_pkt->entry_count = (uint8_t)req_cnt; @@ -432,7 +432,7 @@ __qla2x00_marker(scsi_qla_host_t *ha, uint16_t loop_id, uint16_t lun, mrk->entry_type = MARKER_TYPE; mrk->modifier = type; if (type != MK_SYNC_ALL) { - if (IS_QLA24XX(ha) || IS_QLA54XX(ha)) { + if (IS_FWI2_CAPABLE(ha)) { mrk24 = (struct mrk_entry_24xx *) mrk; mrk24->nport_handle = cpu_to_le16(loop_id); mrk24->lun[1] = LSB(lun); @@ -487,7 +487,7 @@ qla2x00_req_pkt(scsi_qla_host_t *ha) for (timer = HZ; timer; timer--) { if ((req_cnt + 2) >= ha->req_q_cnt) { /* Calculate number of free request entries. */ - if (IS_QLA24XX(ha) || IS_QLA54XX(ha)) + if (IS_FWI2_CAPABLE(ha)) cnt = (uint16_t)RD_REG_DWORD( ®->isp24.req_q_out); else @@ -561,7 +561,7 @@ qla2x00_isp_cmd(scsi_qla_host_t *ha) ha->request_ring_ptr++; /* Set chip new ring index. */ - if (IS_QLA24XX(ha) || IS_QLA54XX(ha)) { + if (IS_FWI2_CAPABLE(ha)) { WRT_REG_DWORD(®->isp24.req_q_in, ha->req_ring_index); RD_REG_DWORD_RELAXED(®->isp24.req_q_in); } else { diff --git a/drivers/scsi/qla2xxx/qla_isr.c b/drivers/scsi/qla2xxx/qla_isr.c index 0ba4c8d37879..b8f226ae2633 100644 --- a/drivers/scsi/qla2xxx/qla_isr.c +++ b/drivers/scsi/qla2xxx/qla_isr.c @@ -143,7 +143,7 @@ qla2300_intr_handler(int irq, void *dev_id) WRT_REG_WORD(®->hccr, HCCR_RESET_RISC); RD_REG_WORD(®->hccr); - ha->isp_ops.fw_dump(ha, 1); + ha->isp_ops->fw_dump(ha, 1); set_bit(ISP_ABORT_NEEDED, &ha->dpc_flags); break; } else if ((stat & HSR_RISC_INT) == 0) @@ -247,7 +247,7 @@ void qla2x00_async_event(scsi_qla_host_t *ha, uint16_t *mb) { #define LS_UNKNOWN 2 - static char *link_speeds[5] = { "1", "2", "?", "4", "10" }; + static char *link_speeds[5] = { "1", "2", "?", "4", "8" }; char *link_speed; uint16_t handle_cnt; uint16_t cnt; @@ -334,9 +334,9 @@ qla2x00_async_event(scsi_qla_host_t *ha, uint16_t *mb) "ISP System Error - mbx1=%xh mbx2=%xh mbx3=%xh.\n", mb[1], mb[2], mb[3]); - ha->isp_ops.fw_dump(ha, 1); + ha->isp_ops->fw_dump(ha, 1); - if (IS_QLA24XX(ha) || IS_QLA54XX(ha)) { + if (IS_FWI2_CAPABLE(ha)) { if (mb[1] == 0 && mb[2] == 0) { qla_printk(KERN_ERR, ha, "Unrecoverable Hardware Error: adapter " @@ -601,7 +601,7 @@ qla2x00_async_event(scsi_qla_host_t *ha, uint16_t *mb) "scsi(%ld): [R|Z]IO update completion.\n", ha->host_no)); - if (IS_QLA24XX(ha) || IS_QLA54XX(ha)) + if (IS_FWI2_CAPABLE(ha)) qla24xx_process_response_queue(ha); else qla2x00_process_response_queue(ha); @@ -823,7 +823,7 @@ qla2x00_status_entry(scsi_qla_host_t *ha, void *pkt) sts = (sts_entry_t *) pkt; sts24 = (struct sts_entry_24xx *) pkt; - if (IS_QLA24XX(ha) || IS_QLA54XX(ha)) { + if (IS_FWI2_CAPABLE(ha)) { comp_status = le16_to_cpu(sts24->comp_status); scsi_status = le16_to_cpu(sts24->scsi_status) & SS_MASK; } else { @@ -872,7 +872,7 @@ qla2x00_status_entry(scsi_qla_host_t *ha, void *pkt) fcport = sp->fcport; sense_len = rsp_info_len = resid_len = fw_resid_len = 0; - if (IS_QLA24XX(ha) || IS_QLA54XX(ha)) { + if (IS_FWI2_CAPABLE(ha)) { sense_len = le32_to_cpu(sts24->sense_len); rsp_info_len = le32_to_cpu(sts24->rsp_data_len); resid_len = le32_to_cpu(sts24->rsp_residual_count); @@ -891,7 +891,7 @@ qla2x00_status_entry(scsi_qla_host_t *ha, void *pkt) /* Check for any FCP transport errors. */ if (scsi_status & SS_RESPONSE_INFO_LEN_VALID) { /* Sense data lies beyond any FCP RESPONSE data. */ - if (IS_QLA24XX(ha) || IS_QLA54XX(ha)) + if (IS_FWI2_CAPABLE(ha)) sense_data += rsp_info_len; if (rsp_info_len > 3 && rsp_info[3]) { DEBUG2(printk("scsi(%ld:%d:%d:%d) FCP I/O protocol " @@ -990,7 +990,7 @@ qla2x00_status_entry(scsi_qla_host_t *ha, void *pkt) case CS_DATA_UNDERRUN: resid = resid_len; /* Use F/W calculated residual length. */ - if (IS_QLA24XX(ha) || IS_QLA54XX(ha)) + if (IS_FWI2_CAPABLE(ha)) resid = fw_resid_len; if (scsi_status & SS_RESIDUAL_UNDER) { @@ -1062,6 +1062,25 @@ qla2x00_status_entry(scsi_qla_host_t *ha, void *pkt) cp->device->id, cp->device->lun, cp, cp->serial_number)); + /* + * In case of a Underrun condition, set both the lscsi + * status and the completion status to appropriate + * values. + */ + if (resid && + ((unsigned)(cp->request_bufflen - resid) < + cp->underflow)) { + DEBUG2(qla_printk(KERN_INFO, ha, + "scsi(%ld:%d:%d:%d): Mid-layer underflow " + "detected (%x of %x bytes)...returning " + "error status.\n", ha->host_no, + cp->device->channel, cp->device->id, + cp->device->lun, resid, + cp->request_bufflen)); + + cp->result = DID_ERROR << 16 | lscsi_status; + } + if (sense_len) DEBUG5(qla2x00_dump_buffer(cp->sense_buffer, CMD_ACTUAL_SNSLEN(cp))); @@ -1166,7 +1185,7 @@ qla2x00_status_entry(scsi_qla_host_t *ha, void *pkt) case CS_TIMEOUT: cp->result = DID_BUS_BUSY << 16; - if (IS_QLA24XX(ha) || IS_QLA54XX(ha)) { + if (IS_FWI2_CAPABLE(ha)) { DEBUG2(printk(KERN_INFO "scsi(%ld:%d:%d:%d): TIMEOUT status detected " "0x%x-0x%x\n", ha->host_no, cp->device->channel, @@ -1235,7 +1254,7 @@ qla2x00_status_cont_entry(scsi_qla_host_t *ha, sts_cont_entry_t *pkt) } /* Move sense data. */ - if (IS_QLA24XX(ha) || IS_QLA54XX(ha)) + if (IS_FWI2_CAPABLE(ha)) host_to_fcp_swap(pkt->data, sizeof(pkt->data)); memcpy(sp->request_sense_ptr, pkt->data, sense_sz); DEBUG5(qla2x00_dump_buffer(sp->request_sense_ptr, sense_sz)); @@ -1483,7 +1502,7 @@ qla24xx_intr_handler(int irq, void *dev_id) qla_printk(KERN_INFO, ha, "RISC paused -- HCCR=%x, " "Dumping firmware!\n", hccr); - ha->isp_ops.fw_dump(ha, 1); + ha->isp_ops->fw_dump(ha, 1); set_bit(ISP_ABORT_NEEDED, &ha->dpc_flags); break; } else if ((stat & HSRX_RISC_INT) == 0) @@ -1617,7 +1636,7 @@ qla24xx_msix_default(int irq, void *dev_id) qla_printk(KERN_INFO, ha, "RISC paused -- HCCR=%x, " "Dumping firmware!\n", hccr); - ha->isp_ops.fw_dump(ha, 1); + ha->isp_ops->fw_dump(ha, 1); set_bit(ISP_ABORT_NEEDED, &ha->dpc_flags); break; } else if ((stat & HSRX_RISC_INT) == 0) @@ -1739,11 +1758,11 @@ qla2x00_request_irqs(scsi_qla_host_t *ha) int ret; /* If possible, enable MSI-X. */ - if (!IS_QLA2432(ha)) + if (!IS_QLA2432(ha) && !IS_QLA2532(ha)) goto skip_msix; - if (ha->chip_revision < QLA_MSIX_CHIP_REV_24XX || - !QLA_MSIX_FW_MODE_1(ha->fw_attributes)) { + if (IS_QLA2432(ha) && (ha->chip_revision < QLA_MSIX_CHIP_REV_24XX || + !QLA_MSIX_FW_MODE_1(ha->fw_attributes))) { DEBUG2(qla_printk(KERN_WARNING, ha, "MSI-X: Unsupported ISP2432 (0x%X, 0x%X).\n", ha->chip_revision, ha->fw_attributes)); @@ -1762,7 +1781,7 @@ qla2x00_request_irqs(scsi_qla_host_t *ha) "MSI-X: Falling back-to INTa mode -- %d.\n", ret); skip_msix: - if (!IS_QLA24XX(ha)) + if (!IS_QLA24XX(ha) && !IS_QLA2532(ha)) goto skip_msi; ret = pci_enable_msi(ha->pdev); @@ -1772,7 +1791,7 @@ skip_msix: } skip_msi: - ret = request_irq(ha->pdev->irq, ha->isp_ops.intr_handler, + ret = request_irq(ha->pdev->irq, ha->isp_ops->intr_handler, IRQF_DISABLED|IRQF_SHARED, QLA2XXX_DRIVER_NAME, ha); if (!ret) { ha->flags.inta_enabled = 1; diff --git a/drivers/scsi/qla2xxx/qla_mbx.c b/drivers/scsi/qla2xxx/qla_mbx.c index 2cd0cff25928..d3746ec80a85 100644 --- a/drivers/scsi/qla2xxx/qla_mbx.c +++ b/drivers/scsi/qla2xxx/qla_mbx.c @@ -90,7 +90,7 @@ qla2x00_mailbox_command(scsi_qla_host_t *pvha, mbx_cmd_t *mcp) spin_lock_irqsave(&ha->hardware_lock, flags); /* Load mailbox registers. */ - if (IS_QLA24XX(ha) || IS_QLA54XX(ha)) + if (IS_FWI2_CAPABLE(ha)) optr = (uint16_t __iomem *)®->isp24.mailbox0; else optr = (uint16_t __iomem *)MAILBOX_REG(ha, ®->isp, 0); @@ -154,7 +154,7 @@ qla2x00_mailbox_command(scsi_qla_host_t *pvha, mbx_cmd_t *mcp) set_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags); - if (IS_QLA24XX(ha) || IS_QLA54XX(ha)) + if (IS_FWI2_CAPABLE(ha)) WRT_REG_DWORD(®->isp24.hccr, HCCRX_SET_HOST_INT); else WRT_REG_WORD(®->isp.hccr, HCCR_SET_HOST_INT); @@ -175,7 +175,7 @@ qla2x00_mailbox_command(scsi_qla_host_t *pvha, mbx_cmd_t *mcp) DEBUG3_11(printk("%s(%ld): cmd=%x POLLING MODE.\n", __func__, ha->host_no, command)); - if (IS_QLA24XX(ha) || IS_QLA54XX(ha)) + if (IS_FWI2_CAPABLE(ha)) WRT_REG_DWORD(®->isp24.hccr, HCCRX_SET_HOST_INT); else WRT_REG_WORD(®->isp.hccr, HCCR_SET_HOST_INT); @@ -228,7 +228,7 @@ qla2x00_mailbox_command(scsi_qla_host_t *pvha, mbx_cmd_t *mcp) uint16_t mb0; uint32_t ictrl; - if (IS_QLA24XX(ha) || IS_QLA54XX(ha)) { + if (IS_FWI2_CAPABLE(ha)) { mb0 = RD_REG_WORD(®->isp24.mailbox0); ictrl = RD_REG_DWORD(®->isp24.ictrl); } else { @@ -322,7 +322,7 @@ qla2x00_load_ram(scsi_qla_host_t *ha, dma_addr_t req_dma, uint32_t risc_addr, DEBUG11(printk("%s(%ld): entered.\n", __func__, ha->host_no)); - if (MSW(risc_addr) || IS_QLA24XX(ha) || IS_QLA54XX(ha)) { + if (MSW(risc_addr) || IS_FWI2_CAPABLE(ha)) { mcp->mb[0] = MBC_LOAD_RISC_RAM_EXTENDED; mcp->mb[8] = MSW(risc_addr); mcp->out_mb = MBX_8|MBX_0; @@ -336,7 +336,7 @@ qla2x00_load_ram(scsi_qla_host_t *ha, dma_addr_t req_dma, uint32_t risc_addr, mcp->mb[6] = MSW(MSD(req_dma)); mcp->mb[7] = LSW(MSD(req_dma)); mcp->out_mb |= MBX_7|MBX_6|MBX_3|MBX_2|MBX_1; - if (IS_QLA24XX(ha) || IS_QLA54XX(ha)) { + if (IS_FWI2_CAPABLE(ha)) { mcp->mb[4] = MSW(risc_code_size); mcp->mb[5] = LSW(risc_code_size); mcp->out_mb |= MBX_5|MBX_4; @@ -387,7 +387,7 @@ qla2x00_execute_fw(scsi_qla_host_t *ha, uint32_t risc_addr) mcp->mb[0] = MBC_EXECUTE_FIRMWARE; mcp->out_mb = MBX_0; mcp->in_mb = MBX_0; - if (IS_QLA24XX(ha) || IS_QLA54XX(ha)) { + if (IS_FWI2_CAPABLE(ha)) { mcp->mb[1] = MSW(risc_addr); mcp->mb[2] = LSW(risc_addr); mcp->mb[3] = 0; @@ -410,7 +410,7 @@ qla2x00_execute_fw(scsi_qla_host_t *ha, uint32_t risc_addr) DEBUG2_3_11(printk("%s(%ld): failed=%x mb[0]=%x.\n", __func__, ha->host_no, rval, mcp->mb[0])); } else { - if (IS_QLA24XX(ha) || IS_QLA54XX(ha)) { + if (IS_FWI2_CAPABLE(ha)) { DEBUG11(printk("%s(%ld): done exchanges=%x.\n", __func__, ha->host_no, mcp->mb[1])); } else { @@ -551,7 +551,7 @@ qla2x00_set_fw_options(scsi_qla_host_t *ha, uint16_t *fwopts) mcp->mb[3] = fwopts[3]; mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0; mcp->in_mb = MBX_0; - if (IS_QLA24XX(ha) || IS_QLA54XX(ha)) { + if (IS_FWI2_CAPABLE(ha)) { mcp->in_mb |= MBX_1; } else { mcp->mb[10] = fwopts[10]; @@ -664,7 +664,7 @@ qla2x00_verify_checksum(scsi_qla_host_t *ha, uint32_t risc_addr) mcp->mb[0] = MBC_VERIFY_CHECKSUM; mcp->out_mb = MBX_0; mcp->in_mb = MBX_0; - if (IS_QLA24XX(ha) || IS_QLA54XX(ha)) { + if (IS_FWI2_CAPABLE(ha)) { mcp->mb[1] = MSW(risc_addr); mcp->mb[2] = LSW(risc_addr); mcp->out_mb |= MBX_2|MBX_1; @@ -681,8 +681,8 @@ qla2x00_verify_checksum(scsi_qla_host_t *ha, uint32_t risc_addr) if (rval != QLA_SUCCESS) { DEBUG2_3_11(printk("%s(%ld): failed=%x chk sum=%x.\n", __func__, - ha->host_no, rval, (IS_QLA24XX(ha) || IS_QLA54XX(ha) ? - (mcp->mb[2] << 16) | mcp->mb[1]: mcp->mb[1]))); + ha->host_no, rval, IS_FWI2_CAPABLE(ha) ? + (mcp->mb[2] << 16) | mcp->mb[1]: mcp->mb[1])); } else { DEBUG11(printk("%s(%ld): done.\n", __func__, ha->host_no)); } @@ -739,7 +739,7 @@ qla2x00_issue_iocb(scsi_qla_host_t *ha, void* buffer, dma_addr_t phys_addr, /* Mask reserved bits. */ sts_entry->entry_status &= - IS_QLA24XX(ha) || IS_QLA54XX(ha) ? RF_MASK_24XX :RF_MASK; + IS_FWI2_CAPABLE(ha) ? RF_MASK_24XX :RF_MASK; } return rval; @@ -1085,7 +1085,7 @@ qla2x00_get_port_database(scsi_qla_host_t *ha, fc_port_t *fcport, uint8_t opt) memset(pd, 0, max(PORT_DATABASE_SIZE, PORT_DATABASE_24XX_SIZE)); mcp->mb[0] = MBC_GET_PORT_DATABASE; - if (opt != 0 && !IS_QLA24XX(ha) && !IS_QLA54XX(ha)) + if (opt != 0 && !IS_FWI2_CAPABLE(ha)) mcp->mb[0] = MBC_ENHANCED_GET_PORT_DATABASE; mcp->mb[2] = MSW(pd_dma); mcp->mb[3] = LSW(pd_dma); @@ -1094,7 +1094,7 @@ qla2x00_get_port_database(scsi_qla_host_t *ha, fc_port_t *fcport, uint8_t opt) mcp->mb[9] = ha->vp_idx; mcp->out_mb = MBX_9|MBX_7|MBX_6|MBX_3|MBX_2|MBX_0; mcp->in_mb = MBX_0; - if (IS_QLA24XX(ha) || IS_QLA54XX(ha)) { + if (IS_FWI2_CAPABLE(ha)) { mcp->mb[1] = fcport->loop_id; mcp->mb[10] = opt; mcp->out_mb |= MBX_10|MBX_1; @@ -1107,15 +1107,15 @@ qla2x00_get_port_database(scsi_qla_host_t *ha, fc_port_t *fcport, uint8_t opt) mcp->mb[1] = fcport->loop_id << 8 | opt; mcp->out_mb |= MBX_1; } - mcp->buf_size = (IS_QLA24XX(ha) || IS_QLA54XX(ha) ? - PORT_DATABASE_24XX_SIZE : PORT_DATABASE_SIZE); + mcp->buf_size = IS_FWI2_CAPABLE(ha) ? + PORT_DATABASE_24XX_SIZE : PORT_DATABASE_SIZE; mcp->flags = MBX_DMA_IN; mcp->tov = (ha->login_timeout * 2) + (ha->login_timeout / 2); rval = qla2x00_mailbox_command(ha, mcp); if (rval != QLA_SUCCESS) goto gpd_error_out; - if (IS_QLA24XX(ha) || IS_QLA54XX(ha)) { + if (IS_FWI2_CAPABLE(ha)) { pd24 = (struct port_database_24xx *) pd; /* Check for logged in state. */ @@ -1333,7 +1333,7 @@ qla2x00_lip_reset(scsi_qla_host_t *ha) DEBUG11(printk("%s(%ld): entered.\n", __func__, ha->host_no)); - if (IS_QLA24XX(ha) || IS_QLA54XX(ha)) { + if (IS_FWI2_CAPABLE(ha)) { mcp->mb[0] = MBC_LIP_FULL_LOGIN; mcp->mb[1] = BIT_6; mcp->mb[2] = 0; @@ -1637,7 +1637,7 @@ qla2x00_login_local_device(scsi_qla_host_t *ha, fc_port_t *fcport, mbx_cmd_t mc; mbx_cmd_t *mcp = &mc; - if (IS_QLA24XX(ha) || IS_QLA54XX(ha)) + if (IS_FWI2_CAPABLE(ha)) return qla24xx_login_fabric(ha, fcport->loop_id, fcport->d_id.b.domain, fcport->d_id.b.area, fcport->d_id.b.al_pa, mb_ret, opt); @@ -1821,7 +1821,7 @@ qla2x00_full_login_lip(scsi_qla_host_t *ha) ha->host_no)); mcp->mb[0] = MBC_LIP_FULL_LOGIN; - mcp->mb[1] = IS_QLA24XX(ha) || IS_QLA54XX(ha) ? BIT_3: 0; + mcp->mb[1] = IS_FWI2_CAPABLE(ha) ? BIT_3: 0; mcp->mb[2] = 0; mcp->mb[3] = 0; mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0; @@ -1871,7 +1871,7 @@ qla2x00_get_id_list(scsi_qla_host_t *ha, void *id_list, dma_addr_t id_list_dma, mcp->mb[0] = MBC_GET_ID_LIST; mcp->out_mb = MBX_0; - if (IS_QLA24XX(ha) || IS_QLA54XX(ha)) { + if (IS_FWI2_CAPABLE(ha)) { mcp->mb[2] = MSW(id_list_dma); mcp->mb[3] = LSW(id_list_dma); mcp->mb[6] = MSW(MSD(id_list_dma)); @@ -2063,7 +2063,7 @@ qla2x00_get_link_status(scsi_qla_host_t *ha, uint16_t loop_id, mcp->mb[7] = LSW(MSD(stat_buf_dma)); mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_0; mcp->in_mb = MBX_0; - if (IS_QLA24XX(ha) || IS_QLA54XX(ha)) { + if (IS_FWI2_CAPABLE(ha)) { mcp->mb[1] = loop_id; mcp->mb[4] = 0; mcp->mb[10] = 0; @@ -2334,7 +2334,7 @@ qla2x00_system_error(scsi_qla_host_t *ha) mbx_cmd_t mc; mbx_cmd_t *mcp = &mc; - if (!IS_QLA24XX(ha) && !IS_QLA54XX(ha)) + if (!IS_FWI2_CAPABLE(ha)) return QLA_FUNCTION_FAILED; DEBUG11(printk("%s(%ld): entered.\n", __func__, ha->host_no)); @@ -2444,7 +2444,7 @@ qla2x00_stop_firmware(scsi_qla_host_t *ha) mbx_cmd_t mc; mbx_cmd_t *mcp = &mc; - if (!IS_QLA24XX(ha) && !IS_QLA54XX(ha)) + if (!IS_FWI2_CAPABLE(ha)) return QLA_FUNCTION_FAILED; DEBUG11(printk("%s(%ld): entered.\n", __func__, ha->host_no)); @@ -2474,7 +2474,7 @@ qla2x00_trace_control(scsi_qla_host_t *ha, uint16_t ctrl, dma_addr_t eft_dma, mbx_cmd_t mc; mbx_cmd_t *mcp = &mc; - if (!IS_QLA24XX(ha) && !IS_QLA54XX(ha)) + if (!IS_FWI2_CAPABLE(ha)) return QLA_FUNCTION_FAILED; DEBUG11(printk("%s(%ld): entered.\n", __func__, ha->host_no)); @@ -2514,7 +2514,7 @@ qla2x00_read_sfp(scsi_qla_host_t *ha, dma_addr_t sfp_dma, uint16_t addr, mbx_cmd_t mc; mbx_cmd_t *mcp = &mc; - if (!IS_QLA24XX(ha) && !IS_QLA54XX(ha)) + if (!IS_FWI2_CAPABLE(ha)) return QLA_FUNCTION_FAILED; DEBUG11(printk("%s(%ld): entered.\n", __func__, ha->host_no)); @@ -2552,7 +2552,7 @@ qla2x00_get_idma_speed(scsi_qla_host_t *ha, uint16_t loop_id, mbx_cmd_t mc; mbx_cmd_t *mcp = &mc; - if (!IS_QLA24XX(ha)) + if (!IS_IIDMA_CAPABLE(ha)) return QLA_FUNCTION_FAILED; DEBUG11(printk("%s(%ld): entered.\n", __func__, ha->host_no)); @@ -2595,7 +2595,7 @@ qla2x00_set_idma_speed(scsi_qla_host_t *ha, uint16_t loop_id, mbx_cmd_t mc; mbx_cmd_t *mcp = &mc; - if (!IS_QLA24XX(ha)) + if (!IS_IIDMA_CAPABLE(ha)) return QLA_FUNCTION_FAILED; DEBUG11(printk("%s(%ld): entered.\n", __func__, ha->host_no)); diff --git a/drivers/scsi/qla2xxx/qla_os.c b/drivers/scsi/qla2xxx/qla_os.c index 92376f9dfdd5..c488996cb958 100644 --- a/drivers/scsi/qla2xxx/qla_os.c +++ b/drivers/scsi/qla2xxx/qla_os.c @@ -265,6 +265,8 @@ qla24xx_pci_info_str(struct scsi_qla_host *ha, char *str) strcpy(str, "PCIe ("); if (lspeed == 1) strcat(str, "2.5Gb/s "); + else if (lspeed == 2) + strcat(str, "5.0Gb/s "); else strcat(str, "<unknown> "); snprintf(lwstr, sizeof(lwstr), "x%d)", lwidth); @@ -343,6 +345,12 @@ qla24xx_fw_version_str(struct scsi_qla_host *ha, char *str) strcat(str, "[IP] "); if (ha->fw_attributes & BIT_2) strcat(str, "[Multi-ID] "); + if (ha->fw_attributes & BIT_3) + strcat(str, "[SB-2] "); + if (ha->fw_attributes & BIT_4) + strcat(str, "[T10 CRC] "); + if (ha->fw_attributes & BIT_5) + strcat(str, "[VI] "); if (ha->fw_attributes & BIT_13) strcat(str, "[Experimental]"); return str; @@ -681,7 +689,7 @@ qla2xxx_eh_abort(struct scsi_cmnd *cmd) DEBUG3(qla2x00_print_scsi_cmd(cmd)); spin_unlock_irqrestore(&pha->hardware_lock, flags); - if (ha->isp_ops.abort_command(ha, sp)) { + if (ha->isp_ops->abort_command(ha, sp)) { DEBUG2(printk("%s(%ld): abort_command " "mbx failed.\n", __func__, ha->host_no)); } else { @@ -813,7 +821,7 @@ qla2xxx_eh_device_reset(struct scsi_cmnd *cmd) #if defined(LOGOUT_AFTER_DEVICE_RESET) if (ret == SUCCESS) { if (fcport->flags & FC_FABRIC_DEVICE) { - ha->isp_ops.fabric_logout(ha, fcport->loop_id); + ha->isp_ops->fabric_logout(ha, fcport->loop_id); qla2x00_mark_device_lost(ha, fcport, 0, 0); } } @@ -1105,7 +1113,7 @@ static int qla2x00_device_reset(scsi_qla_host_t *ha, fc_port_t *reset_fcport) { /* Abort Target command will clear Reservation */ - return ha->isp_ops.abort_target(reset_fcport); + return ha->isp_ops->abort_target(reset_fcport); } static int @@ -1184,8 +1192,8 @@ qla2x00_config_dma_addressing(scsi_qla_host_t *ha) !pci_set_consistent_dma_mask(ha->pdev, DMA_64BIT_MASK)) { /* Ok, a 64bit DMA mask is applicable. */ ha->flags.enable_64bit_addressing = 1; - ha->isp_ops.calc_req_entries = qla2x00_calc_iocbs_64; - ha->isp_ops.build_iocbs = qla2x00_build_scsi_iocbs_64; + ha->isp_ops->calc_req_entries = qla2x00_calc_iocbs_64; + ha->isp_ops->build_iocbs = qla2x00_build_scsi_iocbs_64; return; } } @@ -1194,6 +1202,193 @@ qla2x00_config_dma_addressing(scsi_qla_host_t *ha) pci_set_consistent_dma_mask(ha->pdev, DMA_32BIT_MASK); } +static void +qla2x00_enable_intrs(scsi_qla_host_t *ha) +{ + unsigned long flags = 0; + struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; + + spin_lock_irqsave(&ha->hardware_lock, flags); + ha->interrupts_on = 1; + /* enable risc and host interrupts */ + WRT_REG_WORD(®->ictrl, ICR_EN_INT | ICR_EN_RISC); + RD_REG_WORD(®->ictrl); + spin_unlock_irqrestore(&ha->hardware_lock, flags); + +} + +static void +qla2x00_disable_intrs(scsi_qla_host_t *ha) +{ + unsigned long flags = 0; + struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; + + spin_lock_irqsave(&ha->hardware_lock, flags); + ha->interrupts_on = 0; + /* disable risc and host interrupts */ + WRT_REG_WORD(®->ictrl, 0); + RD_REG_WORD(®->ictrl); + spin_unlock_irqrestore(&ha->hardware_lock, flags); +} + +static void +qla24xx_enable_intrs(scsi_qla_host_t *ha) +{ + unsigned long flags = 0; + struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; + + spin_lock_irqsave(&ha->hardware_lock, flags); + ha->interrupts_on = 1; + WRT_REG_DWORD(®->ictrl, ICRX_EN_RISC_INT); + RD_REG_DWORD(®->ictrl); + spin_unlock_irqrestore(&ha->hardware_lock, flags); +} + +static void +qla24xx_disable_intrs(scsi_qla_host_t *ha) +{ + unsigned long flags = 0; + struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; + + spin_lock_irqsave(&ha->hardware_lock, flags); + ha->interrupts_on = 0; + WRT_REG_DWORD(®->ictrl, 0); + RD_REG_DWORD(®->ictrl); + spin_unlock_irqrestore(&ha->hardware_lock, flags); +} + +static struct isp_operations qla2100_isp_ops = { + .pci_config = qla2100_pci_config, + .reset_chip = qla2x00_reset_chip, + .chip_diag = qla2x00_chip_diag, + .config_rings = qla2x00_config_rings, + .reset_adapter = qla2x00_reset_adapter, + .nvram_config = qla2x00_nvram_config, + .update_fw_options = qla2x00_update_fw_options, + .load_risc = qla2x00_load_risc, + .pci_info_str = qla2x00_pci_info_str, + .fw_version_str = qla2x00_fw_version_str, + .intr_handler = qla2100_intr_handler, + .enable_intrs = qla2x00_enable_intrs, + .disable_intrs = qla2x00_disable_intrs, + .abort_command = qla2x00_abort_command, + .abort_target = qla2x00_abort_target, + .fabric_login = qla2x00_login_fabric, + .fabric_logout = qla2x00_fabric_logout, + .calc_req_entries = qla2x00_calc_iocbs_32, + .build_iocbs = qla2x00_build_scsi_iocbs_32, + .prep_ms_iocb = qla2x00_prep_ms_iocb, + .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb, + .read_nvram = qla2x00_read_nvram_data, + .write_nvram = qla2x00_write_nvram_data, + .fw_dump = qla2100_fw_dump, + .beacon_on = NULL, + .beacon_off = NULL, + .beacon_blink = NULL, + .read_optrom = qla2x00_read_optrom_data, + .write_optrom = qla2x00_write_optrom_data, + .get_flash_version = qla2x00_get_flash_version, +}; + +static struct isp_operations qla2300_isp_ops = { + .pci_config = qla2300_pci_config, + .reset_chip = qla2x00_reset_chip, + .chip_diag = qla2x00_chip_diag, + .config_rings = qla2x00_config_rings, + .reset_adapter = qla2x00_reset_adapter, + .nvram_config = qla2x00_nvram_config, + .update_fw_options = qla2x00_update_fw_options, + .load_risc = qla2x00_load_risc, + .pci_info_str = qla2x00_pci_info_str, + .fw_version_str = qla2x00_fw_version_str, + .intr_handler = qla2300_intr_handler, + .enable_intrs = qla2x00_enable_intrs, + .disable_intrs = qla2x00_disable_intrs, + .abort_command = qla2x00_abort_command, + .abort_target = qla2x00_abort_target, + .fabric_login = qla2x00_login_fabric, + .fabric_logout = qla2x00_fabric_logout, + .calc_req_entries = qla2x00_calc_iocbs_32, + .build_iocbs = qla2x00_build_scsi_iocbs_32, + .prep_ms_iocb = qla2x00_prep_ms_iocb, + .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb, + .read_nvram = qla2x00_read_nvram_data, + .write_nvram = qla2x00_write_nvram_data, + .fw_dump = qla2300_fw_dump, + .beacon_on = qla2x00_beacon_on, + .beacon_off = qla2x00_beacon_off, + .beacon_blink = qla2x00_beacon_blink, + .read_optrom = qla2x00_read_optrom_data, + .write_optrom = qla2x00_write_optrom_data, + .get_flash_version = qla2x00_get_flash_version, +}; + +static struct isp_operations qla24xx_isp_ops = { + .pci_config = qla24xx_pci_config, + .reset_chip = qla24xx_reset_chip, + .chip_diag = qla24xx_chip_diag, + .config_rings = qla24xx_config_rings, + .reset_adapter = qla24xx_reset_adapter, + .nvram_config = qla24xx_nvram_config, + .update_fw_options = qla24xx_update_fw_options, + .load_risc = qla24xx_load_risc, + .pci_info_str = qla24xx_pci_info_str, + .fw_version_str = qla24xx_fw_version_str, + .intr_handler = qla24xx_intr_handler, + .enable_intrs = qla24xx_enable_intrs, + .disable_intrs = qla24xx_disable_intrs, + .abort_command = qla24xx_abort_command, + .abort_target = qla24xx_abort_target, + .fabric_login = qla24xx_login_fabric, + .fabric_logout = qla24xx_fabric_logout, + .calc_req_entries = NULL, + .build_iocbs = NULL, + .prep_ms_iocb = qla24xx_prep_ms_iocb, + .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, + .read_nvram = qla24xx_read_nvram_data, + .write_nvram = qla24xx_write_nvram_data, + .fw_dump = qla24xx_fw_dump, + .beacon_on = qla24xx_beacon_on, + .beacon_off = qla24xx_beacon_off, + .beacon_blink = qla24xx_beacon_blink, + .read_optrom = qla24xx_read_optrom_data, + .write_optrom = qla24xx_write_optrom_data, + .get_flash_version = qla24xx_get_flash_version, +}; + +static struct isp_operations qla25xx_isp_ops = { + .pci_config = qla25xx_pci_config, + .reset_chip = qla24xx_reset_chip, + .chip_diag = qla24xx_chip_diag, + .config_rings = qla24xx_config_rings, + .reset_adapter = qla24xx_reset_adapter, + .nvram_config = qla24xx_nvram_config, + .update_fw_options = qla24xx_update_fw_options, + .load_risc = qla24xx_load_risc, + .pci_info_str = qla24xx_pci_info_str, + .fw_version_str = qla24xx_fw_version_str, + .intr_handler = qla24xx_intr_handler, + .enable_intrs = qla24xx_enable_intrs, + .disable_intrs = qla24xx_disable_intrs, + .abort_command = qla24xx_abort_command, + .abort_target = qla24xx_abort_target, + .fabric_login = qla24xx_login_fabric, + .fabric_logout = qla24xx_fabric_logout, + .calc_req_entries = NULL, + .build_iocbs = NULL, + .prep_ms_iocb = qla24xx_prep_ms_iocb, + .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, + .read_nvram = qla25xx_read_nvram_data, + .write_nvram = qla25xx_write_nvram_data, + .fw_dump = qla25xx_fw_dump, + .beacon_on = qla24xx_beacon_on, + .beacon_off = qla24xx_beacon_off, + .beacon_blink = qla24xx_beacon_blink, + .read_optrom = qla24xx_read_optrom_data, + .write_optrom = qla24xx_write_optrom_data, + .get_flash_version = qla24xx_get_flash_version, +}; + static inline void qla2x00_set_isp_flags(scsi_qla_host_t *ha) { @@ -1238,19 +1433,32 @@ qla2x00_set_isp_flags(scsi_qla_host_t *ha) case PCI_DEVICE_ID_QLOGIC_ISP2422: ha->device_type |= DT_ISP2422; ha->device_type |= DT_ZIO_SUPPORTED; + ha->device_type |= DT_FWI2; + ha->device_type |= DT_IIDMA; ha->fw_srisc_address = RISC_START_ADDRESS_2400; break; case PCI_DEVICE_ID_QLOGIC_ISP2432: ha->device_type |= DT_ISP2432; ha->device_type |= DT_ZIO_SUPPORTED; + ha->device_type |= DT_FWI2; + ha->device_type |= DT_IIDMA; ha->fw_srisc_address = RISC_START_ADDRESS_2400; break; case PCI_DEVICE_ID_QLOGIC_ISP5422: ha->device_type |= DT_ISP5422; + ha->device_type |= DT_FWI2; ha->fw_srisc_address = RISC_START_ADDRESS_2400; break; case PCI_DEVICE_ID_QLOGIC_ISP5432: ha->device_type |= DT_ISP5432; + ha->device_type |= DT_FWI2; + ha->fw_srisc_address = RISC_START_ADDRESS_2400; + break; + case PCI_DEVICE_ID_QLOGIC_ISP2532: + ha->device_type |= DT_ISP2532; + ha->device_type |= DT_ZIO_SUPPORTED; + ha->device_type |= DT_FWI2; + ha->device_type |= DT_IIDMA; ha->fw_srisc_address = RISC_START_ADDRESS_2400; break; } @@ -1323,61 +1531,6 @@ iospace_error_exit: } static void -qla2x00_enable_intrs(scsi_qla_host_t *ha) -{ - unsigned long flags = 0; - struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; - - spin_lock_irqsave(&ha->hardware_lock, flags); - ha->interrupts_on = 1; - /* enable risc and host interrupts */ - WRT_REG_WORD(®->ictrl, ICR_EN_INT | ICR_EN_RISC); - RD_REG_WORD(®->ictrl); - spin_unlock_irqrestore(&ha->hardware_lock, flags); - -} - -static void -qla2x00_disable_intrs(scsi_qla_host_t *ha) -{ - unsigned long flags = 0; - struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; - - spin_lock_irqsave(&ha->hardware_lock, flags); - ha->interrupts_on = 0; - /* disable risc and host interrupts */ - WRT_REG_WORD(®->ictrl, 0); - RD_REG_WORD(®->ictrl); - spin_unlock_irqrestore(&ha->hardware_lock, flags); -} - -static void -qla24xx_enable_intrs(scsi_qla_host_t *ha) -{ - unsigned long flags = 0; - struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; - - spin_lock_irqsave(&ha->hardware_lock, flags); - ha->interrupts_on = 1; - WRT_REG_DWORD(®->ictrl, ICRX_EN_RISC_INT); - RD_REG_DWORD(®->ictrl); - spin_unlock_irqrestore(&ha->hardware_lock, flags); -} - -static void -qla24xx_disable_intrs(scsi_qla_host_t *ha) -{ - unsigned long flags = 0; - struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; - - spin_lock_irqsave(&ha->hardware_lock, flags); - ha->interrupts_on = 0; - WRT_REG_DWORD(®->ictrl, 0); - RD_REG_DWORD(®->ictrl); - spin_unlock_irqrestore(&ha->hardware_lock, flags); -} - -static void qla2xxx_scan_start(struct Scsi_Host *shost) { scsi_qla_host_t *ha = (scsi_qla_host_t *)shost->hostdata; @@ -1422,7 +1575,8 @@ qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id) if (pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2422 || pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2432 || pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5422 || - pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5432) + pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5432 || + pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2532) sht = &qla24xx_driver_template; host = scsi_host_alloc(sht, sizeof(scsi_qla_host_t)); if (host == NULL) { @@ -1466,33 +1620,6 @@ qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id) ha->max_q_depth = ql2xmaxqdepth; /* Assign ISP specific operations. */ - ha->isp_ops.pci_config = qla2100_pci_config; - ha->isp_ops.reset_chip = qla2x00_reset_chip; - ha->isp_ops.chip_diag = qla2x00_chip_diag; - ha->isp_ops.config_rings = qla2x00_config_rings; - ha->isp_ops.reset_adapter = qla2x00_reset_adapter; - ha->isp_ops.nvram_config = qla2x00_nvram_config; - ha->isp_ops.update_fw_options = qla2x00_update_fw_options; - ha->isp_ops.load_risc = qla2x00_load_risc; - ha->isp_ops.pci_info_str = qla2x00_pci_info_str; - ha->isp_ops.fw_version_str = qla2x00_fw_version_str; - ha->isp_ops.intr_handler = qla2100_intr_handler; - ha->isp_ops.enable_intrs = qla2x00_enable_intrs; - ha->isp_ops.disable_intrs = qla2x00_disable_intrs; - ha->isp_ops.abort_command = qla2x00_abort_command; - ha->isp_ops.abort_target = qla2x00_abort_target; - ha->isp_ops.fabric_login = qla2x00_login_fabric; - ha->isp_ops.fabric_logout = qla2x00_fabric_logout; - ha->isp_ops.calc_req_entries = qla2x00_calc_iocbs_32; - ha->isp_ops.build_iocbs = qla2x00_build_scsi_iocbs_32; - ha->isp_ops.prep_ms_iocb = qla2x00_prep_ms_iocb; - ha->isp_ops.prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb; - ha->isp_ops.read_nvram = qla2x00_read_nvram_data; - ha->isp_ops.write_nvram = qla2x00_write_nvram_data; - ha->isp_ops.fw_dump = qla2100_fw_dump; - ha->isp_ops.read_optrom = qla2x00_read_optrom_data; - ha->isp_ops.write_optrom = qla2x00_write_optrom_data; - ha->isp_ops.get_flash_version = qla2x00_get_flash_version; if (IS_QLA2100(ha)) { host->max_id = MAX_TARGETS_2100; ha->mbx_count = MAILBOX_REGISTER_COUNT_2100; @@ -1501,6 +1628,7 @@ qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id) ha->last_loop_id = SNS_LAST_LOOP_ID_2100; host->sg_tablesize = 32; ha->gid_list_info_size = 4; + ha->isp_ops = &qla2100_isp_ops; } else if (IS_QLA2200(ha)) { host->max_id = MAX_TARGETS_2200; ha->mbx_count = MAILBOX_REGISTER_COUNT; @@ -1508,21 +1636,17 @@ qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id) ha->response_q_length = RESPONSE_ENTRY_CNT_2100; ha->last_loop_id = SNS_LAST_LOOP_ID_2100; ha->gid_list_info_size = 4; + ha->isp_ops = &qla2100_isp_ops; } else if (IS_QLA23XX(ha)) { host->max_id = MAX_TARGETS_2200; ha->mbx_count = MAILBOX_REGISTER_COUNT; ha->request_q_length = REQUEST_ENTRY_CNT_2200; ha->response_q_length = RESPONSE_ENTRY_CNT_2300; ha->last_loop_id = SNS_LAST_LOOP_ID_2300; - ha->isp_ops.pci_config = qla2300_pci_config; - ha->isp_ops.intr_handler = qla2300_intr_handler; - ha->isp_ops.fw_dump = qla2300_fw_dump; - ha->isp_ops.beacon_on = qla2x00_beacon_on; - ha->isp_ops.beacon_off = qla2x00_beacon_off; - ha->isp_ops.beacon_blink = qla2x00_beacon_blink; ha->gid_list_info_size = 6; if (IS_QLA2322(ha) || IS_QLA6322(ha)) ha->optrom_size = OPTROM_SIZE_2322; + ha->isp_ops = &qla2300_isp_ops; } else if (IS_QLA24XX(ha) || IS_QLA54XX(ha)) { host->max_id = MAX_TARGETS_2200; ha->mbx_count = MAILBOX_REGISTER_COUNT; @@ -1531,36 +1655,20 @@ qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id) ha->last_loop_id = SNS_LAST_LOOP_ID_2300; ha->init_cb_size = sizeof(struct mid_init_cb_24xx); ha->mgmt_svr_loop_id = 10 + ha->vp_idx; - ha->isp_ops.pci_config = qla24xx_pci_config; - ha->isp_ops.reset_chip = qla24xx_reset_chip; - ha->isp_ops.chip_diag = qla24xx_chip_diag; - ha->isp_ops.config_rings = qla24xx_config_rings; - ha->isp_ops.reset_adapter = qla24xx_reset_adapter; - ha->isp_ops.nvram_config = qla24xx_nvram_config; - ha->isp_ops.update_fw_options = qla24xx_update_fw_options; - ha->isp_ops.load_risc = qla24xx_load_risc; - ha->isp_ops.pci_info_str = qla24xx_pci_info_str; - ha->isp_ops.fw_version_str = qla24xx_fw_version_str; - ha->isp_ops.intr_handler = qla24xx_intr_handler; - ha->isp_ops.enable_intrs = qla24xx_enable_intrs; - ha->isp_ops.disable_intrs = qla24xx_disable_intrs; - ha->isp_ops.abort_command = qla24xx_abort_command; - ha->isp_ops.abort_target = qla24xx_abort_target; - ha->isp_ops.fabric_login = qla24xx_login_fabric; - ha->isp_ops.fabric_logout = qla24xx_fabric_logout; - ha->isp_ops.prep_ms_iocb = qla24xx_prep_ms_iocb; - ha->isp_ops.prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb; - ha->isp_ops.read_nvram = qla24xx_read_nvram_data; - ha->isp_ops.write_nvram = qla24xx_write_nvram_data; - ha->isp_ops.fw_dump = qla24xx_fw_dump; - ha->isp_ops.read_optrom = qla24xx_read_optrom_data; - ha->isp_ops.write_optrom = qla24xx_write_optrom_data; - ha->isp_ops.beacon_on = qla24xx_beacon_on; - ha->isp_ops.beacon_off = qla24xx_beacon_off; - ha->isp_ops.beacon_blink = qla24xx_beacon_blink; - ha->isp_ops.get_flash_version = qla24xx_get_flash_version; ha->gid_list_info_size = 8; ha->optrom_size = OPTROM_SIZE_24XX; + ha->isp_ops = &qla24xx_isp_ops; + } else if (IS_QLA25XX(ha)) { + host->max_id = MAX_TARGETS_2200; + ha->mbx_count = MAILBOX_REGISTER_COUNT; + ha->request_q_length = REQUEST_ENTRY_CNT_24XX; + ha->response_q_length = RESPONSE_ENTRY_CNT_2300; + ha->last_loop_id = SNS_LAST_LOOP_ID_2300; + ha->init_cb_size = sizeof(struct mid_init_cb_24xx); + ha->mgmt_svr_loop_id = 10 + ha->vp_idx; + ha->gid_list_info_size = 8; + ha->optrom_size = OPTROM_SIZE_25XX; + ha->isp_ops = &qla25xx_isp_ops; } host->can_queue = ha->request_q_length + 128; @@ -1628,11 +1736,11 @@ qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id) DEBUG2(printk("DEBUG: detect hba %ld at address = %p\n", ha->host_no, ha)); - ha->isp_ops.disable_intrs(ha); + ha->isp_ops->disable_intrs(ha); spin_lock_irqsave(&ha->hardware_lock, flags); reg = ha->iobase; - if (IS_QLA24XX(ha) || IS_QLA54XX(ha)) { + if (IS_FWI2_CAPABLE(ha)) { WRT_REG_DWORD(®->isp24.hccr, HCCRX_CLR_HOST_INT); WRT_REG_DWORD(®->isp24.hccr, HCCRX_CLR_RISC_INT); } else { @@ -1654,7 +1762,7 @@ qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id) } spin_unlock_irqrestore(&ha->hardware_lock, flags); - ha->isp_ops.enable_intrs(ha); + ha->isp_ops->enable_intrs(ha); pci_set_drvdata(pdev, ha); @@ -1679,9 +1787,9 @@ qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id) " ISP%04X: %s @ %s hdma%c, host#=%ld, fw=%s\n", qla2x00_version_str, ha->model_number, ha->model_desc ? ha->model_desc: "", pdev->device, - ha->isp_ops.pci_info_str(ha, pci_info), pci_name(pdev), + ha->isp_ops->pci_info_str(ha, pci_info), pci_name(pdev), ha->flags.enable_64bit_addressing ? '+': '-', ha->host_no, - ha->isp_ops.fw_version_str(ha, fw_str)); + ha->isp_ops->fw_version_str(ha, fw_str)); return 0; @@ -1747,7 +1855,7 @@ qla2x00_free_device(scsi_qla_host_t *ha) /* turn-off interrupts on the card */ if (ha->interrupts_on) - ha->isp_ops.disable_intrs(ha); + ha->isp_ops->disable_intrs(ha); qla2x00_mem_free(ha); @@ -2025,7 +2133,7 @@ qla2x00_mem_alloc(scsi_qla_host_t *ha) } memset(ha->ct_sns, 0, sizeof(struct ct_sns_pkt)); - if (IS_QLA24XX(ha) || IS_QLA54XX(ha)) { + if (IS_FWI2_CAPABLE(ha)) { /* * Get consistent memory allocated for SFP * block. @@ -2305,7 +2413,7 @@ qla2x00_do_dpc(void *data) if (fcport->flags & FCF_FABRIC_DEVICE) { if (fcport->flags & FCF_TAPE_PRESENT) - ha->isp_ops.fabric_logout( + ha->isp_ops->fabric_logout( ha, fcport->loop_id, fcport->d_id.b.domain, fcport->d_id.b.area, @@ -2385,10 +2493,10 @@ qla2x00_do_dpc(void *data) } if (!ha->interrupts_on) - ha->isp_ops.enable_intrs(ha); + ha->isp_ops->enable_intrs(ha); if (test_and_clear_bit(BEACON_BLINK_NEEDED, &ha->dpc_flags)) - ha->isp_ops.beacon_blink(ha); + ha->isp_ops->beacon_blink(ha); qla2x00_do_dpc_all_vps(ha); @@ -2617,18 +2725,20 @@ qla2x00_down_timeout(struct semaphore *sema, unsigned long timeout) /* Firmware interface routines. */ -#define FW_BLOBS 5 +#define FW_BLOBS 6 #define FW_ISP21XX 0 #define FW_ISP22XX 1 #define FW_ISP2300 2 #define FW_ISP2322 3 #define FW_ISP24XX 4 +#define FW_ISP25XX 5 #define FW_FILE_ISP21XX "ql2100_fw.bin" #define FW_FILE_ISP22XX "ql2200_fw.bin" #define FW_FILE_ISP2300 "ql2300_fw.bin" #define FW_FILE_ISP2322 "ql2322_fw.bin" #define FW_FILE_ISP24XX "ql2400_fw.bin" +#define FW_FILE_ISP25XX "ql2500_fw.bin" static DECLARE_MUTEX(qla_fw_lock); @@ -2638,6 +2748,7 @@ static struct fw_blob qla_fw_blobs[FW_BLOBS] = { { .name = FW_FILE_ISP2300, .segs = { 0x800, 0 }, }, { .name = FW_FILE_ISP2322, .segs = { 0x800, 0x1c000, 0x1e000, 0 }, }, { .name = FW_FILE_ISP24XX, }, + { .name = FW_FILE_ISP25XX, }, }; struct fw_blob * @@ -2656,6 +2767,8 @@ qla2x00_request_firmware(scsi_qla_host_t *ha) blob = &qla_fw_blobs[FW_ISP2322]; } else if (IS_QLA24XX(ha) || IS_QLA54XX(ha)) { blob = &qla_fw_blobs[FW_ISP24XX]; + } else if (IS_QLA25XX(ha)) { + blob = &qla_fw_blobs[FW_ISP25XX]; } down(&qla_fw_lock); @@ -2699,6 +2812,7 @@ static struct pci_device_id qla2xxx_pci_tbl[] = { { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2432) }, { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5422) }, { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5432) }, + { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2532) }, { 0 }, }; MODULE_DEVICE_TABLE(pci, qla2xxx_pci_tbl); diff --git a/drivers/scsi/qla2xxx/qla_sup.c b/drivers/scsi/qla2xxx/qla_sup.c index 206bda093da2..a925a3f179f9 100644 --- a/drivers/scsi/qla2xxx/qla_sup.c +++ b/drivers/scsi/qla2xxx/qla_sup.c @@ -766,6 +766,29 @@ qla24xx_write_nvram_data(scsi_qla_host_t *ha, uint8_t *buf, uint32_t naddr, return ret; } +uint8_t * +qla25xx_read_nvram_data(scsi_qla_host_t *ha, uint8_t *buf, uint32_t naddr, + uint32_t bytes) +{ + uint32_t i; + uint32_t *dwptr; + + /* Dword reads to flash. */ + dwptr = (uint32_t *)buf; + for (i = 0; i < bytes >> 2; i++, naddr++) + dwptr[i] = cpu_to_le32(qla24xx_read_flash_dword(ha, + flash_data_to_access_addr(FA_VPD_NVRAM_ADDR | naddr))); + + return buf; +} + +int +qla25xx_write_nvram_data(scsi_qla_host_t *ha, uint8_t *buf, uint32_t naddr, + uint32_t bytes) +{ + return qla24xx_write_flash_data(ha, (uint32_t *)buf, + FA_VPD_NVRAM_ADDR | naddr, bytes >> 2); +} static inline void qla2x00_flip_colors(scsi_qla_host_t *ha, uint16_t *pflags) @@ -919,7 +942,7 @@ qla2x00_beacon_off(struct scsi_qla_host *ha) else ha->beacon_color_state = QLA_LED_GRN_ON; - ha->isp_ops.beacon_blink(ha); /* This turns green LED off */ + ha->isp_ops->beacon_blink(ha); /* This turns green LED off */ ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING; ha->fw_options[1] &= ~FO1_DISABLE_GPIO6_7; @@ -1031,7 +1054,7 @@ qla24xx_beacon_off(struct scsi_qla_host *ha) ha->beacon_blink_led = 0; ha->beacon_color_state = QLA_LED_ALL_ON; - ha->isp_ops.beacon_blink(ha); /* Will flip to all off. */ + ha->isp_ops->beacon_blink(ha); /* Will flip to all off. */ /* Give control back to firmware. */ spin_lock_irqsave(&ha->hardware_lock, flags); @@ -1419,7 +1442,7 @@ qla2x00_suspend_hba(struct scsi_qla_host *ha) /* Suspend HBA. */ scsi_block_requests(ha->host); - ha->isp_ops.disable_intrs(ha); + ha->isp_ops->disable_intrs(ha); set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags); /* Pause RISC. */ @@ -1705,7 +1728,7 @@ qla24xx_read_optrom_data(struct scsi_qla_host *ha, uint8_t *buf, { /* Suspend HBA. */ scsi_block_requests(ha->host); - ha->isp_ops.disable_intrs(ha); + ha->isp_ops->disable_intrs(ha); set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags); /* Go with read. */ @@ -1713,7 +1736,7 @@ qla24xx_read_optrom_data(struct scsi_qla_host *ha, uint8_t *buf, /* Resume HBA. */ clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags); - ha->isp_ops.enable_intrs(ha); + ha->isp_ops->enable_intrs(ha); scsi_unblock_requests(ha->host); return buf; @@ -1727,7 +1750,7 @@ qla24xx_write_optrom_data(struct scsi_qla_host *ha, uint8_t *buf, /* Suspend HBA. */ scsi_block_requests(ha->host); - ha->isp_ops.disable_intrs(ha); + ha->isp_ops->disable_intrs(ha); set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags); /* Go with write. */ diff --git a/drivers/scsi/qla2xxx/qla_version.h b/drivers/scsi/qla2xxx/qla_version.h index fd2f10a25348..dd1f8ceb79c4 100644 --- a/drivers/scsi/qla2xxx/qla_version.h +++ b/drivers/scsi/qla2xxx/qla_version.h @@ -7,7 +7,7 @@ /* * Driver version */ -#define QLA2XXX_VERSION "8.02.00-k1" +#define QLA2XXX_VERSION "8.02.00-k2" #define QLA_DRIVER_MAJOR_VER 8 #define QLA_DRIVER_MINOR_VER 2 |