diff options
Diffstat (limited to 'drivers/phy/qualcomm/phy-qcom-qmp.h')
| -rw-r--r-- | drivers/phy/qualcomm/phy-qcom-qmp.h | 37 |
1 files changed, 19 insertions, 18 deletions
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.h b/drivers/phy/qualcomm/phy-qcom-qmp.h index 71ce3aa174ae..981d8ee891c0 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp.h +++ b/drivers/phy/qualcomm/phy-qcom-qmp.h @@ -349,13 +349,13 @@ #define QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG4 0x5c #define QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG5 0x60 -/* Only for QMP V3 PHY - DP PHY registers */ -#define QSERDES_V3_DP_PHY_REVISION_ID0 0x000 -#define QSERDES_V3_DP_PHY_REVISION_ID1 0x004 -#define QSERDES_V3_DP_PHY_REVISION_ID2 0x008 -#define QSERDES_V3_DP_PHY_REVISION_ID3 0x00c -#define QSERDES_V3_DP_PHY_CFG 0x010 -#define QSERDES_V3_DP_PHY_PD_CTL 0x018 +/* QMP PHY - DP PHY registers */ +#define QSERDES_DP_PHY_REVISION_ID0 0x000 +#define QSERDES_DP_PHY_REVISION_ID1 0x004 +#define QSERDES_DP_PHY_REVISION_ID2 0x008 +#define QSERDES_DP_PHY_REVISION_ID3 0x00c +#define QSERDES_DP_PHY_CFG 0x010 +#define QSERDES_DP_PHY_PD_CTL 0x018 # define DP_PHY_PD_CTL_PWRDN 0x001 # define DP_PHY_PD_CTL_PSR_PWRDN 0x002 # define DP_PHY_PD_CTL_AUX_PWRDN 0x004 @@ -363,18 +363,19 @@ # define DP_PHY_PD_CTL_LANE_2_3_PWRDN 0x010 # define DP_PHY_PD_CTL_PLL_PWRDN 0x020 # define DP_PHY_PD_CTL_DP_CLAMP_EN 0x040 -#define QSERDES_V3_DP_PHY_MODE 0x01c -#define QSERDES_V3_DP_PHY_AUX_CFG0 0x020 -#define QSERDES_V3_DP_PHY_AUX_CFG1 0x024 -#define QSERDES_V3_DP_PHY_AUX_CFG2 0x028 -#define QSERDES_V3_DP_PHY_AUX_CFG3 0x02c -#define QSERDES_V3_DP_PHY_AUX_CFG4 0x030 -#define QSERDES_V3_DP_PHY_AUX_CFG5 0x034 -#define QSERDES_V3_DP_PHY_AUX_CFG6 0x038 -#define QSERDES_V3_DP_PHY_AUX_CFG7 0x03c -#define QSERDES_V3_DP_PHY_AUX_CFG8 0x040 -#define QSERDES_V3_DP_PHY_AUX_CFG9 0x044 +#define QSERDES_DP_PHY_MODE 0x01c +#define QSERDES_DP_PHY_AUX_CFG0 0x020 +#define QSERDES_DP_PHY_AUX_CFG1 0x024 +#define QSERDES_DP_PHY_AUX_CFG2 0x028 +#define QSERDES_DP_PHY_AUX_CFG3 0x02c +#define QSERDES_DP_PHY_AUX_CFG4 0x030 +#define QSERDES_DP_PHY_AUX_CFG5 0x034 +#define QSERDES_DP_PHY_AUX_CFG6 0x038 +#define QSERDES_DP_PHY_AUX_CFG7 0x03c +#define QSERDES_DP_PHY_AUX_CFG8 0x040 +#define QSERDES_DP_PHY_AUX_CFG9 0x044 +/* Only for QMP V3 PHY - DP PHY registers */ #define QSERDES_V3_DP_PHY_AUX_INTERRUPT_MASK 0x048 # define PHY_AUX_STOP_ERR_MASK 0x01 # define PHY_AUX_DEC_ERR_MASK 0x02 |