diff options
| author | yitian <yitian.bu@tangramtek.com> | 2015-09-29 22:43:17 +0800 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2015-10-02 18:05:51 +0100 |
| commit | 924eb475126fd6bc23c475ac742a69fc466c0b75 (patch) | |
| tree | ce3a86099de66c43cb195a10e13fa715f450e675 /sound | |
| parent | 4873867e5f2bd90faad861dd94865099fc3140f3 (diff) | |
| download | linux-924eb475126fd6bc23c475ac742a69fc466c0b75.tar.gz | |
ASoC: dwc: fix dma stop transferring issue
Designware I2S uses tx empty and rx available signals as the DMA handshaking signals. during music playing, if XRUN occurs, i2s_stop() function will be executed and both tx and rx irq are masked, when music continues to be played, i2s_start() is executed but both tx and rx irq are not unmasked which cause I2S stop sending DMA handshaking signal to DMA controller, and it finally causes music playing will be stopped once XRUN occurs for the first time. [On list discussion suggests this may be partly a race condition on slow systems -- broonie] Signed-off-by: Yitian Bu <yitian.bu@tangramtek.com> Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'sound')
| -rw-r--r-- | sound/soc/dwc/designware_i2s.c | 15 |
1 files changed, 12 insertions, 3 deletions
diff --git a/sound/soc/dwc/designware_i2s.c b/sound/soc/dwc/designware_i2s.c index 0d28e3b356f6..ba34252b7bba 100644 --- a/sound/soc/dwc/designware_i2s.c +++ b/sound/soc/dwc/designware_i2s.c @@ -141,13 +141,22 @@ static inline void i2s_clear_irqs(struct dw_i2s_dev *dev, u32 stream) static void i2s_start(struct dw_i2s_dev *dev, struct snd_pcm_substream *substream) { - + u32 i, irq; i2s_write_reg(dev->i2s_base, IER, 1); - if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { + for (i = 0; i < 4; i++) { + irq = i2s_read_reg(dev->i2s_base, IMR(i)); + i2s_write_reg(dev->i2s_base, IMR(i), irq & ~0x30); + } i2s_write_reg(dev->i2s_base, ITER, 1); - else + } else { + for (i = 0; i < 4; i++) { + irq = i2s_read_reg(dev->i2s_base, IMR(i)); + i2s_write_reg(dev->i2s_base, IMR(i), irq & ~0x03); + } i2s_write_reg(dev->i2s_base, IRER, 1); + } i2s_write_reg(dev->i2s_base, CER, 1); } |