diff options
| author | Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com> | 2022-09-20 15:16:58 +0200 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2022-09-20 19:07:29 +0100 |
| commit | c712be3427ca7b76800f335a6cfabdddab380c27 (patch) | |
| tree | 1e1f7b99d0f13dfdc7aa6d065efddbdcbe35b2bb /sound/soc/sof/intel/hda.h | |
| parent | 556eb41622b01c50dbc330e03bad2b0a5a082428 (diff) | |
| download | linux-c712be3427ca7b76800f335a6cfabdddab380c27.tar.gz | |
ASoC: SOF: Intel: add SKL/KBL hardware code loader
This patch adds support for the SkyLake and KabyLake code loader on top of the SOF IPC4. The work was initially contributed in 2018 by Liam Girdwood and Zhu Yingjiang, and abandoned due to firmware signature issues. With the existing support of IPC v4, it's time to re-add this capability. This patch uses the newly added FSR (Firmware State Register) definitions for DSP state handling and targeting, ass well as new state definition for SKL which indicates that the firmware has been started (similar to FW_ENTERED on other platforms). Co-developed-by: Ranjani Sridharan <ranjani.sridharan@linux.intel.com> Signed-off-by: Ranjani Sridharan <ranjani.sridharan@linux.intel.com> Co-developed-by: Peter Ujfalusi <peter.ujfalusi@linux.intel.com> Signed-off-by: Peter Ujfalusi <peter.ujfalusi@linux.intel.com> Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com> Link: https://lore.kernel.org/r/20220920131700.133103-3-pierre-louis.bossart@linux.intel.com Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'sound/soc/sof/intel/hda.h')
| -rw-r--r-- | sound/soc/sof/intel/hda.h | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/sound/soc/sof/intel/hda.h b/sound/soc/sof/intel/hda.h index 04b730f754d7..6ad8dafce098 100644 --- a/sound/soc/sof/intel/hda.h +++ b/sound/soc/sof/intel/hda.h @@ -229,6 +229,7 @@ #define FSR_STATE_ROM_GET_LOAD_OFFSET 0x7 #define FSR_STATE_ROM_FETCH_ROM_EXT 0x8 #define FSR_STATE_ROM_FETCH_ROM_EXT_DONE 0x9 +#define FSR_STATE_ROM_BASEFW_ENTERED 0xf /* SKL */ /* (ROM) CSE states */ #define FSR_STATE_ROM_CSE_IMR_REQUEST 0x10 @@ -514,6 +515,9 @@ struct sof_intel_hda_dev { /* FW clock config, 0:HPRO, 1:LPRO */ bool clk_config_lpro; + wait_queue_head_t waitq; + bool code_loading; + /* Intel NHLT information */ struct nhlt_acpi_table *nhlt; }; @@ -834,6 +838,8 @@ extern int sof_hda_position_quirk; void hda_set_dai_drv_ops(struct snd_sof_dev *sdev, struct snd_sof_dsp_ops *ops); void hda_ops_free(struct snd_sof_dev *sdev); +/* SKL/KBL */ +int hda_dsp_cl_boot_firmware_skl(struct snd_sof_dev *sdev); int hda_dsp_core_stall_reset(struct snd_sof_dev *sdev, unsigned int core_mask); /* IPC4 */ |