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author | Catalin Marinas <catalin.marinas@arm.com> | 2012-01-25 11:54:22 +0100 |
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committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2012-02-02 17:37:42 +0000 |
commit | 6d3ec1ae6cdcda185bd9452b2daed5145e2493a5 (patch) | |
tree | dabf4577ba47d2f7b70741c94353c94f1770b9f8 /lib/uuid.c | |
parent | 91756acb58b17aee68d055fc15b1e2550ff00801 (diff) | |
download | linux-6d3ec1ae6cdcda185bd9452b2daed5145e2493a5.tar.gz |
ARM: 7302/1: Add TLB flushing for both entries in a PMD
Linux uses two PMD entries for a PTE with the classic page table format, covering 2MB range. However, the __pte_free_tlb() function only adds a single TLB flush corresponding to 1MB range covering 'addr'. On Cortex-A15, level 1 entries can be cached by the TLB independently of the level 2 entries and without additional flushing a PMD entry would be left pointing at the wrong PTE. The patch limits the TLB flushing range to two 4KB pages around the 1MB boundary within PMD. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'lib/uuid.c')
0 files changed, 0 insertions, 0 deletions