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author | Robin Murphy <robin.murphy@arm.com> | 2022-12-15 16:51:55 +0000 |
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committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2023-01-18 11:58:21 +0100 |
commit | bad1a2194485fa7c8d727c06d26c70676901db8a (patch) | |
tree | d7e3895e64f62a1ec34104bd1ff5f8432250428c /kernel/sched | |
parent | a1b9c7b1978aacf4b2f33e34bde1e2bb80b8497a (diff) | |
download | linux-bad1a2194485fa7c8d727c06d26c70676901db8a.tar.gz |
iommu/arm-smmu: Report IOMMU_CAP_CACHE_COHERENCY even betterer
commit ac9c5e92dd15b9927e7355ccf79df76a58b44344 upstream. Although it's vanishingly unlikely that anyone would integrate an SMMU within a coherent interconnect without also making the pagetable walk interface coherent, the same effect happens if a coherent SMMU fails to advertise CTTW correctly. This turns out to be the case on some popular NXP SoCs, where VFIO started failing the IOMMU_CAP_CACHE_COHERENCY test, even though IOMMU_CACHE *was* previously achieving the desired effect anyway thanks to the underlying integration. While those SoCs stand to gain some more general benefits from a firmware update to override CTTW correctly in DT/ACPI, it's also easy to work around this in Linux as well, to avoid imposing too much on affected users - since the upstream client devices *are* correctly marked as coherent, we can trivially infer their coherent paths through the SMMU as well. Reported-by: Vladimir Oltean <vladimir.oltean@nxp.com> Fixes: df198b37e72c ("iommu/arm-smmu: Report IOMMU_CAP_CACHE_COHERENCY better") Signed-off-by: Robin Murphy <robin.murphy@arm.com> Tested-by: Vladimir Oltean <vladimir.oltean@nxp.com> Link: https://lore.kernel.org/r/d6dc41952961e5c7b21acac08a8bf1eb0f69e124.1671123115.git.robin.murphy@arm.com Signed-off-by: Will Deacon <will@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'kernel/sched')
0 files changed, 0 insertions, 0 deletions