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| author | Vladimir Oltean <vladimir.oltean@nxp.com> | 2021-06-11 23:05:25 +0300 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2021-06-11 13:43:56 -0700 |
| commit | dd0721ea4c7a6c2ec8b309ff57d74d88f08d4c23 (patch) | |
| tree | 1b71de6869d88e0bd1ddfdebb0465ade16890b3b /include | |
| parent | 36641b045c839797739f9863e86e4dae2370e24f (diff) | |
| download | linux-dd0721ea4c7a6c2ec8b309ff57d74d88f08d4c23.tar.gz | |
net: pcs: xpcs: add support for NXP SJA1105
The NXP SJA1105 DSA switch integrates a Synopsys SGMII XPCS on port 4. The generic code works fine, except there is an integration issue which needs to be dealt with: in this switch, the XPCS is integrated with a PMA that has the TX lane polarity inverted by default (PLUS is MINUS, MINUS is PLUS). To obtain normal non-inverted behavior, the TX lane polarity must be inverted in the PCS, via the DIGITAL_CONTROL_2 register. We introduce a pma_config() method in xpcs_compat which is called by the phylink_pcs_config() implementation. Also, the NXP SJA1105 returns all zeroes in the PHY ID registers 2 and 3. We need to hack up an ad-hoc PHY ID (OUI is zero, device ID is 1) in order for the XPCS driver to recognize it. This PHY ID is added to the public include/linux/pcs/pcs-xpcs.h for that reason (for the sja1105 driver to be able to use it in a later patch). Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'include')
| -rw-r--r-- | include/linux/pcs/pcs-xpcs.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/include/linux/pcs/pcs-xpcs.h b/include/linux/pcs/pcs-xpcs.h index 4f1cdf6f3d4c..c594f7cdc304 100644 --- a/include/linux/pcs/pcs-xpcs.h +++ b/include/linux/pcs/pcs-xpcs.h @@ -10,6 +10,8 @@ #include <linux/phy.h> #include <linux/phylink.h> +#define NXP_SJA1105_XPCS_ID 0x00000010 + /* AN mode */ #define DW_AN_C73 1 #define DW_AN_C37_SGMII 2 |