Merge tag 'armsoc-for-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC fixes from Olof Johansson:
 "Another quiet week:

   - a fix to silence edma probe error on non-supported platforms from
     Arnd
   - a fix to enable the PL clock for Parallella, to make mainline
     usable with the SDK.
   - a somewhat verbose fix for the PLL clock tree on VF610
   - enabling of SD/MMC on one of the VF610-based boards (for testing)
   - a fix for i.MX where CONFIG_SPI used to be implicitly enabled and
     now needs to be added to the defconfig instead
   - another maintainer added for bcm2835: Lee Jones"

* tag 'armsoc-for-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc:
  ARM: dts: zynq: Enable PL clocks for Parallella
  dma: edma: move device registration to platform code
  ARM: dts: vf610: add SD node to cosmic dts
  MAINTAINERS: update bcm2835 entry
  ARM: imx: Fix the removal of CONFIG_SPI option
  ARM: imx: clk-vf610: define PLL's clock tree

1 files changed, 31 insertions, 8 deletions

diff --git a/include/dt-bindings/clock/vf610-clock.h b/include/dt-bindings/clock/vf610-clock.h
index d6b56b21539b..801c0ac50c47 100644
--- a/include/dt-bindings/clock/vf610-clock.h
+++ b/include/dt-bindings/clock/vf610-clock.h
@@ -21,24 +21,24 @@
 #define VF610_CLK_FASK_CLK_SEL		8
 #define VF610_CLK_AUDIO_EXT		9
 #define VF610_CLK_ENET_EXT		10
-#define VF610_CLK_PLL1_MAIN		11
+#define VF610_CLK_PLL1_SYS		11
 #define VF610_CLK_PLL1_PFD1		12
 #define VF610_CLK_PLL1_PFD2		13
 #define VF610_CLK_PLL1_PFD3		14
 #define VF610_CLK_PLL1_PFD4		15
-#define VF610_CLK_PLL2_MAIN		16
+#define VF610_CLK_PLL2_BUS		16
 #define VF610_CLK_PLL2_PFD1		17
 #define VF610_CLK_PLL2_PFD2		18
 #define VF610_CLK_PLL2_PFD3		19
 #define VF610_CLK_PLL2_PFD4		20
-#define VF610_CLK_PLL3_MAIN		21
+#define VF610_CLK_PLL3_USB_OTG		21
 #define VF610_CLK_PLL3_PFD1		22
 #define VF610_CLK_PLL3_PFD2		23
 #define VF610_CLK_PLL3_PFD3		24
 #define VF610_CLK_PLL3_PFD4		25
-#define VF610_CLK_PLL4_MAIN		26
-#define VF610_CLK_PLL5_MAIN		27
-#define VF610_CLK_PLL6_MAIN		28
+#define VF610_CLK_PLL4_AUDIO		26
+#define VF610_CLK_PLL5_ENET		27
+#define VF610_CLK_PLL6_VIDEO		28
 #define VF610_CLK_PLL3_MAIN_DIV		29
 #define VF610_CLK_PLL4_MAIN_DIV		30
 #define VF610_CLK_PLL6_MAIN_DIV		31
@@ -166,9 +166,32 @@
 #define VF610_CLK_DMAMUX3		153
 #define VF610_CLK_FLEXCAN0_EN		154
 #define VF610_CLK_FLEXCAN1_EN		155
-#define VF610_CLK_PLL7_MAIN		156
+#define VF610_CLK_PLL7_USB_HOST		156
 #define VF610_CLK_USBPHY0		157
 #define VF610_CLK_USBPHY1		158
-#define VF610_CLK_END			159
+#define VF610_CLK_LVDS1_IN		159
+#define VF610_CLK_ANACLK1		160
+#define VF610_CLK_PLL1_BYPASS_SRC	161
+#define VF610_CLK_PLL2_BYPASS_SRC	162
+#define VF610_CLK_PLL3_BYPASS_SRC	163
+#define VF610_CLK_PLL4_BYPASS_SRC	164
+#define VF610_CLK_PLL5_BYPASS_SRC	165
+#define VF610_CLK_PLL6_BYPASS_SRC	166
+#define VF610_CLK_PLL7_BYPASS_SRC	167
+#define VF610_CLK_PLL1			168
+#define VF610_CLK_PLL2			169
+#define VF610_CLK_PLL3			170
+#define VF610_CLK_PLL4			171
+#define VF610_CLK_PLL5			172
+#define VF610_CLK_PLL6			173
+#define VF610_CLK_PLL7			174
+#define VF610_PLL1_BYPASS		175
+#define VF610_PLL2_BYPASS		176
+#define VF610_PLL3_BYPASS		177
+#define VF610_PLL4_BYPASS		178
+#define VF610_PLL5_BYPASS		179
+#define VF610_PLL6_BYPASS		180
+#define VF610_PLL7_BYPASS		181
+#define VF610_CLK_END			182
 
 #endif /* __DT_BINDINGS_CLOCK_VF610_H */