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| author | Stephen Boyd <sboyd@kernel.org> | 2018-10-18 15:39:08 -0700 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2018-10-18 15:39:08 -0700 |
| commit | cd8ca3005269ec327643b3cc39681a6fcde16b0d (patch) | |
| tree | cc3c259675ad1c038d49e45ec4814ad75ba2c1f1 /include/dt-bindings/clock | |
| parent | 5d3a48fe2cee0d9fde91b6552362e86a8efca298 (diff) | |
| parent | 5beb1e60dba973e0b9cfb54d9735d5d4385b9d90 (diff) | |
| parent | 148edd50c80792f40f97e585ff5af8babfb7634a (diff) | |
| parent | e15d598b5c6f61785c85f6c2db3f3cec4d33e6c9 (diff) | |
| parent | 6ffeddd6bca4cb838623d0bf4134c0eb06ad7485 (diff) | |
| parent | e3aaadb0f0d64153674b9f81e3c12f95fa420e6d (diff) | |
| download | linux-cd8ca3005269ec327643b3cc39681a6fcde16b0d.tar.gz | |
Merge branches 'clk-mvebu-periph-pm', 'clk-meson', 'clk-allwinner', 'clk-mvebu-dup' and 'clk-davinci' into clk-next
- S2RAM support for Marvell mvebu periph clks * clk-mvebu-periph-pm: clk: mvebu: armada-37xx-periph: add suspend/resume support clk: mvebu: armada-37xx-periph: save the IP base address in the driver data * clk-meson: clk: meson: meson8b: use the regmap in the internal reset controller clk: meson: meson8b: register the clock controller early clk: meson-axg: pcie: drop the mpll3 clock parent clk: meson: axg: round audio system master clocks down clk: meson: clk-pll: drop hard-coded rates from pll tables clk: meson: clk-pll: remove od parameters clk: meson: clk-pll: drop CLK_GET_RATE_NOCACHE where unnecessary clk: meson: clk-pll: add enable bit * clk-allwinner: dt-bindings: clock: sun50i-a64-ccu: Add PLL_VIDEO0 macro clk: sunxi-ng: a64: Add max. rate constraint to video PLLs clk: sunxi-ng: a64: Add minimal rate for video PLLs clk: sunxi-ng: sun50i: h6: Add 2x fixed post-divider to MMC module clocks clk: sunxi-ng: a83t: Add max. rate constraint to video PLLs clk: sunxi-ng: nkmp: Add constraint for maximum rate clk: sunxi-ng: r40: Add max. rate constraint to video PLLs clk: sunxi-ng: h3/h5: Add max. rate constraint to pll-video clk: sunxi-ng: Add maximum rate constraint to NM PLLs clk: sunxi-ng: h6: fix PWM gate/reset offset clk: sunxi-ng: h6: fix bus clocks' divider position * clk-mvebu-dup: clk: mvebu: ap806: Remove superfluous of_clk_add_provider * clk-davinci: clk: davinci: kill davinci_clk_reset_assert/deassert()