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| author | Chris Wilson <chris@chris-wilson.co.uk> | 2012-07-10 10:27:08 +0100 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2012-07-26 12:56:25 +0200 |
| commit | e6994aeedcee4f71998d89d2c10c5baa419ebeac (patch) | |
| tree | 8b298417e51e2fc2dd2e191b26d504f648ffd91b /include/drm/i915_drm.h | |
| parent | 42d6ab4839799b2f246748ce663d6b023f02bb73 (diff) | |
| download | linux-e6994aeedcee4f71998d89d2c10c5baa419ebeac.tar.gz | |
drm/i915: Export ability of changing cache levels to userspace
By selecting the cache level (essentially whether or not the CPU snoops any updates to the bo, and on more recent machines whether it resides inside the CPU's last-level-cache) a userspace driver is able to then manage all of its memory within buffer objects, if it so desires. This enables the userspace driver to accelerate uploads and more importantly downloads from the GPU and to able to mix CPU and GPU rendering/activity efficiently. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> [danvet: Added code comment about where we plan to stuff platform specific cacheing control bits in the ioctl struct.] Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'include/drm/i915_drm.h')
| -rw-r--r-- | include/drm/i915_drm.h | 10 |
1 files changed, 8 insertions, 2 deletions
diff --git a/include/drm/i915_drm.h b/include/drm/i915_drm.h index 0f149fe32211..772b0d638912 100644 --- a/include/drm/i915_drm.h +++ b/include/drm/i915_drm.h @@ -716,10 +716,16 @@ struct drm_i915_gem_busy { #define I915_CACHEING_CACHED 1 struct drm_i915_gem_cacheing { - /** Handle of the buffer to set/get the cacheing level of */ + /** + * Handle of the buffer to set/get the cacheing level of. */ __u32 handle; - /** Cacheing level to apply or return value */ + /** + * Cacheing level to apply or return value + * + * bits0-15 are for generic cacheing control (i.e. the above defined + * values). bits16-31 are reserved for platform-specific variations + * (e.g. l3$ caching on gen7). */ __u32 cacheing; }; |