pinctrl-amd: Add quirk to timeout irq pin reconfiguration

Since commit 37b635b47124 ("Add support for AMD SPI controller-1 (v2)"),
which enabled the SPI bus on jupiter, the probe of cs35l41 hangs the
entire kernel, because pinctrl-amd spins forever when attempting to
reconfigure the cs35l41 irq pin with interrupts disabled and holding the
spinlock of the irq controller.  The infinite loop happens because of a
board design issue (according to AMD), that tries to use a pin that
can't even trigger the interruption that would otherwise signal the
reconfiguratiion completion.

This patch detects the condition and aborts the reconfiguration when the
problem occurs, failing the probe of the device, but allowing the kernel
to recover.

With this patch, it should be safe to reenable CONFIG_SPI_AMD.

Signed-off-by: Gabriel Krisman Bertazi <krisman@collabora.com>
[Fix conflicts while rebasing on v6.0]
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>

1 files changed, 9 insertions, 2 deletions

diff --git a/drivers/pinctrl/pinctrl-amd.c b/drivers/pinctrl/pinctrl-amd.c
index 2b6d996e393e..d14cbc27aa5f 100644
--- a/drivers/pinctrl/pinctrl-amd.c
+++ b/drivers/pinctrl/pinctrl-amd.c
@@ -30,6 +30,7 @@
 #include <linux/pinctrl/pinconf.h>
 #include <linux/pinctrl/pinconf-generic.h>
 #include <linux/pinctrl/pinmux.h>
+#include <linux/delay.h>
 
 #include "core.h"
 #include "pinctrl-utils.h"
@@ -483,6 +484,7 @@ static int amd_gpio_irq_set_type(struct irq_data *d, unsigned int type)
 	unsigned long flags;
 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 	struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
+	int timeout = 100;
 
 	raw_spin_lock_irqsave(&gpio_dev->lock, flags);
 	pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
@@ -552,11 +554,16 @@ static int amd_gpio_irq_set_type(struct irq_data *d, unsigned int type)
 	pin_reg_irq_en |= mask;
 	pin_reg_irq_en &= ~BIT(INTERRUPT_MASK_OFF);
 	writel(pin_reg_irq_en, gpio_dev->base + (d->hwirq)*4);
-	while ((readl(gpio_dev->base + (d->hwirq)*4) & mask) != mask)
-		continue;
+	while (((readl(gpio_dev->base + (d->hwirq)*4) & mask) != mask) && timeout--)
+		udelay(100);
+
 	writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
 	raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
 
+	if (timeout <= 0)
+		printk("%s: applying Cirrus quirk after timeout when setting irq pin\n",
+		       __func__);
+
 	return ret;
 }