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| author | Vincent Cheng <vincent.cheng.xh@renesas.com> | 2020-05-01 23:35:38 -0400 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2020-05-02 16:31:45 -0700 |
| commit | 425d2b1c563826cf73e204172919fb40b7c45f1d (patch) | |
| tree | 88a887ab348617f37fab2e90fe5ba76eddccebe6 /drivers/ptp/ptp_clockmatrix.h | |
| parent | d3f1cbd29fa63f1bb608603a6cd54ca7af56a68b (diff) | |
| download | linux-425d2b1c563826cf73e204172919fb40b7c45f1d.tar.gz | |
ptp: ptp_clockmatrix: Add adjphase() to support PHC write phase mode.
Add idtcm_adjphase() to support PHC write phase mode. Signed-off-by: Vincent Cheng <vincent.cheng.xh@renesas.com> Acked-by: Richard Cochran <richardcochran@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/ptp/ptp_clockmatrix.h')
| -rw-r--r-- | drivers/ptp/ptp_clockmatrix.h | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/drivers/ptp/ptp_clockmatrix.h b/drivers/ptp/ptp_clockmatrix.h index 6c1f93ab46f3..3de0eb72889c 100644 --- a/drivers/ptp/ptp_clockmatrix.h +++ b/drivers/ptp/ptp_clockmatrix.h @@ -15,6 +15,8 @@ #define FW_FILENAME "idtcm.bin" #define MAX_PHC_PLL 4 +#define MAX_ABS_WRITE_PHASE_PICOSECONDS (107374182350LL) + #define PLL_MASK_ADDR (0xFFA5) #define DEFAULT_PLL_MASK (0x04) @@ -33,8 +35,9 @@ #define POST_SM_RESET_DELAY_MS (3000) #define PHASE_PULL_IN_THRESHOLD_NS (150000) -#define TOD_WRITE_OVERHEAD_COUNT_MAX (5) -#define TOD_BYTE_COUNT (11) +#define TOD_WRITE_OVERHEAD_COUNT_MAX (5) +#define TOD_BYTE_COUNT (11) +#define WR_PHASE_SETUP_MS (5000) /* Values of DPLL_N.DPLL_MODE.PLL_MODE */ enum pll_mode { @@ -77,6 +80,7 @@ struct idtcm_channel { u16 hw_dpll_n; enum pll_mode pll_mode; u16 output_mask; + int write_phase_ready; }; struct idtcm { |