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| author | Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> | 2023-06-19 20:34:00 +0530 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2023-07-23 13:49:36 +0200 |
| commit | cf0d7b72707dcaa21e4c685721072d1234a87162 (patch) | |
| tree | 4c510d12d1981940f23d1c7a8a48d35348a24b58 /drivers/pci | |
| parent | c459365ec7ba182f8ed3fe18080ad19e606c67df (diff) | |
| download | linux-cf0d7b72707dcaa21e4c685721072d1234a87162.tar.gz | |
PCI: qcom: Disable write access to read only registers for IP v2.3.3
commit a33d700e8eea76c62120cb3dbf5e01328f18319a upstream.
In the post init sequence of v2.9.0, write access to read only registers
are not disabled after updating the registers. Fix it by disabling the
access after register update.
Link: https://lore.kernel.org/r/20230619150408.8468-2-manivannan.sadhasivam@linaro.org
Fixes: 5d76117f070d ("PCI: qcom: Add support for IPQ8074 PCIe controller")
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
Cc: <stable@vger.kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'drivers/pci')
| -rw-r--r-- | drivers/pci/controller/dwc/pcie-qcom.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 49905b2a9960..d24712a76ba7 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -1176,6 +1176,8 @@ static int qcom_pcie_post_init_2_3_3(struct qcom_pcie *pcie) writel(PCI_EXP_DEVCTL2_COMP_TMOUT_DIS, pci->dbi_base + offset + PCI_EXP_DEVCTL2); + dw_pcie_dbi_ro_wr_dis(pci); + return 0; } |