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author | Kalle Valo <kvalo@codeaurora.org> | 2021-02-08 18:52:00 +0200 |
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committer | Kalle Valo <kvalo@codeaurora.org> | 2021-02-08 18:52:00 +0200 |
commit | b7e6725df786c424295e740c64de313124ad3608 (patch) | |
tree | 6cd8a33b450f6f8c04beaa276eca78ea660022b7 /drivers/net/wireless/intel/iwlwifi/pcie/trans.c | |
parent | 4331667fa14e6643859d0498b34281185eb8018b (diff) | |
parent | 47ef328c2090cc790c0766094557aedd04ac923f (diff) | |
download | linux-b7e6725df786c424295e740c64de313124ad3608.tar.gz |
Merge tag 'iwlwifi-next-for-kalle-2021-02-05' of git://git.kernel.org/pub/scm/linux/kernel/git/iwlwifi/iwlwifi-next
iwlwifi patches intended for v5.12 * Check FW notification sizes for robustness; * Improvements in the NAPI implementation; * Implement a workaround for CCA-EXT; * Add new FW API support; * Fix a CSA bug; * Implement PHY integration version parsing; * A bit of refactoring; * One more CSA bug fix, this time in the AP side; * Support for new So devices and a bit of reorg; * Per Platform Antenna Gain (PPAG) fixes and improvements; * Improvements in the debug framework; * Some other clean-ups and small fixes. # gpg: Signature made Fri 05 Feb 2021 12:04:21 PM EET using RSA key ID 1A3CC5FA # gpg: Good signature from "Luciano Roth Coelho (Luca) <luca@coelho.fi>" # gpg: aka "Luciano Roth Coelho (Intel) <luciano.coelho@intel.com>"
Diffstat (limited to 'drivers/net/wireless/intel/iwlwifi/pcie/trans.c')
-rw-r--r-- | drivers/net/wireless/intel/iwlwifi/pcie/trans.c | 92 |
1 files changed, 24 insertions, 68 deletions
diff --git a/drivers/net/wireless/intel/iwlwifi/pcie/trans.c b/drivers/net/wireless/intel/iwlwifi/pcie/trans.c index ab93a848a466..16f5757b1260 100644 --- a/drivers/net/wireless/intel/iwlwifi/pcie/trans.c +++ b/drivers/net/wireless/intel/iwlwifi/pcie/trans.c @@ -511,9 +511,9 @@ static int iwl_pcie_nic_init(struct iwl_trans *trans) int ret; /* nic_init */ - spin_lock(&trans_pcie->irq_lock); + spin_lock_bh(&trans_pcie->irq_lock); ret = iwl_pcie_apm_init(trans); - spin_unlock(&trans_pcie->irq_lock); + spin_unlock_bh(&trans_pcie->irq_lock); if (ret) return ret; @@ -3286,16 +3286,29 @@ static struct iwl_trans_dump_data return dump_data; } -#ifdef CONFIG_PM_SLEEP -static int iwl_trans_pcie_suspend(struct iwl_trans *trans) +static void iwl_trans_pci_interrupts(struct iwl_trans *trans, bool enable) { - return 0; + if (enable) + iwl_enable_interrupts(trans); + else + iwl_disable_interrupts(trans); } -static void iwl_trans_pcie_resume(struct iwl_trans *trans) +static void iwl_trans_pcie_sync_nmi(struct iwl_trans *trans) { + u32 inta_addr, sw_err_bit; + struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); + + if (trans_pcie->msix_enabled) { + inta_addr = CSR_MSIX_HW_INT_CAUSES_AD; + sw_err_bit = MSIX_HW_INT_CAUSES_REG_SW_ERR; + } else { + inta_addr = CSR_INT; + sw_err_bit = CSR_INT_BIT_SW_ERR; + } + + iwl_trans_sync_nmi_with_addr(trans, inta_addr, sw_err_bit); } -#endif /* CONFIG_PM_SLEEP */ #define IWL_TRANS_COMMON_OPS \ .op_mode_leave = iwl_trans_pcie_op_mode_leave, \ @@ -3316,25 +3329,17 @@ static void iwl_trans_pcie_resume(struct iwl_trans *trans) .dump_data = iwl_trans_pcie_dump_data, \ .d3_suspend = iwl_trans_pcie_d3_suspend, \ .d3_resume = iwl_trans_pcie_d3_resume, \ - .sync_nmi = iwl_trans_pcie_sync_nmi - -#ifdef CONFIG_PM_SLEEP -#define IWL_TRANS_PM_OPS \ - .suspend = iwl_trans_pcie_suspend, \ - .resume = iwl_trans_pcie_resume, -#else -#define IWL_TRANS_PM_OPS -#endif /* CONFIG_PM_SLEEP */ + .interrupts = iwl_trans_pci_interrupts, \ + .sync_nmi = iwl_trans_pcie_sync_nmi \ static const struct iwl_trans_ops trans_ops_pcie = { IWL_TRANS_COMMON_OPS, - IWL_TRANS_PM_OPS .start_hw = iwl_trans_pcie_start_hw, .fw_alive = iwl_trans_pcie_fw_alive, .start_fw = iwl_trans_pcie_start_fw, .stop_device = iwl_trans_pcie_stop_device, - .send_cmd = iwl_trans_pcie_send_hcmd, + .send_cmd = iwl_pcie_enqueue_hcmd, .tx = iwl_trans_pcie_tx, .reclaim = iwl_txq_reclaim, @@ -3355,13 +3360,12 @@ static const struct iwl_trans_ops trans_ops_pcie = { static const struct iwl_trans_ops trans_ops_pcie_gen2 = { IWL_TRANS_COMMON_OPS, - IWL_TRANS_PM_OPS .start_hw = iwl_trans_pcie_start_hw, .fw_alive = iwl_trans_pcie_gen2_fw_alive, .start_fw = iwl_trans_pcie_gen2_start_fw, .stop_device = iwl_trans_pcie_gen2_stop_device, - .send_cmd = iwl_trans_pcie_gen2_send_hcmd, + .send_cmd = iwl_pcie_gen2_enqueue_hcmd, .tx = iwl_txq_gen2_tx, .reclaim = iwl_txq_reclaim, @@ -3496,9 +3500,6 @@ struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev, snprintf(trans->hw_id_str, sizeof(trans->hw_id_str), "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device); - /* Initialize the wait queue for commands */ - init_waitqueue_head(&trans_pcie->wait_command_queue); - init_waitqueue_head(&trans_pcie->sx_waitq); @@ -3538,48 +3539,3 @@ out_free_trans: iwl_trans_free(trans); return ERR_PTR(ret); } - -void iwl_trans_pcie_sync_nmi(struct iwl_trans *trans) -{ - struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); - unsigned long timeout = jiffies + IWL_TRANS_NMI_TIMEOUT; - bool interrupts_enabled = test_bit(STATUS_INT_ENABLED, &trans->status); - u32 inta_addr, sw_err_bit; - - if (trans_pcie->msix_enabled) { - inta_addr = CSR_MSIX_HW_INT_CAUSES_AD; - sw_err_bit = MSIX_HW_INT_CAUSES_REG_SW_ERR; - } else { - inta_addr = CSR_INT; - sw_err_bit = CSR_INT_BIT_SW_ERR; - } - - /* if the interrupts were already disabled, there is no point in - * calling iwl_disable_interrupts - */ - if (interrupts_enabled) - iwl_disable_interrupts(trans); - - iwl_force_nmi(trans); - while (time_after(timeout, jiffies)) { - u32 inta_hw = iwl_read32(trans, inta_addr); - - /* Error detected by uCode */ - if (inta_hw & sw_err_bit) { - /* Clear causes register */ - iwl_write32(trans, inta_addr, inta_hw & sw_err_bit); - break; - } - - mdelay(1); - } - - /* enable interrupts only if there were already enabled before this - * function to avoid a case were the driver enable interrupts before - * proper configurations were made - */ - if (interrupts_enabled) - iwl_enable_interrupts(trans); - - iwl_trans_fw_error(trans); -} |