diff options
author | françois romieu <romieu@fr.zoreil.com> | 2011-01-03 15:07:42 +0000 |
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committer | David S. Miller <davem@davemloft.net> | 2011-01-04 09:48:32 -0800 |
commit | f0298f8143e89ac4da306e14b9aa1927e93916d0 (patch) | |
tree | 4909a768be104dab18f3e17b41f29b7d0b23e07b /drivers/net/r8169.c | |
parent | bca03d5f32c8ee9b5cfa1d32640a63fded6cb3c0 (diff) | |
download | linux-f0298f8143e89ac4da306e14b9aa1927e93916d0.tar.gz |
r8169: identify different registers.
Documentation (sort of). The location are the same, the values are the same but it is just accidental. Note that the 810x could cope with a smaller value as it does not support jumbo frames. Signed-off-by: Francois Romieu <romieu@fr.zoreil.com> Cc: Hayes <hayeswang@realtek.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/r8169.c')
-rw-r--r-- | drivers/net/r8169.c | 22 |
1 files changed, 14 insertions, 8 deletions
diff --git a/drivers/net/r8169.c b/drivers/net/r8169.c index 312446234509..33c3fbf227f4 100644 --- a/drivers/net/r8169.c +++ b/drivers/net/r8169.c @@ -67,7 +67,6 @@ static const int multicast_filter_limit = 32; #define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */ #define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */ #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */ -#define EarlyTxThld 0x3F /* 0x3F means NO early transmit */ #define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */ #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */ @@ -231,7 +230,14 @@ enum rtl_registers { IntrMitigate = 0xe2, RxDescAddrLow = 0xe4, RxDescAddrHigh = 0xe8, - EarlyTxThres = 0xec, + EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */ + +#define NoEarlyTx 0x3f /* Max value : no early transmit. */ + + MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */ + +#define TxPacketMax (8064 >> 7) + FuncEvent = 0xf0, FuncEventMask = 0xf4, FuncPresetState = 0xf8, @@ -2901,7 +2907,7 @@ static void rtl_hw_start_8169(struct net_device *dev) (tp->mac_version == RTL_GIGA_MAC_VER_04)) RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); - RTL_W8(EarlyTxThres, EarlyTxThld); + RTL_W8(EarlyTxThres, NoEarlyTx); rtl_set_rx_max_size(ioaddr, rx_buf_sz); @@ -3036,7 +3042,7 @@ static void rtl_hw_start_8168bef(void __iomem *ioaddr, struct pci_dev *pdev) { rtl_hw_start_8168bb(ioaddr, pdev); - RTL_W8(EarlyTxThres, EarlyTxThld); + RTL_W8(MaxTxPacketSize, TxPacketMax); RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0)); } @@ -3091,7 +3097,7 @@ static void rtl_hw_start_8168cp_3(void __iomem *ioaddr, struct pci_dev *pdev) /* Magic. */ RTL_W8(DBG_REG, 0x20); - RTL_W8(EarlyTxThres, EarlyTxThld); + RTL_W8(MaxTxPacketSize, TxPacketMax); rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); @@ -3147,7 +3153,7 @@ static void rtl_hw_start_8168d(void __iomem *ioaddr, struct pci_dev *pdev) rtl_disable_clock_request(pdev); - RTL_W8(EarlyTxThres, EarlyTxThld); + RTL_W8(MaxTxPacketSize, TxPacketMax); rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); @@ -3162,7 +3168,7 @@ static void rtl_hw_start_8168(struct net_device *dev) RTL_W8(Cfg9346, Cfg9346_Unlock); - RTL_W8(EarlyTxThres, EarlyTxThld); + RTL_W8(MaxTxPacketSize, TxPacketMax); rtl_set_rx_max_size(ioaddr, rx_buf_sz); @@ -3342,7 +3348,7 @@ static void rtl_hw_start_8101(struct net_device *dev) RTL_W8(Cfg9346, Cfg9346_Unlock); - RTL_W8(EarlyTxThres, EarlyTxThld); + RTL_W8(MaxTxPacketSize, TxPacketMax); rtl_set_rx_max_size(ioaddr, rx_buf_sz); |