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authorAnton Vorontsov <avorontsov@ru.mvista.com>2009-09-09 16:01:30 +0000
committerDavid S. Miller <davem@davemloft.net>2009-09-11 12:54:38 -0700
commit8ff44985c761ad6697a3c97e7b14cf5362ff3801 (patch)
tree3f9903a9573ea74938c8ff66be449e1d0a965dba /drivers/net/phy
parenta4b11649618ef5366ee553f4083449d6bee5d8ec (diff)
downloadlinux-8ff44985c761ad6697a3c97e7b14cf5362ff3801.tar.gz
phy/marvell: Make non-aneg speed/duplex forcing work for 88E1111 PHYs
According to specs, when auto-negotiation is disabled, Marvell PHYs need
a software reset after changing speed/duplex forcing bits. Otherwise,
the modified bits have no effect.

Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/phy')
-rw-r--r--drivers/net/phy/marvell.c21
1 files changed, 20 insertions, 1 deletions
diff --git a/drivers/net/phy/marvell.c b/drivers/net/phy/marvell.c
index dd6f54d1b495..6f69b9ba0df8 100644
--- a/drivers/net/phy/marvell.c
+++ b/drivers/net/phy/marvell.c
@@ -155,8 +155,27 @@ static int marvell_config_aneg(struct phy_device *phydev)
 		return err;
 
 	err = genphy_config_aneg(phydev);
+	if (err < 0)
+		return err;
 
-	return err;
+	if (phydev->autoneg != AUTONEG_ENABLE) {
+		int bmcr;
+
+		/*
+		 * A write to speed/duplex bits (that is performed by
+		 * genphy_config_aneg() call above) must be followed by
+		 * a software reset. Otherwise, the write has no effect.
+		 */
+		bmcr = phy_read(phydev, MII_BMCR);
+		if (bmcr < 0)
+			return bmcr;
+
+		err = phy_write(phydev, MII_BMCR, bmcr | BMCR_RESET);
+		if (err < 0)
+			return err;
+	}
+
+	return 0;
 }
 
 static int m88e1121_config_aneg(struct phy_device *phydev)