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| author | Lubomir Rintel <lkundrak@v3.sk> | 2020-09-26 01:39:14 +0200 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2020-10-13 19:53:36 -0700 |
| commit | 07c565b42a04f38c49c3b09f89917cdf282c4743 (patch) | |
| tree | 140c474d58b213c652cb9d3f0d564d2bbc1c1bd4 /drivers/net/phy | |
| parent | 9123e3a74ec7b934a4a099e98af6a61c2f80bbf5 (diff) | |
| download | linux-07c565b42a04f38c49c3b09f89917cdf282c4743.tar.gz | |
clk: mmp2: Fix the display clock divider base
The LCD clock dividers are apparently based on one. No datasheet, determined empirically, but seems to be confirmed by line 19 of lcd.fth in OLPC laptop's Open Firmware [1]: h# 00000700 value pmua-disp-clk-sel \ PLL1 / 7 -> 113.86 MHz [1] https://raw.githubusercontent.com/quozl/openfirmware/65a08a73b2cac/cpu/arm/olpc/lcd.fth Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Link: https://lore.kernel.org/r/20200925233914.227786-1-lkundrak@v3.sk Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'drivers/net/phy')
0 files changed, 0 insertions, 0 deletions