diff options
| author | Eilon Greenstein <eilong@broadcom.com> | 2009-02-12 08:37:16 +0000 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2009-02-15 23:31:42 -0800 |
| commit | 052a38e096dece43e38a19a896ae7ad019415bc1 (patch) | |
| tree | 127b34c6948872a535bfc13e102d852515c44679 /drivers/net/bnx2x_link.c | |
| parent | c2c8b03e200bdda3ba23d27f5c33bac784dced01 (diff) | |
| download | linux-052a38e096dece43e38a19a896ae7ad019415bc1.tar.gz | |
bnx2x: Using registers name
Signed-off-by: Eilon Greenstein <eilong@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/bnx2x_link.c')
| -rw-r--r-- | drivers/net/bnx2x_link.c | 71 |
1 files changed, 36 insertions, 35 deletions
diff --git a/drivers/net/bnx2x_link.c b/drivers/net/bnx2x_link.c index 4a594b84ba20..39db995c6985 100644 --- a/drivers/net/bnx2x_link.c +++ b/drivers/net/bnx2x_link.c @@ -2094,7 +2094,7 @@ static u8 bnx2x_8073_is_snr_needed(struct link_params *params) PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073, ext_phy_addr, MDIO_PMA_DEVAD, - 0xc801, &val); + MDIO_PMA_REG_8073_CHIP_REV, &val); if (val != 1) { /* No need to workaround in 8073 A1 */ @@ -2126,7 +2126,7 @@ static u8 bnx2x_bcm8073_xaui_wa(struct link_params *params) PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073, ext_phy_addr, MDIO_PMA_DEVAD, - 0xc801, &val); + MDIO_PMA_REG_8073_CHIP_REV, &val); if (val > 0) { /* No need to workaround in 8073 A1 */ @@ -2142,7 +2142,8 @@ static u8 bnx2x_bcm8073_xaui_wa(struct link_params *params) PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073, ext_phy_addr, MDIO_PMA_DEVAD, - 0xc820, &val); + MDIO_PMA_REG_8073_SPEED_LINK_STATUS, + &val); /* If bit [14] = 0 or bit [13] = 0, continue on with system initialization (XAUI work-around not required, as these bits indicate 2.5G or 1G link up). */ @@ -2160,7 +2161,7 @@ static u8 bnx2x_bcm8073_xaui_wa(struct link_params *params) PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073, ext_phy_addr, MDIO_PMA_DEVAD, - 0xc841, &val); + MDIO_PMA_REG_8073_XAUI_WA, &val); if (val & (1<<15)) { DP(NETIF_MSG_LINK, "XAUI workaround has completed\n"); @@ -2758,7 +2759,7 @@ static void bnx2x_bcm8073_set_xaui_low_power_mode(struct link_params *params) PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073, ext_phy_addr, MDIO_PMA_DEVAD, - 0xc801, &val); + MDIO_PMA_REG_8073_CHIP_REV, &val); if (val == 0) { /* Mustn't set low power mode in 8073 A0 */ @@ -3283,7 +3284,7 @@ static u8 bnx2x_ext_phy_init(struct link_params *params, struct link_vars *vars) ext_phy_type, ext_phy_addr, MDIO_PMA_DEVAD, - 0xca13, + MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1); bnx2x_cl45_read(bp, params->port, @@ -3350,7 +3351,7 @@ static u8 bnx2x_ext_phy_init(struct link_params *params, struct link_vars *vars) ext_phy_type, ext_phy_addr, MDIO_AN_DEVAD, - 0x8329, &tmp1); + MDIO_AN_REG_8073_2_5G, &tmp1); if (((params->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G) && @@ -3364,7 +3365,7 @@ static u8 bnx2x_ext_phy_init(struct link_params *params, struct link_vars *vars) PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073, ext_phy_addr, MDIO_PMA_DEVAD, - 0xc801, &phy_ver); + MDIO_PMA_REG_8073_CHIP_REV, &phy_ver); DP(NETIF_MSG_LINK, "Add 2.5G\n"); if (phy_ver > 0) tmp1 |= 1; @@ -3379,7 +3380,7 @@ static u8 bnx2x_ext_phy_init(struct link_params *params, struct link_vars *vars) ext_phy_type, ext_phy_addr, MDIO_AN_DEVAD, - 0x8329, tmp1); + MDIO_AN_REG_8073_2_5G, tmp1); } /* Add support for CL37 (passive mode) II */ @@ -3737,7 +3738,7 @@ static u8 bnx2x_ext_phy_is_link_up(struct link_params *params, ext_phy_type, ext_phy_addr, MDIO_PMA_DEVAD, - 0xca13, + MDIO_PMA_REG_M8051_MSGOUT_REG, &val1); /* Check the LASI */ @@ -3782,17 +3783,17 @@ static u8 bnx2x_ext_phy_is_link_up(struct link_params *params, } } bnx2x_cl45_read(bp, params->port, - ext_phy_type, - ext_phy_addr, - MDIO_AN_DEVAD, - 0x8304, - &an1000_status); + ext_phy_type, + ext_phy_addr, + MDIO_AN_DEVAD, + MDIO_AN_REG_LINK_STATUS, + &an1000_status); bnx2x_cl45_read(bp, params->port, - ext_phy_type, - ext_phy_addr, - MDIO_AN_DEVAD, - 0x8304, - &an1000_status); + ext_phy_type, + ext_phy_addr, + MDIO_AN_DEVAD, + MDIO_AN_REG_LINK_STATUS, + &an1000_status); /* Check the link status on 1.1.2 */ bnx2x_cl45_read(bp, params->port, @@ -3837,11 +3838,11 @@ static u8 bnx2x_ext_phy_is_link_up(struct link_params *params, } bnx2x_cl45_read(bp, params->port, - ext_phy_type, - ext_phy_addr, - MDIO_PMA_DEVAD, - 0xc820, - &link_status); + ext_phy_type, + ext_phy_addr, + MDIO_PMA_DEVAD, + MDIO_PMA_REG_8073_SPEED_LINK_STATUS, + &link_status); /* Bits 0..2 --> speed detected, bits 13..15--> link is down */ @@ -3875,17 +3876,17 @@ static u8 bnx2x_ext_phy_is_link_up(struct link_params *params, } else { /* See if 1G link is up for the 8072 */ bnx2x_cl45_read(bp, params->port, - ext_phy_type, - ext_phy_addr, - MDIO_AN_DEVAD, - 0x8304, - &an1000_status); + ext_phy_type, + ext_phy_addr, + MDIO_AN_DEVAD, + MDIO_AN_REG_LINK_STATUS, + &an1000_status); bnx2x_cl45_read(bp, params->port, - ext_phy_type, - ext_phy_addr, - MDIO_AN_DEVAD, - 0x8304, - &an1000_status); + ext_phy_type, + ext_phy_addr, + MDIO_AN_DEVAD, + MDIO_AN_REG_LINK_STATUS, + &an1000_status); if (an1000_status & (1<<1)) { ext_phy_link_up = 1; vars->line_speed = SPEED_1000; |