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| author | Wolfram Sang <wsa+renesas@sang-engineering.com> | 2022-10-06 21:04:50 +0200 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2022-12-31 13:33:04 +0100 |
| commit | 63604e820f1525975e6a9f017a6fb7db6d703e1e (patch) | |
| tree | f76bde9ee07c40cea255d2ca747174973bb2b9cb /drivers/mmc/host/renesas_sdhi.h | |
| parent | c490e8c3d50029633148827cb215d4f30718a98c (diff) | |
| download | linux-63604e820f1525975e6a9f017a6fb7db6d703e1e.tar.gz | |
mmc: renesas_sdhi: add quirk for broken register layout
[ Upstream commit ec9e80ae1719de541c719116a1ca0a0c70e9240c ] Some early Gen3 SoCs have the DTRANEND1 bit at a different location than all later SoCs. Because we need the bit soon, add a quirk so we know which bit to use. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Tested-by: Duy Nguyen <duy.nguyen.rh@renesas.com> Tested-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/20221006190452.5316-5-wsa+renesas@sang-engineering.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Sasha Levin <sashal@kernel.org>
Diffstat (limited to 'drivers/mmc/host/renesas_sdhi.h')
| -rw-r--r-- | drivers/mmc/host/renesas_sdhi.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/mmc/host/renesas_sdhi.h b/drivers/mmc/host/renesas_sdhi.h index c4abfee1ebae..e4c490729c98 100644 --- a/drivers/mmc/host/renesas_sdhi.h +++ b/drivers/mmc/host/renesas_sdhi.h @@ -44,6 +44,7 @@ struct renesas_sdhi_quirks { bool fixed_addr_mode; bool dma_one_rx_only; bool manual_tap_correction; + bool old_info1_layout; u32 hs400_bad_taps; const u8 (*hs400_calib_table)[SDHI_CALIB_TABLE_MAX]; }; |