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| author | Serge Semin <Sergey.Semin@baikalelectronics.ru> | 2020-05-26 15:59:28 +0300 |
|---|---|---|
| committer | Arnd Bergmann <arnd@arndb.de> | 2020-05-28 14:17:41 +0200 |
| commit | 83ca8b3e8f213f49cc68b5c1fbcf88ebb24671eb (patch) | |
| tree | bd2e9caa7cf5294ac4906ac560abdddda5cd3dc3 /drivers/memory/Kconfig | |
| parent | 8f93662d8324940e8925a0e492c587dbcf7c7fee (diff) | |
| download | linux-83ca8b3e8f213f49cc68b5c1fbcf88ebb24671eb.tar.gz | |
memory: Add Baikal-T1 L2-cache Control Block driver
Baikal-T1 SoC provides a way to tune the MIPS P5600 CM2 L2-cache performance up. It can be done by changing the L2-RAM Data/Tag/WS latencies in a dedicated register exposed by the system controller. The driver added by this commit provides a dts properties-based and sysfs-based interface for it. The device DT node is supposed to be a child of Baikal-T1 System Controller node. Link: https://lore.kernel.org/r/20200526125928.17096-7-Sergey.Semin@baikalelectronics.ru Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru> Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru> Cc: Paul Burton <paulburton@kernel.org> Cc: Olof Johansson <olof@lixom.net> Cc: Rob Herring <robh+dt@kernel.org> Cc: linux-mips@vger.kernel.org Cc: soc@kernel.org Cc: devicetree@vger.kernel.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'drivers/memory/Kconfig')
| -rw-r--r-- | drivers/memory/Kconfig | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/drivers/memory/Kconfig b/drivers/memory/Kconfig index 9bddca292330..04368ee2a809 100644 --- a/drivers/memory/Kconfig +++ b/drivers/memory/Kconfig @@ -46,6 +46,17 @@ config ATMEL_EBI tree is used. This bus supports NANDs, external ethernet controller, SRAMs, ATA devices, etc. +config BT1_L2_CTL + bool "Baikal-T1 CM2 L2-RAM Cache Control Block" + depends on MIPS_BAIKAL_T1 || COMPILE_TEST + select MFD_SYSCON + help + Baikal-T1 CPU is based on the MIPS P5600 Warrior IP-core. The CPU + resides Coherency Manager v2 with embedded 1MB L2-cache. It's + possible to tune the L2 cache performance up by setting the data, + tags and way-select latencies of RAM access. This driver provides a + dt properties-based and sysfs interface for it. + config TI_AEMIF tristate "Texas Instruments AEMIF driver" depends on (ARCH_DAVINCI || ARCH_KEYSTONE) && OF |