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| author | Sakari Ailus <sakari.ailus@linux.intel.com> | 2020-06-17 10:39:34 +0200 |
|---|---|---|
| committer | Mauro Carvalho Chehab <mchehab+huawei@kernel.org> | 2020-12-07 15:48:12 +0100 |
| commit | 4f3d9e6eda9d73c43003701ab837868106125d96 (patch) | |
| tree | 6da239784eed1da94cc0640c77da5e4fbd0131c7 /drivers/media/i2c/ccs-pll.h | |
| parent | 925e3e49730346a39ec718f30f0965c3785facbb (diff) | |
| download | linux-4f3d9e6eda9d73c43003701ab837868106125d96.tar.gz | |
media: ccs-pll: Use the BIT macro
Use the BIT macro for setting individual bits. Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
Diffstat (limited to 'drivers/media/i2c/ccs-pll.h')
| -rw-r--r-- | drivers/media/i2c/ccs-pll.h | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/drivers/media/i2c/ccs-pll.h b/drivers/media/i2c/ccs-pll.h index 1b8d36068c7d..3ad4e6524ab6 100644 --- a/drivers/media/i2c/ccs-pll.h +++ b/drivers/media/i2c/ccs-pll.h @@ -12,13 +12,16 @@ #ifndef CCS_PLL_H #define CCS_PLL_H +#include <linux/bits.h> + /* CSI-2 or CCP-2 */ #define CCS_PLL_BUS_TYPE_CSI2_DPHY 0x00 #define CCS_PLL_BUS_TYPE_CSI2_CPHY 0x01 +/* Old SMIA and implementation specific flags */ /* op pix clock is for all lanes in total normally */ -#define CCS_PLL_FLAG_OP_PIX_CLOCK_PER_LANE (1 << 0) -#define CCS_PLL_FLAG_NO_OP_CLOCKS (1 << 1) +#define CCS_PLL_FLAG_OP_PIX_CLOCK_PER_LANE BIT(0) +#define CCS_PLL_FLAG_NO_OP_CLOCKS BIT(1) /** * struct ccs_pll_branch_fr - CCS PLL configuration (front) |