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| author | Anup Patel <anup@brainfault.org> | 2019-02-12 18:22:43 +0530 |
|---|---|---|
| committer | Marc Zyngier <marc.zyngier@arm.com> | 2019-02-21 10:32:05 +0000 |
| commit | 86c7cbf1e8d1d4f4f60e229fdc2a5b21c09c29a3 (patch) | |
| tree | a7d4426654e3b0b8b6f0930b668beec8a3d1042b /drivers/irqchip/irq-stm32-exti.c | |
| parent | fc03acaeab358c008a194b78daa10e78401376a8 (diff) | |
| download | linux-86c7cbf1e8d1d4f4f60e229fdc2a5b21c09c29a3.tar.gz | |
irqchip/sifive-plic: Pre-compute context hart base and enable base
This patch does following optimizations: 1. Pre-compute hart base for each context handler 2. Pre-compute enable base for each context handler 3. Have enable lock for each context handler instead of global plic_toggle_lock Signed-off-by: Anup Patel <anup@brainfault.org> Reviewed-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Diffstat (limited to 'drivers/irqchip/irq-stm32-exti.c')
0 files changed, 0 insertions, 0 deletions