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| author | Jonathan Cameron <Jonathan.Cameron@huawei.com> | 2022-05-08 18:56:20 +0100 |
|---|---|---|
| committer | Jonathan Cameron <Jonathan.Cameron@huawei.com> | 2022-06-14 11:53:15 +0100 |
| commit | 00eb2b8a077062557772234019ecd6045b8b6298 (patch) | |
| tree | c88748c6f0e4dc0b7bcc6a800ffb83772047583c /drivers/iio/addac | |
| parent | 62fa19bf484bfeb52c56b7c6d6a6b1222c597f9c (diff) | |
| download | linux-00eb2b8a077062557772234019ecd6045b8b6298.tar.gz | |
iio: addac: ad74413r: Fix alignment for DMA safety
____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1. Switch to the updated
IIO_DMA_MINALIGN definition.
Update the comment to include 'may'.
Fixes: fea251b6a5db ("iio: addac: add AD74413R driver")
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Cc: Cosmin Tanislav <cosmin.tanislav@analog.com>
Acked-by: Nuno Sá <nuno.sa@analog.com>
Link: https://lore.kernel.org/r/20220508175712.647246-41-jic23@kernel.org
Diffstat (limited to 'drivers/iio/addac')
| -rw-r--r-- | drivers/iio/addac/ad74413r.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/iio/addac/ad74413r.c b/drivers/iio/addac/ad74413r.c index bc5a58f7f774..899bcd83f40b 100644 --- a/drivers/iio/addac/ad74413r.c +++ b/drivers/iio/addac/ad74413r.c @@ -77,13 +77,13 @@ struct ad74413r_state { struct spi_transfer adc_samples_xfer[AD74413R_CHANNEL_MAX + 1]; /* - * DMA (thus cache coherency maintenance) requires the + * DMA (thus cache coherency maintenance) may require the * transfer buffers to live in their own cache lines. */ struct { u8 rx_buf[AD74413R_FRAME_SIZE * AD74413R_CHANNEL_MAX]; s64 timestamp; - } adc_samples_buf ____cacheline_aligned; + } adc_samples_buf __aligned(IIO_DMA_MINALIGN); u8 adc_samples_tx_buf[AD74413R_FRAME_SIZE * AD74413R_CHANNEL_MAX]; u8 reg_tx_buf[AD74413R_FRAME_SIZE]; |