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| author | Alexander Shishkin <alexander.shishkin@linux.intel.com> | 2019-07-05 17:14:25 +0300 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2019-07-25 13:03:19 +0200 |
| commit | 092f47c383adbff4d873dcb7f0887954bd407a08 (patch) | |
| tree | 389a6d92b3b0d4e18222ed530172df90bd79e456 /drivers/hwtracing | |
| parent | ed5207afc580937cd6cc671357fe1119f1b5b0f5 (diff) | |
| download | linux-092f47c383adbff4d873dcb7f0887954bd407a08.tar.gz | |
intel_th: msu: Preserve pre-existing buffer configuration
The MSU configuration registers may contain buffer address/size set by the BIOS or an external hardware debugger, which may want to take over tracing from the driver when the driver is not actively tracing. Preserve these settings when not actively tracing. Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20190705141425.19894-6-alexander.shishkin@linux.intel.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'drivers/hwtracing')
| -rw-r--r-- | drivers/hwtracing/intel_th/msu.c | 9 |
1 files changed, 7 insertions, 2 deletions
diff --git a/drivers/hwtracing/intel_th/msu.c b/drivers/hwtracing/intel_th/msu.c index b200d9d1c7a0..fc9f15f36ad4 100644 --- a/drivers/hwtracing/intel_th/msu.c +++ b/drivers/hwtracing/intel_th/msu.c @@ -143,6 +143,8 @@ struct msc { unsigned int single_wrap : 1; void *base; dma_addr_t base_addr; + u32 orig_addr; + u32 orig_sz; /* <0: no buffer, 0: no users, >0: active users */ atomic_t user_count; @@ -767,6 +769,9 @@ static int msc_configure(struct msc *msc) msc_buffer_clear_hw_header(msc); } + msc->orig_addr = ioread32(msc->reg_base + REG_MSU_MSC0BAR); + msc->orig_sz = ioread32(msc->reg_base + REG_MSU_MSC0SIZE); + reg = msc->base_addr >> PAGE_SHIFT; iowrite32(reg, msc->reg_base + REG_MSU_MSC0BAR); @@ -841,8 +846,8 @@ static void msc_disable(struct msc *msc) msc->enabled = 0; - iowrite32(0, msc->reg_base + REG_MSU_MSC0BAR); - iowrite32(0, msc->reg_base + REG_MSU_MSC0SIZE); + iowrite32(msc->orig_addr, msc->reg_base + REG_MSU_MSC0BAR); + iowrite32(msc->orig_sz, msc->reg_base + REG_MSU_MSC0SIZE); dev_dbg(msc_dev(msc), "MSCnNWSA: %08x\n", ioread32(msc->reg_base + REG_MSU_MSC0NWSA)); |