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author | Kever Yang <kever.yang@rock-chips.com> | 2014-11-13 16:11:49 +0800 |
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committer | Heiko Stuebner <heiko@sntech.de> | 2014-11-16 00:40:19 +0100 |
commit | 29e94468516cdf191ec839ee39f79e011817276d (patch) | |
tree | c262b61f1785452a305e66993c7a0cfc5c99fd59 /drivers/hid/hid-chicony.c | |
parent | 0132234160ae46d8bd4677e37adb0b4366e05b1e (diff) | |
download | linux-29e94468516cdf191ec839ee39f79e011817276d.tar.gz |
clk: rockchip: fix clock select order for rk3288 usbphy480m_src
According to rk3288 trm, the mux selector locate at bit[12:11] of CRU_CLKSEL13_CON shows: 2'b00: select HOST0 USB pll clock (clk_otgphy1) 2'b01: select HOST1 USB pll clock (clk_otgphy2) 2'b10: select OTG USB pll clock (clk_otgphy0) The clock map is in Fig. 3-4 CRU Clock Architecture Diagram 3 - clk_otgphy0 -> USB PHY OTG - clk_otgphy1 -> USB PHY host0 - clk_otgphy2 -> USB PHY host1 Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Diffstat (limited to 'drivers/hid/hid-chicony.c')
0 files changed, 0 insertions, 0 deletions