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| author | Russell King <rmk+kernel@arm.linux.org.uk> | 2013-08-14 21:43:27 +0200 |
|---|---|---|
| committer | Dave Airlie <airlied@redhat.com> | 2013-08-19 09:10:07 +1000 |
| commit | bcb2481df01a9aee7a09b20d43194011edd35754 (patch) | |
| tree | 38a13de9603de6b37f5ee84a53ef08786c21c423 /drivers/gpu | |
| parent | 063b472fbb44ac562797a630ac3516720f588140 (diff) | |
| download | linux-bcb2481df01a9aee7a09b20d43194011edd35754.tar.gz | |
drm/i2c: tda998x: ensure VIP output mux is properly set
When switching between various drivers for this device, it's possible that some critical registers are left containing values which affect the device operation. One such case encountered is the VIP output mux register. This defaults to 0x24 on powerup, but other drivers may set this to 0x12. This results in incorrect colours. Fix this by ensuring that the register is always set to the power on default setting. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Tested-by: Darren Etheridge <detheridge@ti.com> Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Tested-by: Russell King <rmk_kernel@arm.linux.org.uk> Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers/gpu')
| -rw-r--r-- | drivers/gpu/drm/i2c/tda998x_drv.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i2c/tda998x_drv.c b/drivers/gpu/drm/i2c/tda998x_drv.c index d71c408916e4..cb9b13ad1ae6 100644 --- a/drivers/gpu/drm/i2c/tda998x_drv.c +++ b/drivers/gpu/drm/i2c/tda998x_drv.c @@ -110,6 +110,7 @@ struct tda998x_priv { #define REG_VIP_CNTRL_5 REG(0x00, 0x25) /* write */ # define VIP_CNTRL_5_CKCASE (1 << 0) # define VIP_CNTRL_5_SP_CNT(x) (((x) & 3) << 1) +#define REG_MUX_VP_VIP_OUT REG(0x00, 0x27) /* read/write */ #define REG_MAT_CONTRL REG(0x00, 0x80) /* write */ # define MAT_CONTRL_MAT_SC(x) (((x) & 3) << 0) # define MAT_CONTRL_MAT_BP (1 << 2) @@ -415,6 +416,9 @@ tda998x_reset(struct drm_encoder *encoder) reg_write(encoder, REG_PLL_SCGR1, 0x5b); reg_write(encoder, REG_PLL_SCGR2, 0x00); reg_write(encoder, REG_PLL_SCG2, 0x10); + + /* Write the default value MUX register */ + reg_write(encoder, REG_MUX_VP_VIP_OUT, 0x24); } /* DRM encoder functions */ |