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| author | Rafał Miłecki <zajec5@gmail.com> | 2014-05-16 11:10:29 +0200 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2014-06-02 10:25:04 -0400 |
| commit | 2e93cac90c4b063c8732deb727a192dea1119640 (patch) | |
| tree | d693edcb5a2ae13673e194f2985bf8b417f1d2d3 /drivers/gpu/drm/radeon/r600d.h | |
| parent | 8f33a156c2adeddb5b5755b277b2c0b68da56ae2 (diff) | |
| download | linux-2e93cac90c4b063c8732deb727a192dea1119640.tar.gz | |
drm/radeon/hdmi: DCE3: clean ACR control
What initially seemed to be a typo in fglrx (using register 0x740c instead of 0x74dc) appeared to be a correct behavior. DCE3 has ACR and CRC registers swapped which explains why we needed WREG32(HDMI0_AUDIO_CRC_CONTROL + offset, 0x1000); This has been tested for possible regressions on DCE3 HD3470 (RV620). Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/r600d.h')
| -rw-r--r-- | drivers/gpu/drm/radeon/r600d.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/gpu/drm/radeon/r600d.h b/drivers/gpu/drm/radeon/r600d.h index 37455f65107f..10380c5322a3 100644 --- a/drivers/gpu/drm/radeon/r600d.h +++ b/drivers/gpu/drm/radeon/r600d.h @@ -1038,6 +1038,7 @@ # define HDMI0_AZ_FORMAT_WTRIG_ACK (1 << 29) #define HDMI0_AUDIO_CRC_CONTROL 0x740c # define HDMI0_AUDIO_CRC_EN (1 << 0) +#define DCE3_HDMI0_ACR_PACKET_CONTROL 0x740c #define HDMI0_VBI_PACKET_CONTROL 0x7410 # define HDMI0_NULL_SEND (1 << 0) # define HDMI0_GC_SEND (1 << 4) @@ -1166,6 +1167,7 @@ # define HDMI0_ACR_48 3 # define HDMI0_ACR_SOURCE (1 << 8) /* 0 - hw; 1 - cts value */ # define HDMI0_ACR_AUTO_SEND (1 << 12) +#define DCE3_HDMI0_AUDIO_CRC_CONTROL 0x74dc #define HDMI0_RAMP_CONTROL0 0x74e0 # define HDMI0_RAMP_MAX_COUNT(x) (((x) & 0xffffff) << 0) #define HDMI0_RAMP_CONTROL1 0x74e4 |