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| author | Paulo Zanoni <paulo.r.zanoni@intel.com> | 2013-01-29 16:35:18 -0200 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2013-01-31 11:50:10 +0100 |
| commit | 10aa17c86f0de1fd902f7b8ee487a3682d7401df (patch) | |
| tree | d2709feff4e1b2b7557c710de788c5b3cce3841e /drivers/gpu/drm/i915 | |
| parent | d5f21e4072645d0174ed4cc7197e0e30f84f96a2 (diff) | |
| download | linux-10aa17c86f0de1fd902f7b8ee487a3682d7401df.tar.gz | |
drm/i915: don't send DP "idle" pattern before "normal" on HSW PORT_A
The DP_TP_STATUS register for PORT_A doesn't exist. Our documentation will be fixed soon, so the code does not match it for now. This solves "Timed out waiting for DP idle patterns" and "unclaimed register" messages on eDP. V1: Was called "drm/i915: don't read DP_TP_STATUS(PORT_A)" V2: Was called "drm/i915: don't send DP idle pattern before normal pattern on HSW" V3: Only change the code that touches PORT_A. Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_dp.c | 16 |
1 files changed, 10 insertions, 6 deletions
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 51fd79758368..1b76b04787c7 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -1785,14 +1785,18 @@ intel_dp_set_link_train(struct intel_dp *intel_dp, temp &= ~DP_TP_CTL_LINK_TRAIN_MASK; switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { case DP_TRAINING_PATTERN_DISABLE: - temp |= DP_TP_CTL_LINK_TRAIN_IDLE; - I915_WRITE(DP_TP_CTL(port), temp); - if (wait_for((I915_READ(DP_TP_STATUS(port)) & - DP_TP_STATUS_IDLE_DONE), 1)) - DRM_ERROR("Timed out waiting for DP idle patterns\n"); + if (port != PORT_A) { + temp |= DP_TP_CTL_LINK_TRAIN_IDLE; + I915_WRITE(DP_TP_CTL(port), temp); + + if (wait_for((I915_READ(DP_TP_STATUS(port)) & + DP_TP_STATUS_IDLE_DONE), 1)) + DRM_ERROR("Timed out waiting for DP idle patterns\n"); + + temp &= ~DP_TP_CTL_LINK_TRAIN_MASK; + } - temp &= ~DP_TP_CTL_LINK_TRAIN_MASK; temp |= DP_TP_CTL_LINK_TRAIN_NORMAL; break; |