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author | Mika Kuoppala <mika.kuoppala@linux.intel.com> | 2016-06-07 17:19:13 +0300 |
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committer | Mika Kuoppala <mika.kuoppala@intel.com> | 2016-06-08 16:25:56 +0300 |
commit | 590e8ff04bc0182dce97228e5e352d6413d80456 (patch) | |
tree | 286494aa30688c00d76244a64621319126bca820 /drivers/gpu/drm/i915/intel_pm.c | |
parent | 954337aa96a31f6d4baf1e40ac219fbb1b1d92f4 (diff) | |
download | linux-590e8ff04bc0182dce97228e5e352d6413d80456.tar.gz |
drm/i915/gen9: Add WaEnableChickenDCPR
Workaround for display underrun issues with Y & Yf Tiling. Set this on all gen9 as stated by bspec. v2: proper workaround name References: HSD#2136383, BSID#857 Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com> Reviewed-by: Matthew Auld <matthew.auld@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1465309159-30531-22-git-send-email-mika.kuoppala@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/intel_pm.c')
-rw-r--r-- | drivers/gpu/drm/i915/intel_pm.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index d8eb23f0ccbf..d766d1a562df 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -65,6 +65,10 @@ static void gen9_init_clock_gating(struct drm_device *dev) I915_WRITE(GEN8_CONFIG0, I915_READ(GEN8_CONFIG0) | GEN9_DEFAULT_FIXES); + + /* WaEnableChickenDCPR:skl,bxt,kbl */ + I915_WRITE(GEN8_CHICKEN_DCPR_1, + I915_READ(GEN8_CHICKEN_DCPR_1) | MASK_WAKEMEM); } static void bxt_init_clock_gating(struct drm_device *dev) |