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| author | Imre Deak <imre.deak@intel.com> | 2016-05-03 15:54:20 +0300 |
|---|---|---|
| committer | Imre Deak <imre.deak@intel.com> | 2016-05-03 16:49:15 +0300 |
| commit | 36579cb63b87b7a4406b9b19c8ff376ca701083b (patch) | |
| tree | 08a5555290f7b17085f9d3ae959197b642208e13 /drivers/gpu/drm/i915/intel_pm.c | |
| parent | 48e5d68d28f00c0cadac5a830980ff3222781abb (diff) | |
| download | linux-36579cb63b87b7a4406b9b19c8ff376ca701083b.tar.gz | |
drm/i915: Clean up L3 SQC register field definitions
No need for hard-coding the register value, the corresponding fields are defined properly in BSpec. No functional change. v2: - Rebased on BXT L3 SQC tuning patch merged meanwhile. CC: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> (v1) Link: http://patchwork.freedesktop.org/patch/msgid/1462280061-1457-3-git-send-email-imre.deak@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/intel_pm.c')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_pm.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 227cd2d395a9..6a48f40a00b9 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -6737,7 +6737,8 @@ static void broadwell_init_clock_gating(struct drm_device *dev) */ misccpctl = I915_READ(GEN7_MISCCPCTL); I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE); - I915_WRITE(GEN8_L3SQCREG1, BDW_WA_L3SQCREG1_DEFAULT); + I915_WRITE(GEN8_L3SQCREG1, L3_GENERAL_PRIO_CREDITS(30) | + L3_HIGH_PRIO_CREDITS(2)); /* * Wait at least 100 clocks before re-enabling clock gating. See * the definition of L3SQCREG1 in BSpec. |