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| author | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2019-06-04 23:09:33 +0300 |
|---|---|---|
| committer | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2019-06-12 14:49:47 +0300 |
| commit | 86761789b38a90ee56d455b81d534ac65e8a2b8b (patch) | |
| tree | 3d92e733f5ec6a45fce7a7be87c69bb51dd066b7 /drivers/gpu/drm/i915/i915_reg.h | |
| parent | d1707a96b11787c7b9ca11fd93d235d6eb6ccbf1 (diff) | |
| download | linux-86761789b38a90ee56d455b81d534ac65e8a2b8b.tar.gz | |
drm/i915: Improve WRPLL reference clock readout on HSW/BDW
On non-ULT HSW the "special" WRPLL reference clock select actually means non-SSC. Take that into account when reading out the WRPLL state. Also the non-SSC reference may be either 24MHz or 135MHz, which we can read out from FUSE_STRAP3. The BDW docs actually say: "also indicates whether the CPU and PCH are in a single package or separate packages", so it may be that this is not actually required and we could just assume 135 MHz (just like the code already did). But it doesn't really hurt to read this out as the HSW docs aren't quite so clear. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190604200933.29417-5-ville.syrjala@linux.intel.com Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_reg.h')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 665dfc177528..d0c262367f09 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -7514,6 +7514,9 @@ enum { #define ILK_DESKTOP (1 << 23) #define HSW_CPU_SSC_ENABLE (1 << 21) +#define FUSE_STRAP3 _MMIO(0x42020) +#define HSW_REF_CLK_SELECT (1 << 1) + #define ILK_DSPCLK_GATE_D _MMIO(0x42020) #define ILK_VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) #define ILK_DPFCUNIT_CLOCK_GATE_DISABLE (1 << 9) |