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| author | Linus Torvalds <torvalds@linux-foundation.org> | 2017-09-07 14:37:25 -0700 |
|---|---|---|
| committer | Linus Torvalds <torvalds@linux-foundation.org> | 2017-09-07 14:37:25 -0700 |
| commit | 7d955656121f547ff9a708ed7ee4c86a08bf628a (patch) | |
| tree | 479c63f5cccfb460793ada8cb2bcb7246f96f238 /drivers/gpu/drm/i915/i915_gem_gtt.c | |
| parent | 5f9cc57036165bbd96f3a432fd2569c812503a92 (diff) | |
| parent | 426ca2cb69cda59f32c251d1f3e111aee8c42814 (diff) | |
| download | linux-7d955656121f547ff9a708ed7ee4c86a08bf628a.tar.gz | |
Merge tag 'drm-intel-next-fixes-2017-09-07' of git://anongit.freedesktop.org/git/drm-intel
Pull i916 drm fixes from Rodrigo Vivi: "Since Dave is on paternity leave we are sending drm/i915 fixes for v4.14-rc1 directly to you as he had asked us to do. The most critical ones are the GPU reset fix for gen2-4 and GVT fix for a regression that is blocking gvt init to work on your tree. The rest is general fixes for patches coming from drm-next" Acked-by: Dave Airlie <airlied@redhat.com> * tag 'drm-intel-next-fixes-2017-09-07' of git://anongit.freedesktop.org/git/drm-intel: drm/i915: Re-enable GTT following a device reset drm/i915: Annotate user relocs with __user drm/i915: Silence sparse by using gfp_t drm/i915: Add __rcu to radix tree slot pointer drm/i915: Fix the missing PPAT cache attributes on CNL drm/i915/gvt: Remove one duplicated MMIO drm/i915: Fix enum pipe vs. enum transcoder for the PCH transcoder drm/i915: Make i2c lock ops static drm/i915: Make i9xx_load_ycbcr_conversion_matrix() static drm/i915/edp: Increase T12 panel delay to 900 ms to fix DP AUX CH timeouts drm/i915: Ignore duplicate VMA stored within the per-object handle LUT drm/i915: Skip fence alignemnt check for the CCS plane drm/i915: Treat fb->offsets[] as a raw byte offset instead of a linear offset drm/i915: Always wake the device to flush the GTT drm/i915: Recreate vmapping even when the object is pinned drm/i915: Quietly cancel FBC activation if CRTC is turned off before worker
Diffstat (limited to 'drivers/gpu/drm/i915/i915_gem_gtt.c')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_gem_gtt.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c index 6c6b8e8592aa..0d5a988b3867 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.c +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c @@ -2754,10 +2754,10 @@ static void cnl_setup_private_ppat(struct drm_i915_private *dev_priv) I915_WRITE(GEN10_PAT_INDEX(1), GEN8_PPAT_WC | GEN8_PPAT_LLCELLC); I915_WRITE(GEN10_PAT_INDEX(2), GEN8_PPAT_WT | GEN8_PPAT_LLCELLC); I915_WRITE(GEN10_PAT_INDEX(3), GEN8_PPAT_UC); - I915_WRITE(GEN10_PAT_INDEX(4), GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0)); - I915_WRITE(GEN10_PAT_INDEX(5), GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(1)); - I915_WRITE(GEN10_PAT_INDEX(6), GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2)); - I915_WRITE(GEN10_PAT_INDEX(7), GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3)); + I915_WRITE(GEN10_PAT_INDEX(4), GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0)); + I915_WRITE(GEN10_PAT_INDEX(5), GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(1)); + I915_WRITE(GEN10_PAT_INDEX(6), GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2)); + I915_WRITE(GEN10_PAT_INDEX(7), GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3)); } /* The GGTT and PPGTT need a private PPAT setup in order to handle cacheability |