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| author | Geert Uytterhoeven <geert+renesas@glider.be> | 2014-06-20 14:37:38 +0200 |
|---|---|---|
| committer | Simon Horman <horms+renesas@verge.net.au> | 2014-07-09 10:55:57 +0200 |
| commit | 6b32fafee2bb5fcf0b3d3d04a9762d3a0212089e (patch) | |
| tree | 150c5661c704174150299b62b82b10f704353934 /drivers/dma/sh/shdmac.c | |
| parent | 7171511eaec5bf23fb06078f59784a3a0626b38f (diff) | |
| download | linux-6b32fafee2bb5fcf0b3d3d04a9762d3a0212089e.tar.gz | |
dmaengine: shdma: Add more register documentation
Also add a few definitions that were missing. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'drivers/dma/sh/shdmac.c')
| -rw-r--r-- | drivers/dma/sh/shdmac.c | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/drivers/dma/sh/shdmac.c b/drivers/dma/sh/shdmac.c index 146d5df926db..1a6f6595c6c1 100644 --- a/drivers/dma/sh/shdmac.c +++ b/drivers/dma/sh/shdmac.c @@ -38,12 +38,12 @@ #include "../dmaengine.h" #include "shdma.h" -/* DMA register */ -#define SAR 0x00 -#define DAR 0x04 -#define TCR 0x08 -#define CHCR 0x0C -#define DMAOR 0x40 +/* DMA registers */ +#define SAR 0x00 /* Source Address Register */ +#define DAR 0x04 /* Destination Address Register */ +#define TCR 0x08 /* Transfer Count Register */ +#define CHCR 0x0C /* Channel Control Register */ +#define DMAOR 0x40 /* DMA Operation Register */ #define TEND 0x18 /* USB-DMAC */ |