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author | Dan Williams <dan.j.williams@intel.com> | 2022-06-01 12:49:32 -0700 |
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committer | Dan Williams <dan.j.williams@intel.com> | 2022-07-10 12:10:07 -0700 |
commit | ee800010835db23c70acc01000f182955cab27a5 (patch) | |
tree | bb7678bc2cd22ea26b50b23f772d1124de3e61d9 /drivers/cxl/cxl.h | |
parent | 08f8d040a11d539481b9aee7b482430561281a28 (diff) | |
download | linux-ee800010835db23c70acc01000f182955cab27a5.tar.gz |
cxl/port: Cache CXL host bridge data
Region creation has need for checking host-bridge connectivity when adding endpoints to regions. Record, at port creation time, the host-bridge to provide a useful shortcut from any location in the topology to the most-significant ancestor. Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Link: https://lore.kernel.org/r/20220624041950.559155-4-dan.j.williams@intel.com Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Diffstat (limited to 'drivers/cxl/cxl.h')
-rw-r--r-- | drivers/cxl/cxl.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h index fd02f9e2a829..79d4c361b54f 100644 --- a/drivers/cxl/cxl.h +++ b/drivers/cxl/cxl.h @@ -282,6 +282,7 @@ struct cxl_nvdimm { * decode hierarchy. * @dev: this port's device * @uport: PCI or platform device implementing the upstream port capability + * @host_bridge: Shortcut to the platform attach point for this port * @id: id for port device-name * @dports: cxl_dport instances referenced by decoders * @endpoints: cxl_ep instances, endpoints that are a descendant of this port @@ -293,6 +294,7 @@ struct cxl_nvdimm { struct cxl_port { struct device dev; struct device *uport; + struct device *host_bridge; int id; struct list_head dports; struct list_head endpoints; |