diff options
| author | Tomasz Figa <t.figa@samsung.com> | 2013-04-04 13:33:37 +0900 |
|---|---|---|
| committer | Kukjin Kim <kgene.kim@samsung.com> | 2013-04-04 15:51:16 +0900 |
| commit | 0f1fce908efb2aa76b713d424b422f117376a04a (patch) | |
| tree | 4425cf6d556b872f90cf5aef69be6382ef7efecf /drivers/clk | |
| parent | 017ab64bdbca6f2f421d59a8235cdee90da08463 (diff) | |
| download | linux-0f1fce908efb2aa76b713d424b422f117376a04a.tar.gz | |
clk: exynos4: Remove SoC-specific registers from save list
Current clock save list is shared for all Exynos4 SoCs, so it must contain only registers present in all supported SoCs, because accessing unavailable registers might have undefined effect. This patch removes registers specific for particular SoCs from shared save list, as they should be supported by separate SoC-specific lists. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Diffstat (limited to 'drivers/clk')
| -rw-r--r-- | drivers/clk/samsung/clk-exynos4.c | 16 |
1 files changed, 0 insertions, 16 deletions
diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c index 5e26d5d0d8a3..7ae0a0560354 100644 --- a/drivers/clk/samsung/clk-exynos4.c +++ b/drivers/clk/samsung/clk-exynos4.c @@ -172,27 +172,21 @@ enum exynos4_clks { */ static __initdata unsigned long exynos4_clk_regs[] = { SRC_LEFTBUS, - E4X12_GATE_IP_IMAGE, GATE_IP_RIGHTBUS, - E4X12_GATE_IP_PERIR, SRC_TOP0, SRC_TOP1, SRC_CAM, SRC_TV, SRC_MFC, SRC_G3D, - E4210_SRC_IMAGE, SRC_LCD0, - SRC_LCD1, SRC_MAUDIO, SRC_FSYS, SRC_PERIL0, SRC_PERIL1, - E4X12_SRC_CAM1, SRC_MASK_CAM, SRC_MASK_TV, SRC_MASK_LCD0, - SRC_MASK_LCD1, SRC_MASK_MAUDIO, SRC_MASK_FSYS, SRC_MASK_PERIL0, @@ -204,8 +198,6 @@ static __initdata unsigned long exynos4_clk_regs[] = { DIV_G3D, DIV_IMAGE, DIV_LCD0, - E4210_DIV_LCD1, - E4X12_DIV_ISP, DIV_MAUDIO, DIV_FSYS0, DIV_FSYS1, @@ -217,24 +209,16 @@ static __initdata unsigned long exynos4_clk_regs[] = { DIV_PERIL3, DIV_PERIL4, DIV_PERIL5, - E4X12_DIV_CAM1, GATE_SCLK_CAM, GATE_IP_CAM, GATE_IP_TV, GATE_IP_MFC, GATE_IP_G3D, - E4210_GATE_IP_IMAGE, GATE_IP_LCD0, - GATE_IP_LCD1, - E4X12_GATE_IP_MAUDIO, GATE_IP_FSYS, GATE_IP_GPS, GATE_IP_PERIL, - GATE_IP_PERIR, - E4X12_MPLL_CON0, - E4X12_SRC_DMC, APLL_CON0, - E4210_MPLL_CON0, SRC_CPU, DIV_CPU0, }; |