diff options
| author | Dmitry Baryshkov <dmitry.baryshkov@linaro.org> | 2022-05-21 03:53:37 +0300 |
|---|---|---|
| committer | Bjorn Andersson <bjorn.andersson@linaro.org> | 2022-05-23 12:26:13 -0500 |
| commit | 720e14f3281731e3f606f65bbee32f95d2cd3f64 (patch) | |
| tree | 2a80068a6424ad7efaeccd529cdff70342a76e00 /drivers/clk | |
| parent | dd6456e6c4d8e384226a2f6d87801db15eeb24b0 (diff) | |
| download | linux-720e14f3281731e3f606f65bbee32f95d2cd3f64.tar.gz | |
Revert "clk: qcom: gcc-sc7280: use new clk_regmap_mux_safe_ops for PCIe pipe clocks"
Johan Hovold has pointed out that there are several deficiencies and a race condition in the regmap_mux_safe ops that were merged. Revert the commit that switches gcc-sc7280 driver to use regmap_mux_safe. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Johan Hovold <johan+linaro@kernel.org> Tested-by: Reviewed-by: Johan Hovold <johan+linaro@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220521005343.1429642-3-dmitry.baryshkov@linaro.org
Diffstat (limited to 'drivers/clk')
| -rw-r--r-- | drivers/clk/qcom/gcc-sc7280.c | 6 |
1 files changed, 2 insertions, 4 deletions
diff --git a/drivers/clk/qcom/gcc-sc7280.c b/drivers/clk/qcom/gcc-sc7280.c index dafbbc8f3bf4..423627d49719 100644 --- a/drivers/clk/qcom/gcc-sc7280.c +++ b/drivers/clk/qcom/gcc-sc7280.c @@ -373,14 +373,13 @@ static struct clk_regmap_mux gcc_pcie_0_pipe_clk_src = { .reg = 0x6b054, .shift = 0, .width = 2, - .safe_src_parent = P_BI_TCXO, .parent_map = gcc_parent_map_6, .clkr = { .hw.init = &(struct clk_init_data){ .name = "gcc_pcie_0_pipe_clk_src", .parent_data = gcc_parent_data_6, .num_parents = ARRAY_SIZE(gcc_parent_data_6), - .ops = &clk_regmap_mux_safe_ops, + .ops = &clk_regmap_mux_closest_ops, }, }, }; @@ -389,14 +388,13 @@ static struct clk_regmap_mux gcc_pcie_1_pipe_clk_src = { .reg = 0x8d054, .shift = 0, .width = 2, - .safe_src_parent = P_BI_TCXO, .parent_map = gcc_parent_map_7, .clkr = { .hw.init = &(struct clk_init_data){ .name = "gcc_pcie_1_pipe_clk_src", .parent_data = gcc_parent_data_7, .num_parents = ARRAY_SIZE(gcc_parent_data_7), - .ops = &clk_regmap_mux_safe_ops, + .ops = &clk_regmap_mux_closest_ops, }, }, }; |