diff options
| author | Nicolin Chen <nicoleotsuka@gmail.com> | 2020-10-28 17:48:20 -0700 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2020-11-20 17:19:46 +0100 |
| commit | 6160aca443148416994c022a35c77daeba948ea6 (patch) | |
| tree | b3a9450ab0369f2901aa17e19200bbaa0a3362f9 /drivers/clk | |
| parent | 3650b228f83adda7e5ee532e2b90429c03f7b9ec (diff) | |
| download | linux-6160aca443148416994c022a35c77daeba948ea6.tar.gz | |
clk: tegra: Do not return 0 on failure
Return values from read_dt_param() will be either TRUE (1) or
FALSE (0), while dfll_fetch_pwm_params() returns 0 on success
or an ERR code on failure.
So this patch fixes the bug of returning 0 on failure.
Fixes: 36541f0499fe ("clk: tegra: dfll: support PWM regulator control")
Cc: <stable@vger.kernel.org>
Signed-off-by: Nicolin Chen <nicoleotsuka@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'drivers/clk')
| -rw-r--r-- | drivers/clk/tegra/clk-dfll.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/clk/tegra/clk-dfll.c b/drivers/clk/tegra/clk-dfll.c index cfbaa90c7adb..a5f526bb0483 100644 --- a/drivers/clk/tegra/clk-dfll.c +++ b/drivers/clk/tegra/clk-dfll.c @@ -1856,13 +1856,13 @@ static int dfll_fetch_pwm_params(struct tegra_dfll *td) &td->reg_init_uV); if (!ret) { dev_err(td->dev, "couldn't get initialized voltage\n"); - return ret; + return -EINVAL; } ret = read_dt_param(td, "nvidia,pwm-period-nanoseconds", &pwm_period); if (!ret) { dev_err(td->dev, "couldn't get PWM period\n"); - return ret; + return -EINVAL; } td->pwm_rate = (NSEC_PER_SEC / pwm_period) * (MAX_DFLL_VOLTAGES - 1); |