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| author | Peter De Schrijver <pdeschrijver@nvidia.com> | 2017-02-28 16:37:21 +0200 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2017-03-20 14:07:33 +0100 |
| commit | e827ba1840bc6a9540deb81c6df6943a19e0e891 (patch) | |
| tree | 17c61ab18ac405e8cfb52930787367f285e16f73 /drivers/clk/tegra/clk.h | |
| parent | 6cfc8bc9ee66677fbd1b3331167d6f520e30b6fd (diff) | |
| download | linux-e827ba1840bc6a9540deb81c6df6943a19e0e891.tar.gz | |
clk: tegra: Add super clock mux/divider
Add a super clock type which implements both mux and divider. This is used for aclk. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com> Tested-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'drivers/clk/tegra/clk.h')
| -rw-r--r-- | drivers/clk/tegra/clk.h | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h index 8b09021eee00..960e47e41fdf 100644 --- a/drivers/clk/tegra/clk.h +++ b/drivers/clk/tegra/clk.h @@ -686,6 +686,8 @@ struct tegra_periph_init_data { struct tegra_clk_super_mux { struct clk_hw hw; void __iomem *reg; + struct tegra_clk_frac_div frac_div; + const struct clk_ops *div_ops; u8 width; u8 flags; u8 div2_index; @@ -702,7 +704,10 @@ struct clk *tegra_clk_register_super_mux(const char *name, const char **parent_names, u8 num_parents, unsigned long flags, void __iomem *reg, u8 clk_super_flags, u8 width, u8 pllx_index, u8 div2_index, spinlock_t *lock); - +struct clk *tegra_clk_register_super_clk(const char *name, + const char * const *parent_names, u8 num_parents, + unsigned long flags, void __iomem *reg, u8 clk_super_flags, + spinlock_t *lock); /** * struct clk_init_table - clock initialization table * @clk_id: clock id as mentioned in device tree bindings |