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| author | Thierry Reding <treding@nvidia.com> | 2015-03-23 10:52:45 +0100 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2015-04-10 16:04:20 +0200 |
| commit | 699b477a0d3a5bc68034a1520a4337ea0a20f63b (patch) | |
| tree | cbd74f6791b022d63f8b556b042afde65f006d18 /drivers/clk/tegra/clk.c | |
| parent | 5e43e259171e1eee8bc074d9c44be434e685087b (diff) | |
| download | linux-699b477a0d3a5bc68034a1520a4337ea0a20f63b.tar.gz | |
clk: tegra: Add peripheral registers for bank Y
Tegra210 has an extra bank of peripheral clock registers. Add it to the generic peripheral clock code. Cc: Peter De Schrijver <pdeschrijver@nvidia.com> Cc: Prashant Gaikwad <pgaikwad@nvidia.com> Reviewed-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'drivers/clk/tegra/clk.c')
| -rw-r--r-- | drivers/clk/tegra/clk.c | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/drivers/clk/tegra/clk.c b/drivers/clk/tegra/clk.c index 7a1df61847fc..41cd87c67be6 100644 --- a/drivers/clk/tegra/clk.c +++ b/drivers/clk/tegra/clk.c @@ -30,6 +30,7 @@ #define CLK_OUT_ENB_V 0x360 #define CLK_OUT_ENB_W 0x364 #define CLK_OUT_ENB_X 0x280 +#define CLK_OUT_ENB_Y 0x298 #define CLK_OUT_ENB_SET_L 0x320 #define CLK_OUT_ENB_CLR_L 0x324 #define CLK_OUT_ENB_SET_H 0x328 @@ -42,6 +43,8 @@ #define CLK_OUT_ENB_CLR_W 0x44c #define CLK_OUT_ENB_SET_X 0x284 #define CLK_OUT_ENB_CLR_X 0x288 +#define CLK_OUT_ENB_SET_Y 0x29c +#define CLK_OUT_ENB_CLR_Y 0x2a0 #define RST_DEVICES_L 0x004 #define RST_DEVICES_H 0x008 @@ -50,6 +53,7 @@ #define RST_DEVICES_V 0x358 #define RST_DEVICES_W 0x35C #define RST_DEVICES_X 0x28C +#define RST_DEVICES_Y 0x2a4 #define RST_DEVICES_SET_L 0x300 #define RST_DEVICES_CLR_L 0x304 #define RST_DEVICES_SET_H 0x308 @@ -62,6 +66,8 @@ #define RST_DEVICES_CLR_W 0x43c #define RST_DEVICES_SET_X 0x290 #define RST_DEVICES_CLR_X 0x294 +#define RST_DEVICES_SET_Y 0x2a8 +#define RST_DEVICES_CLR_Y 0x2ac /* Global data of Tegra CPU CAR ops */ static struct tegra_cpu_car_ops dummy_car_ops; @@ -122,6 +128,14 @@ static struct tegra_clk_periph_regs periph_regs[] = { .rst_set_reg = RST_DEVICES_SET_X, .rst_clr_reg = RST_DEVICES_CLR_X, }, + [6] = { + .enb_reg = CLK_OUT_ENB_Y, + .enb_set_reg = CLK_OUT_ENB_SET_Y, + .enb_clr_reg = CLK_OUT_ENB_CLR_Y, + .rst_reg = RST_DEVICES_Y, + .rst_set_reg = RST_DEVICES_SET_Y, + .rst_clr_reg = RST_DEVICES_CLR_Y, + }, }; static void __iomem *clk_base; |