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author | Jerome Brunet <jbrunet@baylibre.com> | 2019-02-01 13:58:41 +0100 |
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committer | Neil Armstrong <narmstrong@baylibre.com> | 2019-02-02 17:43:32 +0100 |
commit | 889c2b7ec42b8d14d421541f0a3ae1238e34891e (patch) | |
tree | 50b87aee6330c788ac17929493973891586e1eaa /drivers/clk/meson/clk-regmap.h | |
parent | cb78ba76296efd145c50d943017d76a36544bb76 (diff) | |
download | linux-889c2b7ec42b8d14d421541f0a3ae1238e34891e.tar.gz |
clk: meson: rework and clean drivers dependencies
Initially, the meson clock directory only hosted 2 controllers drivers, for meson8 and gxbb. At the time, both used the same set of clock drivers so managing the dependencies was not a big concern. Since this ancient time, entropy did its job, controllers with different requirement and specific clock drivers have been added. Unfortunately, we did not do a great job at managing the dependencies between the controllers and the different clock drivers. Some drivers, such as clk-phase or vid-pll-div, are compiled even if they are useless on the target (meson8). As we are adding new controllers, we need to be able to pick a driver w/o pulling the whole thing. The patch aims to clean things up by: * providing a dedicated CONFIG_ for each clock drivers * allowing clock drivers to be compiled as a modules, if possible * stating explicitly which drivers are required by each controller. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Link: https://lkml.kernel.org/r/20190201125841.26785-5-jbrunet@baylibre.com
Diffstat (limited to 'drivers/clk/meson/clk-regmap.h')
-rw-r--r-- | drivers/clk/meson/clk-regmap.h | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/drivers/clk/meson/clk-regmap.h b/drivers/clk/meson/clk-regmap.h index e9c5728d40eb..b7a085bbf072 100644 --- a/drivers/clk/meson/clk-regmap.h +++ b/drivers/clk/meson/clk-regmap.h @@ -111,4 +111,19 @@ clk_get_regmap_mux_data(struct clk_regmap *clk) extern const struct clk_ops clk_regmap_mux_ops; extern const struct clk_ops clk_regmap_mux_ro_ops; +#define MESON_GATE(_name, _reg, _bit) \ +struct clk_regmap _name = { \ + .data = &(struct clk_regmap_gate_data){ \ + .offset = (_reg), \ + .bit_idx = (_bit), \ + }, \ + .hw.init = &(struct clk_init_data) { \ + .name = #_name, \ + .ops = &clk_regmap_gate_ops, \ + .parent_names = (const char *[]){ "clk81" }, \ + .num_parents = 1, \ + .flags = (CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED), \ + }, \ +} + #endif /* __CLK_REGMAP_H */ |