diff options
| author | Fabio Estevam <fabio.estevam@nxp.com> | 2017-05-15 08:55:05 -0300 |
|---|---|---|
| committer | Stephen Boyd <sboyd@codeaurora.org> | 2017-06-01 00:25:38 -0700 |
| commit | ad14972422899b620fb594789824f0871dfb788c (patch) | |
| tree | 949897fde1a7c049d9fd9ec8d2eb4255dcd65a78 /drivers/clk/imx/clk-pllv3.c | |
| parent | 9593f4f56cf5d1c443f66660a0c7f01de38f979d (diff) | |
| download | linux-ad14972422899b620fb594789824f0871dfb788c.tar.gz | |
clk: imx7d: Fix the powerdown bit location of PLL DDR
According to the MX7D Reference Manual the powerdown bit of CCM_ANALOG_PLL_DDRn register is bit 20, so fix it accordingly. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Reviewed-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Diffstat (limited to 'drivers/clk/imx/clk-pllv3.c')
| -rw-r--r-- | drivers/clk/imx/clk-pllv3.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/drivers/clk/imx/clk-pllv3.c b/drivers/clk/imx/clk-pllv3.c index f1099167ba31..0039b169364e 100644 --- a/drivers/clk/imx/clk-pllv3.c +++ b/drivers/clk/imx/clk-pllv3.c @@ -27,6 +27,7 @@ #define BM_PLL_POWER (0x1 << 12) #define BM_PLL_LOCK (0x1 << 31) #define IMX7_ENET_PLL_POWER (0x1 << 5) +#define IMX7_DDR_PLL_POWER (0x1 << 20) /** * struct clk_pllv3 - IMX PLL clock version 3 @@ -451,6 +452,10 @@ struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name, pll->ref_clock = 500000000; ops = &clk_pllv3_enet_ops; break; + case IMX_PLLV3_DDR_IMX7: + pll->power_bit = IMX7_ENET_PLL_POWER; + ops = &clk_pllv3_av_ops; + break; default: ops = &clk_pllv3_ops; } |