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| author | Babu Moger <babu.moger@oracle.com> | 2017-07-06 09:34:19 -0700 |
|---|---|---|
| committer | Helge Deller <deller@gmx.de> | 2017-07-31 17:51:27 +0200 |
| commit | 74ad3d28af2104b92dd83a43add79e6a8c45d8e2 (patch) | |
| tree | 9fcdbdacd85baf6fd8456c349110720b2ed74737 /drivers/clk/at91/clk-pll.c | |
| parent | 93964fd4ea6ab86a2d2853a9ae56ae0c24cbbe16 (diff) | |
| download | linux-74ad3d28af2104b92dd83a43add79e6a8c45d8e2.tar.gz | |
parisc: Define CONFIG_CPU_BIG_ENDIAN
While working on enabling queued rwlock on SPARC, found this following
code in include/asm-generic/qrwlock.h which uses CONFIG_CPU_BIG_ENDIAN
to clear a byte.
static inline u8 *__qrwlock_write_byte(struct qrwlock *lock)
{
return (u8 *)lock + 3 * IS_BUILTIN(CONFIG_CPU_BIG_ENDIAN);
}
Problem is many of the fixed big endian architectures don't define
CPU_BIG_ENDIAN and clears the wrong byte.
Define CPU_BIG_ENDIAN for parisc architecture to fix it.
Signed-off-by: Babu Moger <babu.moger@oracle.com>
Signed-off-by: Helge Deller <deller@gmx.de>
Diffstat (limited to 'drivers/clk/at91/clk-pll.c')
0 files changed, 0 insertions, 0 deletions