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author | Stefan Agner <stefan@agner.ch> | 2016-12-14 12:48:09 -0800 |
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committer | Dave Airlie <airlied@redhat.com> | 2017-03-10 11:10:49 +1000 |
commit | 53990e416bb7adaa59d045f325a47f31a11b75ee (patch) | |
tree | d87ea97b09ecedad96ffaf192c35dc1ee616517f /drivers/auxdisplay | |
parent | 10f2889ba35aeb251b9945ec4c461af8c124c41f (diff) | |
download | linux-53990e416bb7adaa59d045f325a47f31a11b75ee.tar.gz |
drm: mxsfb: fix pixel clock polarity
The DRM subsystem specifies the pixel clock polarity from a controllers perspective: DRM_BUS_FLAG_PIXDATA_NEGEDGE means the controller drives the data on pixel clocks falling edge. That is the controllers DOTCLK_POL=0 (Default is data launched at negative edge). Also change the data enable logic to be high active by default and only change if explicitly requested via bus_flags. With that defaults are: - Data enable: high active - Pixel clock polarity: controller drives data on negative edge Signed-off-by: Stefan Agner <stefan@agner.ch> Acked-by: Marek Vasut <marex@denx.de> Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers/auxdisplay')
0 files changed, 0 insertions, 0 deletions